JPS61255051A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce element effective area and to improve high-resistance layer controllability by a method where in a lamination constituted of a tantalum film to serve as a stopper and a tantalum oxide film to serve as a high- resistance layer is formed on a part of the source or drain electrode of a Schottky gate FET. CONSTITUTION:On a semi-insulating GaAs substrate 1, an n-type enhancement layer 2 is formed, for the building of a gate electrode 5, source and drain ohmic electrodes 3 and 4, for a Schottky gate FET. An insulating film 6 is formed made of CVD-SiO2 or the like, whereafter an opening is provided in the insulating film 6 for the source ohmic electrode 3. Next, the entirety of the substrate 1 is covered with a tantalum oxide film (element high-resistance section) 8. The formation of the required thickness of a tantalum film 7. A source electrode 10 and a drain electrode 11 are then formed respectively by photolighography and by reactive dry etching. This design reduces element effective area and improves the controllability of its high-resistance layer.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a single-junction type compound semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that achieves high-density packaging by extremely reducing the effective area of elements. .

(Prior Art) Recently, compound semiconductor devices, l! ! l1cGakB Sirotki junction field effect transistor (hereinafter referred to as GaAsMES)
Compound semiconductor integrated circuits that use heterojunctions such as FETs and GaAJAs are known for their high speed.

It is attracting attention due to its low power consumption and resistance to radiation damage, and is being actively developed. Compound semiconductor integrated circuit devices at the single-unit level (SSI level) have higher electron mobility than silicon devices, can provide so-called semi-insulating substrates of 10'Ω-2 or more, and have simple device structures. Therefore, its high speed, low power consumption, etc. are being proven. However, when moving from a medium-scale integrated circuit to a large-scale integrated circuit with several hundred to several thousand elements, or even a single element, the gain of the GaAs MESFET itself is smaller than that of a silicon bipolar transistor or the like.

If the wiring capacitance increases or the fan-out increases, the high-speed performance of a highly integrated circuit device will be rapidly impaired.

In order to solve these problems, for example, methods of manufacturing high mutual conductance elements are used to improve the performance of the single element itself, and studies from the circuit aspect are also being actively conducted.

There are circuits shown in FIGS. 5(a) to 5(d) as gate circuits constructed using this GaAs MESFET.

In the figure, FIG. 5(a) shows a buffered PET logic circuit (BFL: Buffer
edFET Logic), in Figure 5) are the same and depress! 1! FF1tT, type 2 [(Vnn, -Vs
s) FET logic circuit using 5chottky diodes (5DFT; 5chottky DiOdes)
FBT LogiC).

Figure 5 (C) shows enhancement and depression type F.
'Low Pinchoff PgT logic circuit using one power supply using ET, (LPFL;
gic), Figure 5) uses enhancement type FETs to create a direct coupled F'ET logic circuit (DCF) consisting of one power supply.
L; Direct Coupled FET Lo
gic) There is.

Among these circuits, the DCFL circuit shown in FIG. 5(d) is suitable for high integration because it has a simple circuit configuration using a single power supply, consumes little power, and occupies a small area. Generally, among DCFL circuits, E/D gate circuits use normally-on FETs as loads.

That is, the DCFL circuit using a normally-off FET for driving a normally-on FET as the load shown in FIG. 5(d) can have a smaller element area than the E/R gate circuit using a high resistance as the load, and This method has been studied exclusively because of the difficulty in controlling the high resistance layer in the conventional method.

To manufacture these integrated circuits on compound semiconductor substrates, ion implantation is used, which allows for high uniformity and optimization of each device.However, commonly used ion implantation and device manufacturing techniques So, for example, Ga containing Mg
It is extremely difficult to manufacture an integrated circuit using an E/D gate circuit using a 5FET enhancement type FBT and a depressing type FET by controlling the pinch-off voltage within a desired range, and even if control is possible, However, the device occupies a large area, and it is difficult to prevent defects and characteristic deterioration based on uniformity within the chip.

Furthermore, even if an E/F gate circuit is manufactured in the same way, in order to control and manufacture a high resistance layer on a GaAs substrate, surface depletion, which is a problem specific to compound semiconductors such as Gaps, must be avoided. There are problems with layer shadows and electron velocity saturation (in GaAs, if an electric field of about 3KV/cm is applied, it will no longer function as a resistance element), and it is difficult to control the high resistance layer and reduce the resistance area. has extraordinary problems and limitations.

(Objective of the Invention) The object of the present invention is to provide a semiconductor integrated circuit that can extremely reduce the element area in such E/R gate circuits, have good controllability of the high resistance layer, and avoid problems specific to GaAs crystals. Our goal is to provide the following.

(Structure of the Invention) The structure of the semiconductor integrated circuit of the present invention is such that in a partial region on the source electrode or the drain electrode of the field effect transistor,
The tantalum oxide film is used as a high-resistance conductive film, and the tantalum metal film and high-resistance layer are used as a stopper layer to prevent mutual reactions with the underlying electrode during high-temperature heat treatment and allow each device to function stably. By forming a multilayer structure of tantalum oxide films, the effective area of the device can be reduced, and for example, in an E/R type gate circuit, it is possible to construct a circuit with an area equivalent to an enhancement type FBT. shall be.

(Principle of the Invention) Generally, a tantalum oxide film is used as a high dielectric constant insulating film. This tantalum oxide film can be deposited by sputtering tantalum metal in an oxygen atmosphere using reactive DC sputtering. In this case, the relationship between the deposition rate and oxygen partial pressure is as shown in Figure 2.
There is a critical oxygen partial pressure at which the deposition rate rapidly decreases at a predetermined oxygen partial pressure (A). This critical oxygen partial pressure A varies depending on the type and shape of the deposition apparatus and deposition conditions 1, such as substrate heating temperature, argon flow rate, power, etc.

In general, a tantalum oxide film deposited at an oxygen partial pressure lower than this critical oxygen intrusion has less oxygen than the stoichiometric composition of an insulator, so it functions as a high-resistance material rather than an insulator.

The present invention uses such a tantalum oxide film as a high resistance material as a vertical resistance element in a GaAs MESFET.
By configuring the source electrode or drain electrode on the source or drain electrode, Ga
Problems specific to As compound semiconductors can be eliminated, the area occupied by the device can be extremely reduced, and circuit configurations such as DCFLs on a highly integrated scale can be advantageously arranged.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(f) show an example of the present invention in the order of manufacturing steps of a GaAs MESFBT of an E/R type gate circuit.
FIG.

First, as shown in FIG. 1(a), an n-type enhancement layer is formed on a semi-insulating GaAs substrate 1.
t) Layer 2 is provided, and the gate electrode 5 and source and drain ohmic contact layers 3 and 4 (for example, input U G e/N i, etc.) of the enhancement type switching gate FBT are provided.
is formed. Next, as shown in FIG. 1(b), CV
An insulating film 6 made of D SiOz or the like is coated, and holes are formed in the insulating film 6 only in the source and the cathode portions 3 by the commonly used photolithography and insulating film etching methods. next.

A high-resistance tantalum oxide film 8 is deposited on the entire surface of the substrate at a desired oxygen partial pressure (for example, below the critical oxygen partial pressure) as shown in FIG. At this time, first, tantalum metal film 7 is deposited to a desired thickness, and then tantalum oxide film 8 is deposited to a desired thickness.

This is followed by photolithography and reactive dry etching, such as Freon gas, as shown in FIG. 1C.

The ohmic electrode 3 is etched with a mixed gas containing a small amount of oxygen in Freon gas, as shown in Figure 1 (d).
A tantalum film and an oxide film 7.8 are obtained on top.

Thereafter, as shown in FIG. 1(e), in order to form the upper electrode, source electrode 10, and drain electrode 11 of the high-resistance element, holes are made in the insulating film 6 in the same manner as in the conventional method. The cross-sectional view of the element in this case is as shown in Fig. 1(e), but E/R
A plan view of the fi gate circuit is shown in FIG. 3, for example.

Next, electrode metals such as titanium (Ti), platinum, gold, etc. are deposited as the source and drain electrodes 10.11 and the upper electrodes of the high-resistance elements by a sputtering method, etc., and then photolithography and ion deposition are carried out using the conventional photolithography method. Etching is performed using a cylindrical method or the like to form the structure shown in FIG. 1(f).

As explained above, according to the present invention, the high resistance element is not used as a planar resistance element, but is used as a vertical element, with the electrode between both terminals partially sharing the source or drain electrode of the FET element. The E/R type DCF has an extremely small effective area and avoids problems such as the effect of the surface depletion layer and the electron velocity saturation phenomenon that are unique to GaAs.
L circuits can be manufactured.

In addition, when forming a vertical high resistance element of the multilayer film (7, 8), after forming the tantalum film 7,
A tantalum oxide film formed by heat treatment for a predetermined time in an oxidizing atmosphere at 0°C also deviates from its stoichiometric composition as a dielectric and becomes an oxide with an excess of tantalum metal, so it cannot be used as a high-resistance material. Function.

(Effects of the Invention) According to the present invention, the effective area of a device can be reduced by about 50% for a unit gate compared to the case of using a conventional ElD type DCFL circuit, and static memory etc. can be reduced by about 50% as shown in FIG. If a cell is formed with a similar circuit configuration, 30 to 50%
Its effective area will be reduced.

Furthermore, the present invention is applicable not only to DCFL circuits based on compound semiconductor integrated circuits including GaAs of this embodiment (but also to analog ICs, and is not limited to compound semiconductor integrated circuits, but also silicon MO8ICs, silicon bipolar LCs). It can also be applied to the case where the area occupied by a high resistance element is reduced and integrated.

[Brief explanation of the drawing]

Figures 1 (a) to (e) are cross-sectional views of an element showing an example of the present invention in the order of manufacturing steps, and Figure 2 is a characteristic showing the relationship between oxygen partial pressure and deposition rate in the process of Figure 1. 3 is a plan view of the E/R type gate circuit in FIG. 1, FIG. 4 is a circuit diagram of a static memory used as the circuit in FIG. 1, and FIGS. 5(a) to (d) ) are various circuit diagrams of general gate circuits. In the figure, 1... Semi-insulating GaA
s substrate, 2...nli enhancement layer, 3
......Source ohmic electrode, 4...Drain ohmic electrode, 5...Gate electrode. 6... Insulating film such as CVD8i0z, 7...
... Tantalum film, 8 ... Tantalum oxide film (high resistance element part), 9 ... Photoresist, 10.
... Source 1 and others, 11 ... Drain' hidden pole, 13 ... Source t = 11i11 hole, 14
. . . This is the drain electrode opening. ＾Behe scolding 悌 0 Abandonment million Vss Figure 5

Claims (1)

[Claims] A feature of the field effect transistor is that the effective area of the device is reduced by laminating a tantalum metal film that serves as a stopper layer and a tantalum oxide film that serves as a high resistance layer in a partial region on the source or drain electrode of the field effect transistor. semiconductor integrated circuits.