JPH04116875A - Superconducting element and its manufacture - Google Patents

Superconducting element and its manufacture

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Publication number
JPH04116875A
JPH04116875A JP2236534A JP23653490A JPH04116875A JP H04116875 A JPH04116875 A JP H04116875A JP 2236534 A JP2236534 A JP 2236534A JP 23653490 A JP23653490 A JP 23653490A JP H04116875 A JPH04116875 A JP H04116875A
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JP
Japan
Prior art keywords
superconducting
substrate
channel
thin film
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2236534A
Other languages
Japanese (ja)
Other versions
JP2641966B2 (en
Inventor
Takao Nakamura
孝夫 中村
Hiroshi Inada
博史 稲田
Michitomo Iiyama
飯山 道朝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
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Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2236534A priority Critical patent/JP2641966B2/en
Priority to CA002050731A priority patent/CA2050731C/en
Priority to EP91402384A priority patent/EP0477063B1/en
Priority to DE69123415T priority patent/DE69123415T2/en
Publication of JPH04116875A publication Critical patent/JPH04116875A/en
Application granted granted Critical
Publication of JP2641966B2 publication Critical patent/JP2641966B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To unnecessitate fine work technique, stabilize element performance, and improve reliability, by a method wherein a thinned part on the protruding part of a substrate, of an oxide superconducting thin film formed on the substrate provided with the protruding part, is made a superconducting channel. CONSTITUTION:A protruding part is formed on a substrate 5; a part of the substrate 5 is covered with photo resist 8; the surface is shaved by a dry etching method, and a protruding part 50 is formed. An oxide superconducting film is formed on the substrate 5, and a superconducting layer 1 is formed. The surface of said layer 1 is flattened, and the upper part of the protruding part 50 of the substrate 5 is thinly worked as follows; the superconducting layer 1 is so coated with photo resist 9 that the surface becomes flat, and the superconducting layer 1 is flattened by ion etching or the like until the thickness of a superconducting channel 10 on the protruding part 50 becomes 5nm. Next an insulating film 6 and a metal film 7 are laminated on the superconducting layer 1. Said laminated films are eliminated by etching, in the manner in which only the part on the superconducting channel 10 is left, and a gate electrode 4 is formed. Finally a source electrode 2 and a drain electrode 3 are formed on both sides of the gate electrode 4, thereby completing an element.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、超電導素子およびその作製方法に関する。よ
り詳細には、新規な構成の超電導素子およびその作製方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a superconducting element and a method for manufacturing the same. More specifically, the present invention relates to a superconducting element with a novel configuration and a method for manufacturing the same.

従来の技術 超電導を使用した代表的な素子に、ジョセフソン素子が
ある。ジョセフソン素子は、一対の超電導体をトンネル
障壁を介して結合した構成であり、高速スイッチング動
作が可能である。しかしながら、ジョセフソン素子は2
端子の素子であり、論理回路を実現するためには複雑な
回路構成になってしまう。
A Josephson device is a typical device using conventional technology superconductivity. A Josephson device has a configuration in which a pair of superconductors are coupled via a tunnel barrier, and is capable of high-speed switching operation. However, the Josephson element is 2
It is a terminal element and requires a complicated circuit configuration to realize a logic circuit.

一方、超電導を利用した3端子素子としては、超電導ベ
ーストランジスタ、超電導FET等がある。第3図に、
超電導ベーストランジスタの概念図を示す。第3図の超
電導ベーストランジスタは、超電導体または常電導体で
構成されたエミッタ21、絶縁体で構成されたトンネル
障壁22、超電導体で構成されたベース23、半導体ア
イソレータ24および常電導体で構成されたコレクタ2
5を積層した構成になっている。この超電導ベーストラ
ンジスタは、トンネル障壁22を通過した高速電子を利
用した低電力消費、高速動作の素子である。
On the other hand, three-terminal elements using superconductivity include superconducting base transistors, superconducting FETs, and the like. In Figure 3,
A conceptual diagram of a superconducting base transistor is shown. The superconducting base transistor shown in FIG. 3 is composed of an emitter 21 made of a superconductor or a normal conductor, a tunnel barrier 22 made of an insulator, a base 23 made of a superconductor, a semiconductor isolator 24, and a normal conductor. collector 2
It has a structure in which 5 layers are stacked. This superconducting base transistor is a low-power consumption, high-speed operation element that utilizes high-speed electrons that have passed through the tunnel barrier 22.

第4図に、超電導FETの概念図を示す。第4図の超電
導FETは、超電導体で構成されている超電導ソース電
極41および超電導ドレイン電極42が、半導体層43
上に互いに近接して配置されている。超電導ソース電極
41および超電導ドレイン電極42の間の部分の半導体
層43は、下側が大きく削られ厚さが薄くなっている。
FIG. 4 shows a conceptual diagram of a superconducting FET. In the superconducting FET of FIG. 4, a superconducting source electrode 41 and a superconducting drain electrode 42 made of a superconductor are connected to a semiconductor layer 43
are placed close to each other on top. The semiconductor layer 43 in the portion between the superconducting source electrode 41 and the superconducting drain electrode 42 has its lower side largely shaved and has a reduced thickness.

また、半導体層43の下側表面にはゲート絶縁膜46が
形成され、ゲート絶縁膜46上にゲート電極44が設け
られている。
Further, a gate insulating film 46 is formed on the lower surface of the semiconductor layer 43, and a gate electrode 44 is provided on the gate insulating film 46.

超電導FETは、超電導近接効果で超電導ソース電極4
1および超電導ドレイン電極42間の半導体層43を流
れる超電導電流を、ゲート電圧で制御する低電力消費、
高速動作の素子である。
A superconducting FET has a superconducting source electrode 4 due to the superconducting proximity effect.
1 and the superconducting current flowing through the semiconductor layer 43 between the superconducting drain electrode 42 by controlling the superconducting current with a gate voltage;
It is a high-speed operating element.

さらに、ソース電極、ドレイン電極間に超電導体でチャ
ネルを形成し、この超電導チャネルを流れる電流をゲー
ト電極に印加する電圧で制御する3端子の超電導素子も
発表されている。
Furthermore, a three-terminal superconducting element has been announced in which a channel is formed between a source electrode and a drain electrode using a superconductor, and the current flowing through this superconducting channel is controlled by a voltage applied to a gate electrode.

発明が解決しようとする課題 上記の超電導ベーストランジスタおよび超電導FETは
、いずれも半導体層と超電導体層とが積層された部分を
有する。ところが、近年研究が進んでいる酸化物超電導
体を使用して、半導体層と超電導体層との積層構造を作
製することは困難である。また、この構造が作製できて
も半導体層と超電導体層の間の界面の制御が難しく、素
子として満足な動作をしなかった。
Problems to be Solved by the Invention The above-described superconducting base transistor and superconducting FET both have a portion in which a semiconductor layer and a superconductor layer are laminated. However, it is difficult to fabricate a stacked structure of a semiconductor layer and a superconductor layer using oxide superconductors, which have been studied in recent years. Moreover, even if this structure could be fabricated, it was difficult to control the interface between the semiconductor layer and the superconductor layer, and the device did not operate satisfactorily.

また、超電導FETは、超電導近接効果を利用するため
、超電導ソース電極41および超電導ドレイン電極42
を、それぞれを構成する超電導体のコヒーレンス長の数
倍程度以内に近接させて作製しなければならない。特に
酸化物超電導体は、コヒーレンス長が短いので、酸化物
超電導体を使用した場合には、超電導ソース電極41お
よび超電導ドレイン電極42間の距離は、数1On+n
程度にしなければならない。このような微細加工は非常
に困難であり、従来は酸化物超電導体を使用した超電導
FETを再現性よく作製できなかった。
Furthermore, in order to utilize the superconducting proximity effect, the superconducting FET has a superconducting source electrode 41 and a superconducting drain electrode 42.
must be made close to each other within several times the coherence length of the superconductor that constitutes each. In particular, since an oxide superconductor has a short coherence length, when an oxide superconductor is used, the distance between the superconducting source electrode 41 and the superconducting drain electrode 42 is several On+n.
It has to be moderate. Such microfabrication is extremely difficult, and conventionally it has not been possible to fabricate superconducting FETs using oxide superconductors with good reproducibility.

さらに、従来の超電導チャネルを有する超電導素子は、
変調動作は確認されたが、キャリア密度が高いため、完
全なオン/オフ動作ができなかった。酸化物超電導体は
、キャリア密度が低いので、超電導チャネルに使用する
ことにより、完全なオン/オフ動作を行う上記の素子の
実現の可能性が期待されている。しかしながら、超電導
チャネルは5nm程度の厚さにしなければならず、その
ような構成の実現することは困難であった。
Furthermore, superconducting devices with conventional superconducting channels are
Although modulation operation was confirmed, complete on/off operation was not possible due to the high carrier density. Since oxide superconductors have a low carrier density, it is expected that by using them for superconducting channels, it will be possible to realize the above-mentioned devices that perform perfect on/off operation. However, the thickness of the superconducting channel must be approximately 5 nm, making it difficult to realize such a configuration.

そこで本発明の目的は、上記従来技術の問題点を解決し
た、新規な構成の超電導素子およびその作製方法を提供
することにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a superconducting element having a novel configuration and a method for manufacturing the same, which solves the problems of the prior art described above.

課題を解決するための手段 本発明に従うと、基板上に成膜された酸化物超電導薄膜
に形成された超電導チャネルと、該超電導チャネルの両
端近傍に配置されて該超電導チャネルに電流を流すソー
ス電極およびドレイン電極と、前記超電導チャネル上に
配置されて該超電導チャネルに流れる電流を制御するゲ
ート電極を具備する超電導素子において、前記基板が突
出部を有し、前記酸化物超電導薄膜の前記突出部上の部
分が薄くされており、前記酸化物超電導薄膜の前記薄い
部分が、前記超電導チャネルであることを特徴とする超
電導素子が提供される。
Means for Solving the Problems According to the present invention, there are provided a superconducting channel formed in an oxide superconducting thin film formed on a substrate, and source electrodes disposed near both ends of the superconducting channel to flow current through the superconducting channel. and a superconducting element comprising a drain electrode and a gate electrode disposed on the superconducting channel to control a current flowing through the superconducting channel, wherein the substrate has a protrusion, and the substrate has a protrusion above the protrusion of the oxide superconducting thin film. There is provided a superconducting element characterized in that a portion of the oxide superconducting thin film is made thin, and the thin portion of the oxide superconducting thin film is the superconducting channel.

また、本発明では、上記の超電導素子を作製する方法と
して、突出部が形成された絶縁体基板上または突出部が
形成され、且つ絶縁膜を表面に有する半導体基板上に酸
化物超電導薄膜を形成し、該薄膜表面を平坦にする工程
を含むことを特徴とする超電導素子の作製方法が提供さ
れる。
Furthermore, in the present invention, as a method for manufacturing the above superconducting element, an oxide superconducting thin film is formed on an insulating substrate on which a protrusion is formed or on a semiconductor substrate on which a protrusion is formed and has an insulating film on the surface. However, there is provided a method for manufacturing a superconducting element characterized by including a step of flattening the surface of the thin film.

作用 本発明の超電導素子は、酸化物超電導体による超電導チ
ャネルと、超電導チャネルに電流を流すソース電極およ
びドレイン電極と、超電導チャネルを流れる電流を制御
するゲート電極とを具備する。本発明の超電導素子では
、各電極は必ずしも超電導電極である必要がない。
Function The superconducting element of the present invention includes a superconducting channel made of an oxide superconductor, a source electrode and a drain electrode that allow current to flow through the superconducting channel, and a gate electrode that controls the current flowing through the superconducting channel. In the superconducting element of the present invention, each electrode does not necessarily have to be a superconducting electrode.

また、従来の超電導FETが、超電導近接効果を利用し
て半導体中に超電導電流を流すのに対し、本発明の超電
導素子では、主電流は超電導体中を流れる。従って、従
来の超電導FETを作製するときに必要な微細加工技術
の制限が緩和される。
Further, while conventional superconducting FETs use the superconducting proximity effect to cause a superconducting current to flow through the semiconductor, in the superconducting element of the present invention, the main current flows through the superconductor. Therefore, restrictions on microfabrication techniques required when manufacturing conventional superconducting FETs are relaxed.

超電導チャネルは、ゲート電極に印加された電圧で開閉
させるために、ゲート電極により発生される電界の方向
で、厚さが5nm程度でなければならない。本発明の主
眼は、このような極薄の超電導チャネルを実現すること
にある。本発明の超電導素子では、突出部を設けた基板
上に形成された酸化物超電導薄膜の、基板の突出部によ
り薄くなった部分を超電導チャネルとする。
The superconducting channel must be on the order of 5 nm thick in the direction of the electric field generated by the gate electrode in order to be opened and closed by the voltage applied to the gate electrode. The main focus of the present invention is to realize such an ultra-thin superconducting channel. In the superconducting element of the present invention, a portion of an oxide superconducting thin film formed on a substrate provided with a protrusion, which becomes thinner due to the protrusion of the substrate, serves as a superconducting channel.

突出部を設けた基板上に単に酸化物超電導薄膜を成長さ
せただけでは、突出部上にも同じ厚さの薄膜が形成され
るので、本発明の方法では薄膜を形成後薄膜表面を平坦
にし、薄膜の基板突出部上の部分を薄くする。
If an oxide superconducting thin film is simply grown on a substrate with protrusions, a thin film of the same thickness will be formed on the protrusions, so the method of the present invention flattens the thin film surface after forming the thin film. , the portion of the thin film above the substrate protrusion is thinned;

本発明の超電導素子において、絶縁体基板には、MgO
1SrTi03等の酸化物単結晶基板が使用可能である
。これらの基板上には、配向性の高い結晶からなる酸化
物超電導薄膜を成長させることが可能であるので好まし
い。
In the superconducting element of the present invention, the insulator substrate includes MgO
An oxide single crystal substrate such as 1SrTi03 can be used. These substrates are preferable because it is possible to grow an oxide superconducting thin film made of highly oriented crystals.

また、本発明の超電導素子には、Y−Ba −CuO系
酸化物超電導体、Bi −3r−Ca−Cu −0系酸
化物超電導体、TI −Ba−Ca−Cu −0系酸化
物超電導体等任意の酸化物超電導体を使用することがで
きる。
Further, the superconducting element of the present invention includes a Y-Ba-CuO-based oxide superconductor, a Bi-3r-Ca-Cu-0-based oxide superconductor, and a TI-Ba-Ca-Cu-0-based oxide superconductor. Any oxide superconductor can be used.

以下、本発明を実施例により、さらに詳しく説明するが
、以下の開示は本発明の単なる実施例に過ぎず、本発明
の技術的範囲をなんら制限するものではない。
EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

実施例 第1図に、本発明の超電導素子の断面図を示す。Example FIG. 1 shows a cross-sectional view of the superconducting element of the present invention.

第1図の超電導素子は、突出部50を有する基板5上に
表面が平坦に形成された超電導層1を有する。
The superconducting element shown in FIG. 1 has a superconducting layer 1 having a flat surface formed on a substrate 5 having a protrusion 50. The superconducting element shown in FIG.

超電導層10基板5の突出部50の上の部分は、薄くな
っており超電導チャネル10になっている。超電導チャ
ネル10の上にはゲート電極4が配置され、超電導層1
上の超電導チャネル10の両側には、ソース電極2およ
びドレイン電極3が配置されている。
The portion of the superconducting layer 10 above the protrusion 50 of the substrate 5 is thinned to form a superconducting channel 10 . A gate electrode 4 is arranged on the superconducting channel 10 and the superconducting layer 1
On both sides of the upper superconducting channel 10, a source electrode 2 and a drain electrode 3 are arranged.

第2図を参照して、本発明の超電導素子を本発明の方法
で作製する手順を説明する。まず、第2図(a)に示す
ような基板5に突出部を形成する。基板5としては、M
g0(100)基板、5rT103(100)基板等の
絶縁体基板、または表面に絶縁膜を有する81等の半導
体基板が好ましい。ただし、半導体基板を使用する場合
には、突出部を形成後、表面に絶縁膜を形成する。
Referring to FIG. 2, the procedure for manufacturing the superconducting element of the present invention using the method of the present invention will be described. First, a protrusion is formed on the substrate 5 as shown in FIG. 2(a). As the substrate 5, M
An insulating substrate such as a g0 (100) substrate or a 5rT103 (100) substrate, or a semiconductor substrate such as 81 having an insulating film on the surface is preferable. However, when a semiconductor substrate is used, an insulating film is formed on the surface after forming the protrusion.

次に、第2図(社)に示すよう、基板5の一部をフォト
レジスト8で被覆し、Arイオンエツチング等のドライ
エツチング法で表面を削り、突出部50を形成する。
Next, as shown in FIG. 2 (Corporation), a portion of the substrate 5 is covered with a photoresist 8, and the surface is etched using a dry etching method such as Ar ion etching to form a protrusion 50.

半導体基板を使用する場合は、結晶方向も重要であり、
上述のように手順も多少異なる。例えば、Si基板を使
用する場合、5i(100)面に対し、ゲート長手方向
、即ち、チャネルの電流の流れる方向に向かって垂直方
向が(110)面になるようフォトレジスト8を形成す
る。この81基板をKOHまたはAPW等のエツチング
液を使用してエツチングし、突出部50を形成する。こ
の基板の表面にCVD法でl!gA10*およびスパッ
タリング法でBat+03を連続して積層する。
When using a semiconductor substrate, the crystal orientation is also important.
As mentioned above, the steps are slightly different. For example, when using a Si substrate, the photoresist 8 is formed so that the (110) plane is perpendicular to the gate longitudinal direction, that is, the channel current flow direction, with respect to the 5i (100) plane. This 81 substrate is etched using an etching solution such as KOH or APW to form the protrusion 50. The surface of this substrate is coated with l! gA10* and Bat+03 are successively laminated using a sputtering method.

次に、第2図(C)に示すよう加工した基板5上に酸化
物超電導薄膜をオファクシススバッタリング法、反応性
蒸着法、MBE法、CVD法等の方法で成膜し、超電導
層1を形成する。酸化物超電導体としては、Y−Ba−
Cu−0系酸化物超電導体、B1−3r−Ca−Cu 
−0系酸化物超電導体、TI −BaCa−Cu−0系
酸化物超電導体が好ましく、C軸配向の薄膜とすること
が好ましい。これは、C軸配向の酸化物超電導薄膜は、
基板と平行な方向の臨界電流密度が大きいからである。
Next, an oxide superconducting thin film is formed on the processed substrate 5 as shown in FIG. form 1. As the oxide superconductor, Y-Ba-
Cu-0 based oxide superconductor, B1-3r-Ca-Cu
A -0-based oxide superconductor and a TI-BaCa-Cu-0 based oxide superconductor are preferred, and a C-axis oriented thin film is preferred. This means that the C-axis oriented oxide superconducting thin film is
This is because the critical current density in the direction parallel to the substrate is large.

超電導層1は、このままではどの部分もほぼ一定の厚さ
であるので、表面を平坦にし、基板5の突出部50の上
の部分を薄く加工する。そのために、第2図(diに示
すよう、超電導層1上にフォトレジスト9を表面が平ら
になるよう被覆する。そして、第2図(e)に示すよう
、突出部50の上の超電導チャネル10の厚さが5nm
になるまで^rイオンエツチング等で超電導層1を平坦
にする。
Since all parts of the superconducting layer 1 have a substantially constant thickness as it is, the surface is made flat and the part above the protrusion 50 of the substrate 5 is processed to be thin. For this purpose, as shown in FIG. 2(di), a photoresist 9 is coated on the superconducting layer 1 so that the surface is flat.Then, as shown in FIG. 10 thickness is 5nm
The superconducting layer 1 is made flat by ion etching or the like until it becomes ^r.

次に、超電導チャネル10上にゲート電極を作製する。Next, a gate electrode is fabricated on the superconducting channel 10.

ゲート電極は、絶縁体層上に金属層が積層された構造と
することが好ましい。従って、第2図(f)に示すよう
超電導層1上に絶縁膜6右よび金属膜7を積層する。絶
縁膜6にはMgO等酸化物超電導薄膜との界面で大きな
準位を作らない絶縁体を用いることが好ましく、金属膜
7にはAuまたはTI、W等の高融点金属、これらのシ
リサイドを用いることが好ましい。この積層された膜を
第2図(glに示すよう超電導チャネル10の上の部分
だけ残してエツチングにより除去し、ゲート電極4を形
成する。
The gate electrode preferably has a structure in which a metal layer is laminated on an insulator layer. Therefore, as shown in FIG. 2(f), an insulating film 6 and a metal film 7 are laminated on the superconducting layer 1. For the insulating film 6, it is preferable to use an insulator that does not create a large level at the interface with the oxide superconducting thin film, such as MgO, and for the metal film 7, use a high melting point metal such as Au, TI, or W, or a silicide thereof. It is preferable. This stacked film is removed by etching leaving only the portion above the superconducting channel 10, as shown in FIG. 2 (gl), to form the gate electrode 4.

最後に、ゲート電極40両側にやはり^Uでソース電極
2およびドレイン電極3を形成して、本発明の超電導素
子が完成する。
Finally, the source electrode 2 and drain electrode 3 are formed on both sides of the gate electrode 40, again using ^U, to complete the superconducting element of the present invention.

本発明の超電導素子を本発明の方法で作製すると、超電
導FETを作製する場合に要求される微細加工技術の制
限が緩和される。また、表面が平坦にできるので、後に
必要に応じ配線を形成することが容易になる。従って、
作製が容易であり、素子の性能も安定しており、再現性
もよい。
When the superconducting element of the present invention is manufactured by the method of the present invention, restrictions on microfabrication techniques required when manufacturing a superconducting FET are relaxed. Furthermore, since the surface can be made flat, it becomes easier to form wiring later as required. Therefore,
It is easy to manufacture, has stable device performance, and has good reproducibility.

発明の詳細 な説明したように、本発明の超電導素子は、超電導チャ
ネル中を流れる超電導電流をゲート電圧で制御する構成
となっている。従って、従来の超電導FETのように、
超電導近接効果を利用していないので微細加工技術が不
要である。また、超電導体と半導体を積層する必要もな
いので、酸化物超電導体を使用して高性能な素子が作製
できる。
As described in detail, the superconducting element of the present invention has a configuration in which the superconducting current flowing in the superconducting channel is controlled by the gate voltage. Therefore, like the conventional superconducting FET,
Since it does not utilize the superconducting proximity effect, microfabrication technology is not required. Furthermore, since there is no need to stack a superconductor and a semiconductor, high-performance devices can be manufactured using oxide superconductors.

本発明により、超電導技術の電子デバイスへの応用がさ
らに促進される。
The present invention further promotes the application of superconducting technology to electronic devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の超電導素子の概略図であり、第2図
は、本発明の方法により本発明の超電導素子を作製する
場合の工程を示す概略図であり、第3図は、超電導ベー
ストランジスタの概略図であり、 !4t!lは、超電導FETの概略図である。 〔主な参照番号〕 1・・・超電導層、 2・・・ソース電極、3・・・ド
レイン電極、
FIG. 1 is a schematic diagram of the superconducting device of the present invention, FIG. 2 is a schematic diagram showing the steps for producing the superconducting device of the present invention by the method of the present invention, and FIG. 3 is a schematic diagram of the superconducting device of the present invention. Schematic diagram of the base transistor, ! 4t! 1 is a schematic diagram of a superconducting FET. [Main reference numbers] 1... superconducting layer, 2... source electrode, 3... drain electrode,

Claims (2)

【特許請求の範囲】[Claims] (1)基板上に成膜された酸化物超電導薄膜に形成され
た超電導チャネルと、該超電導チャネルの両端近傍に配
置されて該超電導チャネルに電流を流すソース電極およ
びドレイン電極と、前記超電導チャネル上に配置されて
該超電導チャネルに流れる電流を制御するゲート電極を
具備する超電導素子において、前記基板が突出部を有し
、前記酸化物超電導薄膜の前記突出部上の部分が薄くさ
れており、前記酸化物超電導薄膜の前記薄い部分が、前
記超電導チャネルであることを特徴とする超電導素子。
(1) A superconducting channel formed in an oxide superconducting thin film formed on a substrate, a source electrode and a drain electrode arranged near both ends of the superconducting channel to flow a current through the superconducting channel, and a source electrode and a drain electrode arranged on the superconducting channel. In the superconducting element comprising a gate electrode disposed in the superconducting channel for controlling a current flowing through the superconducting channel, the substrate has a protrusion, a portion of the oxide superconducting thin film above the protrusion is thinned, and the substrate has a protrusion. A superconducting element, wherein the thin portion of the oxide superconducting thin film is the superconducting channel.
(2)請求項1に記載の超電導素子を作製する方法にお
いて、突出部が形成された絶縁体基板上または突出部が
形成され、且つ絶縁膜を表面に有する半導体基板上に酸
化物超電導薄膜を形成し、該薄膜表面を平坦にする工程
を含むことを特徴とする超電導素子の作製方法。
(2) In the method for producing a superconducting element according to claim 1, an oxide superconducting thin film is formed on an insulating substrate on which a protrusion is formed or on a semiconductor substrate on which a protrusion is formed and has an insulating film on its surface. 1. A method for producing a superconducting element, comprising the steps of forming a thin film and flattening the surface of the thin film.
JP2236534A 1990-09-06 1990-09-06 Superconducting element and fabrication method Expired - Lifetime JP2641966B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2236534A JP2641966B2 (en) 1990-09-06 1990-09-06 Superconducting element and fabrication method
CA002050731A CA2050731C (en) 1990-09-06 1991-09-05 Superconducting device having a reduced thickness of oxide superconducting layer and method for manufacturing the same
EP91402384A EP0477063B1 (en) 1990-09-06 1991-09-05 Superconducting device having a reduced thickness of oxide superconducting layer and method for manufacturing the same
DE69123415T DE69123415T2 (en) 1990-09-06 1991-09-05 Superconducting component with reduced thickness of the superconducting oxide layer and its production method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2236534A JP2641966B2 (en) 1990-09-06 1990-09-06 Superconducting element and fabrication method

Publications (2)

Publication Number Publication Date
JPH04116875A true JPH04116875A (en) 1992-04-17
JP2641966B2 JP2641966B2 (en) 1997-08-20

Family

ID=17002103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2236534A Expired - Lifetime JP2641966B2 (en) 1990-09-06 1990-09-06 Superconducting element and fabrication method

Country Status (1)

Country Link
JP (1) JP2641966B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02234479A (en) * 1989-03-07 1990-09-17 Nec Corp Superconducting device and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02234479A (en) * 1989-03-07 1990-09-17 Nec Corp Superconducting device and manufacture thereof

Also Published As

Publication number Publication date
JP2641966B2 (en) 1997-08-20

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