JP2643849B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing a semiconductor integrated circuit in which a plurality of field effect transistors (FETs) having different threshold voltages are integrated on the same semiconductor substrate. It is about.

[0002]

2. Description of the Related Art At present, compound semiconductor FETs such as GaAs
-Speed and low-power semiconductor integrated circuit (LSI)
) Are being actively researched and developed. In particular, in a digital type semiconductor integrated circuit of this kind, it is necessary to realize a threshold voltage with high accuracy and reproducibility and to form an FET having a small difference in threshold voltage at a high speed operation. This is extremely important for preventing malfunction and reducing power consumption.

Conventionally, high electron mobility transistors (HEMs)
In T), as a means for realizing different threshold voltages, changing the film thickness of the electron supply layer immediately below the gate electrode has been performed. For example, Japanese Patent Application Laid-Open No. 60-116177
And Japanese Patent Application Laid-Open No. Sho.
A multilayer film made of GaAs and AlGaAs is formed on an electron supply layer made of s, and a semiconductor layer in a gate formation region of an enhancement transistor is first dug down to a certain depth, and then a gate of an enhancement type transistor and a depletion type transistor is formed. A method has been proposed in which regions are simultaneously etched to form recesses of enhancement type transistors deeper. In these conventional examples, a difference in recess depth between the two transistors can be controlled with good controllability by utilizing a difference in etching rate between GaAs and AlGaAs.

[0004]

In a semiconductor integrated circuit, other circuits such as a memory may be mounted in addition to a logic circuit, and a transistor having a threshold value different from that of the logic circuit portion is provided in a drive circuit. There is a need to be able to form two or more transistors with different threshold values on the same substrate in order to meet various needs of integrated circuits, such as the need, or to increase design flexibility. . However, in the above-described conventional manufacturing method, although it is possible to manufacture two FETs having different threshold voltages, the FE having more different threshold voltages is used.
It is difficult to integrate T.

In the above-described conventional example, GaAs and AlG
Since the difference in the etching rate for different materials such as aAs is used, the etching start time and the time when the semiconductor layer actually starts to be etched may be different due to the difference in the surface state of these semiconductor layers. Controllability is not high. For this reason, there has been a problem that the variation of the threshold voltage is increased. Further, in the conventional example, there is a complicated process in that a multilayer film of AlGaAs and GaAs must be formed, and strict process control is required because the film thickness of AlGaAs directly appears in the difference in threshold value. There was also the problem of becoming.

The present invention has been made in view of such a situation, and an object of the present invention is to provide a semiconductor integrated circuit in which two or more FETs having different threshold voltages are integrated on the same substrate. And a threshold value can be realized with high accuracy and high reproducibility.

[0007]

To achieve the above object, according to the present invention, there are provided (1) a channel layer and a contour on a semi-insulating semiconductor substrate.
Growing a semiconductor layer containing transfected layer forming a protective layer thereon
A step you, (2) selectively etching said protective layer and the contact layer
Exposing a plurality of gate formation regions on the channel layer by removing the gate; and (3) covering only a part of the plurality of gate formation regions and a peripheral portion thereof with a mask. (4) a step of exposing to a processing atmosphere to change the surface of the gate forming region not covered with the mask to form a deteriorated layer in the region; (5) removing the deteriorated layer; and (6) Forming a Schottky barrier type gate electrode having a T-shaped cross section on each of the gate formation regions; and (7) at least the protective layer in the ohmic electrode formation region
Is removed, and a source / drain electrode is formed on the contact layer.
Forming an ohmic electrode to provide a method for manufacturing a semiconductor integrated circuit.

[0008]

According to the present invention, for example, a plurality of gate forming regions are exposed on the electron supply layer, and the semiconductor surface in the region not covered by the mask is converted into an altered layer (eg, an oxide layer) and removed. You. According to this method, since the thickness of the semiconductor layer to be removed is determined by the processing atmosphere (for example, plasma atmosphere), the thickness can be accurately controlled on the order of nm, and its reproducibility is maintained high. be able to. Therefore, according to the present invention, different threshold values can be realized by a simple method, the difference between the threshold values can be accurately controlled, and the difference between the threshold values can be reduced. It is possible to do. Therefore, according to the present invention, it is possible to provide a high-speed and low-power-consumption semiconductor integrated circuit while being able to meet various circuit configuration requirements.

[0009]

Next, embodiments of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIGS. 1A to 1F are process cross-sectional views showing main manufacturing steps of a first embodiment of the present invention. As shown in FIG. 1A, a semi-insulating GaAs substrate 1
An undoped GaAs layer having a thickness of about 500 nm is deposited on the GaAs buffer layer 01 to form a GaAs buffer layer 102. An undoped InGaAs channel layer 103 having a thickness of about 15 nm and a donor density of about 2 × 10 ¹⁸ cm ^-3 at a film thickness of about 35 nm n-type AlGaAs electron supply layer 104, donor density of about 4 × 10 ¹⁸ cm ^-3 with a thickness of about 50 nm n-type Ga
The As contact layers 105 are sequentially grown using a molecular beam epitaxy (MBE) method.

Next, the mask is partially masked with a photoresist (not shown), and boron is ion-implanted to form an element isolation region 1.
06 is formed. Subsequently, a SiO ₂ film having a thickness of about 300 nm is formed.
After depositing the film 107 by the thermal CVD method and patterning the photoresist 108 by the photolithography method, the SiO ₂ film 107 is dry-etched by using CF ₄ gas to form an opening having a width of about 0.5 μm. Form.

Thereafter, as shown in FIG.
₂ is deposited to a thickness of about 150 nm using a low pressure CVD method, and anisotropic dry etching using CF ₄ gas is performed to form a sidewall oxide film (thickness about 100 nm) 109. Next, as shown in FIG. 1C, BCl ₃ and SF ₆
By reactive ion etching using a mixed gas of
N-type GaAs contact layer 10 exposed on the surface of the opening
5 is selectively removed to form an n-type AlGaAs electron supply layer 10.
Openings 110 and 111 for exposing 4 to the surface are formed. At this stage, the first threshold voltage is determined.

Next, as shown in FIG. 1D, a gate forming region of the FET to be set to the first threshold voltage is masked with a photoresist 112. Thereafter, the surface of the n-type AlGaAs electron supply layer 104 exposed on the surface in a part of the gate formation region is oxidized by leaving the substrate in oxygen plasma for a certain period of time, for example, about 20 minutes to form a thin altered layer. In this case, it is necessary to set conditions so that the photoresist 112 is not completely ashed and removed by oxygen plasma. Next, the altered layer is removed by immersion in hydrochloric acid. At this stage, the second threshold voltage is determined.

Subsequently, an FET having a third threshold voltage
FETs with first and second threshold voltages to form
Is masked with a photoresist (not shown) to form an altered layer and remove it.
In order to form an FET having a threshold voltage of
The gate regions of the FETs having the second and third threshold voltages are masked with a photoresist (not shown) to form an altered layer and remove it.

Next, as shown in FIG. 1E, a WSi film 113 and a Ti / Pt /
An Au multilayer film 114 is deposited by a sputtering method, and is patterned using a photoresist mask to form a gate electrode. Next, as shown in FIG. 1F, an AuGe / Ni / Au multilayer film 115 is deposited using a photoresist as a mask, lift-off is performed, and an alloying process is performed. A drain electrode is formed.

According to this embodiment, -0.4 V, -0.15
FETs with four different threshold voltages of V, + 0.1V and + 0.35V were obtained. In addition, each standard deviation, despite the fact that the gate length is as fine as about 0.3 μm,
It was very small, 10 to 20 mV, and it was found that the reproducibility was high.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. FIGS. 2A to 2F are process cross-sectional views sequentially showing main manufacturing steps of the second embodiment of the present invention. First, as shown in FIG. 2A, a film thickness of about 500 nm is formed on a semi-insulating InP substrate 201.
Undoped AlInAs buffer layer 202 and undoped InGaAs channel layer 20 having a thickness of about 50 nm.
3. A donor density of about 3 × 10 ¹⁸ cm ^-3 and a film thickness of about 20 nm
AlInAs electron supply layer 204 composed of a two-layer film of an n-type AlInAs layer having a thickness of about 15 nm and an undoped AlInAs layer, an n-type InGaAs contact layer having a donor density of about 6 × 10 ¹⁸ cm ^-3 and a thickness of about 50 nm 205 are sequentially grown using molecular beam epitaxy.

Subsequently, the element isolation region 2 is partially masked with a photoresist (not shown) and ion-implanted with oxygen.
06 and then a SiN film 2 having a thickness of about 300 nm
07 is deposited by a plasma CVD method. Next, after patterning the photoresist 208 using a photolithography method, the SiN film 207 is dry-etched using a mixed gas of CF ₄ and SF ₆ to have a width of about 0.5.
An opening of μm is formed.

Thereafter, as shown in FIG.
₂ is deposited to a thickness of about 150 nm using a low pressure CVD method, and an anisotropic dry etching of the SiO ₂ film is performed using a CF ₄ gas to form a sidewall oxide film 209 having a thickness of about 100 nm.
To form Next, as shown in FIG. 2C, the n-type InGaAs contact layer 205 exposed on the surface of the opening is selectively removed by a reactive ion etching method using a mixed gas of Cl ₂ and He. Openings 210 and 211 for exposing the surface of the undoped layer of the AlInAs electron supply layer 204 are formed. At this stage, the first threshold voltage is determined.

Next, as shown in FIG. 2D, the gate region of the FET to be set to the first threshold voltage is masked with a photoresist 212. Thereafter, the substrate is left in a plasma of CCl ₂ F ₂ gas for a certain period of time, for example, about 10 minutes, and the AlInA exposed on the surface in a part of the gate formation region
The surface of the s-electron supply layer 204 is fluorinated to form a thin altered layer. Next, it is immersed in a buffered HF solution to remove the altered layer. At this stage, the second threshold voltage is determined.

Next, in order to form an FET having a third threshold voltage, the gate regions of the FETs having the first and second threshold voltages are masked with a photoresist (not shown). An altered layer is formed under the above conditions, and is removed. Next, as shown in FIG. 2E, a WSi film 213 and a Ti / Pt / Au multilayer film 214 are deposited as a metal film for the gate electrode by a sputtering method, and processed into a gate electrode using a photoresist mask. . Subsequently, as shown in FIG. 2F, AuGe is
After the / Ni / Au multilayer film 215 is deposited and lifted off, an alloying process is performed to form a source electrode and a drain electrode which are ohmic electrodes.

In the semiconductor integrated circuit formed by this embodiment, three different threshold voltages of -0.4 V, -0.1 V and +0.2 V were obtained. Also, each standard deviation is very small, 10 to 20 mV, despite the gate length being as fine as about 0.3 μm.
It was found that the uniformity was excellent.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, M
The present invention relates to a semiconductor integrated circuit having an ISFET. 3A to 3F are process cross-sectional views sequentially showing main manufacturing steps of the third embodiment of the present invention.

First, as shown in FIG. 3A, an undoped first GaAs buffer layer 302a having a thickness of about 500 nm and an undoped GaAs layer having a thickness of about 2 nm are formed on a semi-insulating Si substrate 301. 2 nm undoped Al
A total film thickness of about 400 nm formed by alternately growing GaAs layers
GaAs / AlGaAs buffer layer 302b of about 50 nm in thickness and undoped second GaAs buffer layer 302b
c, the donor density is about 3 × 10 ¹⁸ cm ^-3 and the film thickness is about 10 nm
An n-type GaAs channel layer 303, an undoped AlGaAs high-resistance layer 304 having a thickness of about 30 nm, and an n-type GaAs contact layer 305 having a donor density of about 5 × 10 ¹⁸ cm ^-3 and a thickness of about 50 nm, respectively. It grows sequentially using the method.

Next, the element isolation region 30 is partially masked with a photoresist (not shown) and ion-implanted with oxygen.
6 and then a SiON film 3 having a thickness of about 300 nm
07 is deposited by a plasma CVD method. Subsequently, after patterning the photoresist 308 using a photolithography method, the SiON film 307 is dry-etched using a mixed gas of CF ₄ and SF ₆ to have a width of about 0.3 mm.
An opening of 5 μm is formed.

Next, as shown in FIG.
₂ is deposited to a thickness of about 150 nm using a low pressure CVD method, and the SiO ₂ film is anisotropically dry-etched using CF ₄ gas to form a sidewall oxide film 30 having a thickness of about 100 nm.
9 is formed. Next, as shown in FIG.
_The n-type GaAs contact layer 305 exposed on the surface of the opening was selectively removed by a reactive ion etching method using a mixed gas of ₂ F ₂ and He, thereby exposing the surface of the AlGaAs high resistance layer 304. Openings 310 and 311
To form At this stage, the first threshold voltage is determined.

Next, as shown in FIG. 3D, a gate forming region of the FET to be set to the first threshold voltage is masked with a photoresist 312. After that, the surface of the AlGaAs high resistance layer 304 exposed in a part of the gate formation region is nitrided or oxidized by being left in a plasma of N ₂ O gas for a predetermined time, for example, about 10 minutes, to form a thin altered layer.

Next, the altered layer is immersed in acidic electrolytic ionized water to remove the altered layer. In this case, a small amount of an acidic liquid may be added to the ionic water. At this stage, the second threshold voltage is determined. Next, in order to form an FET having a third threshold voltage, the gate regions of the FETs having the first and second threshold voltages are masked with a photoresist (not shown). To form an altered layer and remove it.

Next, as shown in FIG. 3E, a WSi film 313 and a Ti / Pt /
An Au multilayer film 314 is deposited by a sputtering method and processed using a photoresist mask. Subsequently, as shown in FIG. 3 (f), the AuGe / N
After the i / Au multilayer film 315 is deposited and lifted off, an alloying process is performed to form a source electrode and a drain electrode which are ohmic electrodes.

In the semiconductor integrated circuit formed by this embodiment, three different threshold voltages of -0.4 V, -0.1 V, and +0.2 V were obtained. Also, each standard deviation is very small, 10 to 20 mV, despite the gate length being as fine as about 0.3 μm.
The uniformity was excellent. In this embodiment, acidic electrolytic ionized water is used for removing the deteriorated layer. However, alkaline electrolytic ionized water may be effective depending on the deteriorated layer.

While the preferred embodiment has been described above,
The present invention is not limited to these embodiments, and various modifications are possible. For example, GaS is used as a semiconductor material.
Other materials such as b, InSb, InAs, AlSb, and GaInP can be used. As a method of forming a semiconductor layer, a liquid phase growth method, an organic metal vapor phase growth method, an atomic layer growth method, or the like is used instead of the molecular beam epitaxy method. Can be used. Further, as the doping means, a doping method such as monoatomic layer (δ) doping or a structure having a doping region by this method can be adopted. Further, the channel layer may be formed by a method other than the epitaxial growth method such as an ion implantation method or a diffusion method. The present invention is also applicable to MES type FETs and hole channel FETs.

[0031]

As described above, in the method of manufacturing a semiconductor integrated circuit according to the present invention, after exposing the surfaces of a plurality of gate formation regions and masking some of the gate formation regions, the process is performed in a processing atmosphere. Since the surface of the gate forming region which is not masked is converted into an altered layer and removed, the semiconductor integrated circuit including FETs having two or more different threshold voltages can be easily formed. Become like Further, according to the present invention, since the thickness of the semiconductor layer to be removed from the gate formation region can be controlled accurately and with good reproducibility, the accuracy and reproducibility of the threshold value of each transistor can be improved. it can.

[Brief description of the drawings]

FIG. 1 is a process sectional view sequentially showing main manufacturing steps of a first embodiment of the present invention.

FIG. 2 is a process sectional view sequentially showing main manufacturing steps of a second embodiment of the present invention.

FIG. 3 is a process sectional view sequentially showing main manufacturing steps of a third embodiment of the present invention.

[Description of sign]

101 semi-insulating GaAs substrate 201 semi-insulating InP substrate 301 semi-insulating Si substrate 102 GaAs buffer layer 202 AlInAs buffer layer 302a first GaAs buffer layer 302b GaAs / AlGaAs buffer layer 302c second GaAs buffer layer 103, 203 InGaAs channel layer 303n -Type GaAs channel layer 104 n-type AlGaAs electron supply layer 204 AlInAs electron supply layer 304 AlGaAs high resistance layer 105, 305 n-type GaAs contact layer 205 n-type InGaAs contact layer 106, 206, 306 Device isolation region 107 SiO ₂ film 207 SiN film 307 SiON film 108, 112, 208, 212, 308, 312 Photoresist 109, 209, 309 Side wall oxide film 110, 111, 21 , 211,310,311 openings 113, 213, 313 WSi film 114,214,314 Ti / Pt / Au multilayer 115,215,315 AuGe / Ni / Au multilayer film

Claims (5)

(57) [Claims] 1. A (1) thereon is grown semiconductor layer including a channel layer and a contact layer on a semi-insulating semiconductor substrate
Selectively etching the steps that form a protective layer, the protective layer and the contact layer (2) to
Exposing a plurality of gate formation regions on the channel layer by removing the gate; and (3) covering only a part of the plurality of gate formation regions and a peripheral portion thereof with a mask. (4) a step of exposing to a processing atmosphere to change the surface of the gate forming region not covered with the mask to form a deteriorated layer in the region; (5) removing the deteriorated layer; and (6) Each of the gate forming regions has a T-shaped cross section.
Forming a type of Schottky barrier gate electrode, (7) at least the protective layer of the ohmic electrode formation region
Is removed, and a source / drain electrode is formed on the contact layer.
Forming an ohmic electrode to be a semiconductor integrated circuit. 2. The method according to claim 1, wherein each of the steps (3) to (5) is repeated a plurality of times. 3. The method according to claim 1, wherein the gate forming region is set on an electron supply layer or a high resistance layer formed on the channel layer. 4. The semiconductor integrated circuit according to claim 1, wherein the processing atmosphere in the step (4) is a plasma atmosphere containing one or more of oxygen, nitrogen and halogen elements. Production method. 5. The method according to claim 1, wherein, in the step (5), the altered layer is removed using electrolytic ion water.