KR950000869B1 - Fabricating method of mesfet - Google Patents

Abstract

The method includes the steps of forming a buffer layer (2), a channel layer (3) and a cap layer (4) on the substrate (1) to etch the layer (2) in a mesa structure forming a surface pasivation film (5) thereon to remove the film (5) on the source and drain formation area to form a source and drain metal region, selectively removing the portion between the source and drain regions to the layer (3) to form a 1st gate window (L1), forming an insulating layer on the side wall of the gate window, etching the channel layer (3) by using the side wall and a photoresist film (9) as a mask, and depositing a gate metal (8) to remove the photo-resist film (9) and the gate metal portion on the film (9) to form a gate, thereby using the sidew wall to obtain a short gate of 0.3-0.5 micron.

Description

Manufacturing method of MESFET

(A) through (e) of FIG. 1 are MESFET manufacturing process diagrams of a general double-etched T-shaped gate structure.

2 is an equivalent circuit diagram of a GaAs MESFET, in which (a) is a physical basis diagram of a circuit constant, and (b) is an equivalent circuit diagram.

Figure 3 (a) to (f) is a manufacturing process diagram of the MESFET of the present invention.

* Explanation of symbols for main parts of the drawings

1: semi-insulating substrate 2: high resistance beeper layer

3: n-channel layer 4: n + resistive layer cap layer

5: silicon nitride film 6: resistive metal layer

7: silicon oxide film 8: gate schottky metal layer

9: photosensitive film

The present invention relates to a method for manufacturing a MESFET (Metal Semiconductor Field Effec Transistor), which is a central element of MMIC of 1 GHZ or more, and in particular, a self-aligning process for simplifying the manufacturing process while satisfying the basic configuration requirements of the MESFET. It relates to a method for manufacturing a MESFET.

The MESFET is a transistor that modulates the amount of current flowing between the drain and the source by adjusting the width of the depletion region of the Schottky diode between the gate metal and the GaAs. There are single and double etching structures in the structure, and the gate metal is classified into a general type and a T shape.

(A) to (e) of FIG. 1 are manufacturing process diagrams of a general MESFET having a double etching structure and a T-shaped gate metal shape.

First, as in (a), a highly resistive buffer layer 2, n channel 3, and n + resistive cap layer 4, which are n- (p-) buffer layers, are epitaxially deposited on the semi-insulating substrate 1, as shown in (a). After this growth, electrical insulation is performed by mesa etching. (Mask 1)

Thereafter, as shown in (b), a protective film is formed on the entire surface of the silicon nitride film 5, and the source and drain regions are selectively etched.

Then, AuGe / Ni / Au is used to form a resistive metal layer of the source and drain portions to perform an alloying process (mask 2).

Then, as in (c), a recess etching process is performed in which the metal nitride film 5 and the n + resistive cap layer 4 between the source and drain regions are removed (mask 3), and then as in (d), After the SiO ₂ film 7 was applied and the gate forming portion was etched (mask 4), as in (e), the T-type gate Schottky metal layer 8 was formed by Ti / Pt / Au, Al, Ti / Al, or the like. Is defined.

(Mask 5)

As described above, in the conventional MESFET manufacturing method, all of the masks 3 to 4 require a very accurate alignment process, and the mask 3 has to align the line width of 1 μM with 3 μM between the source and the drain, and the mask 4 has 1 In the first recess etch portion of μM, a gate area of 0.5 μM should be defined, and mask 5 should define a 0.5 μM gate area to include a T-shaped gate of about 2 μM.

In general, the T-shaped gate shape is manufactured through an electron beam lithography process in which the electron beam is exposed by direct lighting. In this case, the number of masks can be reduced by one than in the above case, but this method is less productive and mass-produced. There is an unfavorable way.

In the manufacturing method of such a general MESFET has the following problems.

That is, the conventional method of manufacturing MESFET having a double etching structure and T-shaped gate metal shape is very difficult because the mask process must be at least five times, and in particular, the mask 3 and mask 4 processes require very accurate alignment, so the process margin is low. .

As a result, defective and undesired device characteristics can be obtained, thereby reducing reliability.

In addition, in order to solve this problem, the number of mask processes will be reduced even if a single structure is used instead of a multi-etch structure, but the output gate conductance and the capacitance between the gate and drain become larger among the elements of the equivalent circuit. Even in the same channel layer, the high frequency characteristic is weakened.

An object of the present invention is to provide a method for manufacturing a MESFET having a T-shaped gate structure which reduces the number of mask processes requiring difficult alignment and improves mass productivity.

The present invention for achieving the above object will be described in more detail with reference to the accompanying drawings.

3 (a) to (g) are cross-sectional views of the MESFET process according to the first embodiment of the present invention. The method of manufacturing the MESFET according to the first embodiment of the present invention is an epitaxial process to the semi-insulating substrate 1 as shown in FIG. The high-resistance buffer layer 2, the 7-channel channel layer 2, and the high-concentration n-type resistive cap layer 4, which are low concentration n-type (or p-type) buffer layers, are sequentially grown. After mesa etching with a predetermined thickness, a protective film is formed on the entire surface of the silicon nitride film 5, and the silicon nitride film 5 of the source and drain regions is selectively etched, and then source and drain regions are formed using AuGe / Ni / Au. Of the capping layer 4 to form a resistive metal layer (6).

The silicon nitride film 5 and the high concentration n-type resistive cap layer 4 between the source region and the drain region are formed in the n-type channel layer 3 by a photoetching process using a mask according to the conventional method as shown in FIG. 3 (b). The portion is selectively removed to form the gate window L ₁ .

As shown in FIG. 3 (c), the silicon nitride film 7 is deposited on the entire surface, and the silicon oxide film 7 side wall is formed on the sidewalls and mesa-etched portions of the gate window region by a reactive ion etching (RIE) process as shown in 3d. do.

As shown in FIG. 3 (e), the photoresist film 8 is deposited on the entire surface, and the photoresist film 9 is patterned by using a mask in which the gate window l ₁ is formed in FIG. To form, the n-type channel layer 3 is secondly etched to a predetermined depth using the photoresist film 9 and the sidewalls of the silicon oxide film 7 as masks.

As shown in FIG. 3 (f), the gate Schottky metal layer 8 is deposited on the entire surface, and the photosensitive film 9 and the metal layer 8 are selectively selected by a lift-off method as shown in FIG. 3 (g). Remove

Here, the lift-off method means a process of selectively removing the metal layer 8 above the photosensitive film 9 when the photosensitive film 9 is removed.

In the above manufacturing process, it is preferable to use CHF ₃ gas to etch the silicon oxide film 7 by the RIE method, and to use the PECVD method to deposit the silicon oxide film 7.

The reason is that the CHF ₃ gas has a higher etching rate for etching the silicon oxide film 5 than the rate for etching the silicon nitride film 5. This is because the sidewalls can be formed by etching 7).

In addition, the thickness of the final gate can be adjusted according to the thickness of the side wall of the silicon oxide film 7, and the thickness of the sidewall can be easily obtained in the range of 100 kPa to 2000 kPa.

That is, in FIG. 3 (b), when the length of the gate window L ₁ is obtained by about 0.5 to 0.7 μM by the photoetching process, the final gate length L ₂ is 0.3 to 0.5 μM.

Meanwhile, the same process as in the first embodiment of the present invention may be formed on the n + n / n- (p) buffer substrate by a method different from the first embodiment of the present invention. It can be applied to defining MESFETs or to FETs of hete and structure.

As described above, the MESFET manufacturing method of the present invention has the following effects.

First, as compared to the conventional manufacturing method, a small number of mask processes are required in the present invention, so that a difficult mask alignment operation is reduced.

Second, the gate length is defined at least about 0.5 to 0.7 μM because the gate length is defined by the photoetching process. However, in the present invention, the gate length actually obtained by using the sidewall is 0.3 to 0.5 even when the gate length is 0.5 to 0.7 μM. Since it is about M, a short gate length can be obtained to improve high frequency characteristics.

Claims (2)

Forming a buffer layer, a channel layer, and a cap layer on the substrate in order and mesa-etching a predetermined portion of the buffer layer; forming a surface protective film on the entire surface of the substrate; selectively removing the surface protective film of the source / drain forming region, and then removing the source Forming a primary gate window by selectively removing the source / drain regions to the channel layer, and etching back to deposit an insulating film on the front surface to form an insulating film sidewall on the sidewall of the gate window. Forming a photoresist film at a portion other than the gate window; etching the channel layer to a predetermined depth using the insulating film sidewalls and the photoresist film as a mask; depositing a gate metal on the entire surface and depositing a photoresist film by a lift-off method. And removing the gate metal on the photoresist layer to form a gate. Method of producing a MESFET, characterized by more than true. The method of claim 1, wherein the protective film is formed of a silicon nitride film, the insulating film is formed of a silicon oxide film, and CHF ₃ is used as an etching gas during the silicon oxide film RIE process.