KR950000157B1 - Manufacturing method of fet - Google Patents

Abstract

forming AlxGa1-xAs layer (24a) lattice-matched with a GaAs substrate (20); forming an n channel layer (22) in the substrate (20); forming an Al cap metal (25); etching the layer (24a) with the cap metal mask to form a photoresist pattern as an impurity implantation region pattern; forming an AlGaAs dummy gate (24) by using a mesa-etching; removing the pattern and the cap metal to form and aneal an oxide film thereon to activate the layers (24a,24); forming an opening part into the oxide film to form 1st and 2nd electrode (28) ohmic-contacted with the gate (24); removing the dummy gate (24) to form a mesa hole; and forming a gate electrode (32) into the hole thereby forming a dummy gate with fine line width to reduce the effective gate length.

Description

Manufacturing Method of Field Effect Transistor

1 is a cross-sectional view of a conventional metal-semiconductor field effect transistor.

2 is a manufacturing process diagram of the metal-semiconductor field effect transistor according to the embodiment of the present invention.

The present invention relates to a field effect transistor of a compound semiconductor, and more particularly, to a method of manufacturing an improved field effect transistor capable of operating at high speed by forming a self-alignment between components such as electrodes. .

Recently, GaAs process technology has been developed along with new semiconductor manufacturing technology and circuit design, enabling GaAs IC technology comparable to that of silicon (Si).

The development of the information society has demanded high performance semiconductor devices in the fields of high speed computers, high frequency and optical communication. Since there are technical limitations in satisfying such a necessity with conventional silicon (Si) devices, research on compound semiconductors having excellent material properties is being actively conducted.

Among the compound semiconductors, GaAs has three inherent advantages over Si. Because of the large electron mobility, the series resistance is reduced in a given device structure, and the device speed is improved because of the large drift speed in a given electric field. GaAs can be made of semi-insulating semiconductor substrate with matching lattice constant.

Various kinds of devices have been developed by using the excellent material properties of GaAs.

Some examples include metal-semiconductor field effect transistors (hereinafter referred to as MESFETs), heterojunction bipolar transistors, and high electron mobility transistors.

The most significant of these techniques is in the field of MESFETs, where multiple carriers transfer between metal-semiconductor contacts.

In general, a MESFET has source and drain electrodes on ohmic contacts on a semi-insulating GaAs substrate, and a gate electrode is Schottky contact on a channel layer formed between these electrodes. When a voltage is applied to the gate electrode, the thickness of the depletion region of the channel layer changes according to the intensity of the applied voltage, thereby controlling the current between the source and the drain flowing through the channel layer.

An n ⁺ type impurity region is formed under the source and drain electrodes to lower ohmic resistance.

The operating speed of the MESFET is mainly determined by the mutual conductance (gm) and the resistance between the source and drain electrodes. In other words, the greater the mutual conductance, and the less resistance between the source and drain, the faster the operating speed. The mutual conductance is inversely proportional to the gate length, and the resistance is smaller as the gap between the channel length and the source and drain becomes smaller. Therefore, for the high speed operation of the MESFET, it is necessary to shorten the length between the components such as the electrodes.

If components such as these electrodes are manufactured by a conventional photolithography process, their length is limited by the precision of mask fitting.

As described above, the MESFET has various difficulties in proper alignment between components such as the source, drain electrode, and gate electrode. In order to solve this problem, various self-aligning processes have been developed to match the positions of components such as electrodes without using a photolithography process.

Among them, a technique for forming a buried gate electrode by self aligning has been proposed in the Very High Speed Integrated Circuits, SEMICONDUCTORS AND SEMIMETALS vol. 29/1991.

The manufacturing method of the MESFET of this document is shown in FIG. This will be described with reference to the manufacturing method of the conventional MESFET.

The starting material is a semi-insulating GaAs substrate. As shown in FIG. 1A, n-type ions, for example, Si and the like, are selectively implanted onto the substrate 10 to form the n-type channel layer 12. Thereafter, a silicon oxide film (SiO ₂ ) is deposited on the channel layer 12, an aluminum (Al) film is deposited thereon, and then patterned to form a cap metal 15. The cap metal 15 is subjected to reactive ion etching (RIE) using an etching mask to form a SiO ₂ dummy gate having a length of 1.5 m and a thickness of 1 m.

Next, as shown in FIG. 1 (b), a photoresist pattern 13 for defining source and drain regions is formed, and the photoresist pattern 13 and the cammetal / virtual gate 15/14 are formed. As an ion implantation mask, ions such as Si are selectively implanted to form the n ⁺ type source and drain regions 16. After that, the sidewall of the virtual gate 14 is etched by about 0.2 mu m. As a result, the length d ₂ of the virtual gate 15 is about 1.1 μm, and the length d ₁ between the virtual gate 15 and the source and drain regions is about 0.2 μm.

After the sidewall etching of the virtual gate 14 is finished, the photoresist pattern 13 and the Al-capmetal 15 are removed as shown in FIG. 1C, and the resulting SiO is 0.15 mu m thick on the structure. _{After the second} film 17 is formed, annealing is performed.

Subsequently, as shown in FIG. 1 (d), in order to form source and drain electrodes, the AuGe / Ni / Au ohmic contact 18 is formed by a normal lift off method, and the photoresist shown by dotted lines is shown. (19a) is applied. The photoresist 19a is then etched by the RIE method until the surface 14a of the virtual gate 14 is exposed.

Finally, as shown in FIG. 1E, the inverted pattern is obtained by etching the virtual gate 14 with an NHF + HF mixed etchant. That is, as a result, a vertical hole of 1.1 m in length and 1.15 m in depth remains in the photoresist 19. Pt 21 is deposited on the structure and the photoresist 19 is lifted off. In this process step, the virtual gate 14 is replaced with a Pt gate 22.

The conventional MESFET manufactured as described above is subjected to dry etching, such as RIE, for sidewall etching of the SiO ₂ virtual gate 14. SiO ₂ has poor reproducibility in dry etching due to its material properties. In addition, it is difficult to expect a satisfactory role as the virtual gate 14 having a fine line width of 1.5 mu m or less as mentioned above because the adhesive strength with the GaAs crystal used as the substrate is not good.

In addition, the lift-off process is performed after the Pt gate electrode is formed. In this process, the Pt gate is formed between the oxide film and the bottom of the photoresist in the vertical hole made by the virtual gate, so that the lift-off process is not easy. .

An object of the present invention is to provide a method for manufacturing a field effect transistor that can form a short channel length of an actual gate with a new type of virtual gate formed by mesa etching.

It is another object of the present invention to provide a method for manufacturing a field effect transistor which presents a suitable material as a virtual gate in the formation of a gate having a submicron fine line width.

Another object of the present invention is to provide a field effect transistor which is easy to lift off process.

The present invention for achieving the above object is a first step of forming a first material layer lattice matched with the semiconductor substrate on a semiconductor substrate, and a first impurity region formed on the surface of the first material layer and the semiconductor substrate A second step of forming a cap metal on the first impurity region, a fourth process of etching the first material layer using the cap metal as a mask, and a photoresist pattern defining a second impurity implantation region Forming a second impurity region using the photoresist pattern and the cap metal as a mask; and mesa-etching the side surface of the first material layer etched in the fourth process. A seventh step of forming an oxide layer, an eighth step of removing the photoresist pattern and a cap metal, and an oxide film formed on the entire surface of the semiconductor substrate on which the virtual gate is formed and A ninth process of activating the first and second impurity regions, a tenth process of opening the oxide film to form first and second electrodes in ohmic contact with a second impurity region, and on the resulting structure of the tenth process. An eleventh process of applying a photoresist and etching to expose the surface of the virtual gate, a twelfth process of removing the virtual gate to form a hole having the same shape as the virtual gate, and the resulting structure of the twelfth process And a thirteenth step of forming a third electrode in the hole by depositing a metal material, and a fourteenth step of removing the photoresist together with the metal material layer thereon by a lift-off step.

The present invention having such a configuration provides a virtual gate structure formed by mesa etching in a method of reducing the length of the gate electrode formed on the channel layer.

The virtual gate has a fine line width and is positioned on a semiconductor substrate to be formed to substitute with the actual gate. Therefore, Al _X GS _1-X As (where x = 0.5), which is lattice matched with the substrate and has excellent adhesion, is used as the material of the fine line width virtual gate, and they are formed by epitaxy growth.

The removal of the virtual gate causes the upper width of the mesa hole formed by the photoresist to determine the length of the third electrode, that is, the actual gate.

The length of the third electrode is formed to be the same size as the width of the mesa hole to form a short effective channel length. Therefore, the field effect transistor operating at high speed due to the increase in the mutual conductance is realized.

The space remaining after the formation of the third electrode under the mesa type hole is advantageous for the lift-off process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 (a) to (f) are cross-sectional views of a manufacturing process of the MESFET according to the embodiment.

The starting material is a semi-insulating GaAs substrate. However, a semiconductor substrate such as InP, GaP or InGaP may be used depending on the purpose. As shown in FIG. 2 (a), a first material layer of 0.5 to 1 탆, i.e., Al _X Ga _1-X , is deposited on the GaAs substrate 20 by a conventional epitaxy method such as LPE, MBE, or MOCVD As layer (but x = 0.5) 24a is grown. This Al _X Ga _1-X As layer 24a is for forming a virtual gate to be described later.

Thereafter, n-type ions such as Si or the like are selectively implanted into the entire surface of the Al _X Ga _1-X As layer 24a to form a channel layer. The implanted ions penetrate to the surface of the substrate 20 to form a first impurity region, that is, an n-type channel layer 22. At this time, the injection energy is 50 to 200 KeV and the dose is 10 ¹² to 10 ¹³ cm ^-2 .

After the ion implantation process is completed, a cap metal 25 having an aluminum (Al) film pattern is formed on the Al _X Ga _1-X As layer 24a by a normal lift-off method. Using this capmetal 25 as an etching mask, dry or wet etching such as reactive ion etching (RIE) is performed to form an AlGaAs dummy gate 24 (see FIG. 2 (b)). At this time, the virtual gate 24 is etched in Mesa (mesa), the mesa etching is naturally formed by dry or wet etching.

As shown in FIG. 2 (b), the length d ₁ of the cap metal 25 is equal to the bottom length of the virtual gate 24 in the state where the virtual gate 24 having both sides reversely inclined by mesa etching is formed. The length becomes about 1.5 micrometers. The upper surface length d ₂ of the virtual gate 24 is about 0.7 to 1 μm. It is possible to form the virtual gate 24 in a mesa shape with such a fine line width in view of the material properties of AlGaAs epitaxially grown. This material not only has excellent etching reforming but also has superior adhesion to conventional silicon oxide layers.

Next, as shown in FIG. 2C, a photoresist pattern 23 for defining source and drain regions is formed, and the photoresist pattern 23 and the cap metal 25 are used as ion implantation masks. N-type ions, for example, Si ⁺ and the like, are selectively implanted to form a second impurity region, that is, an n ⁺ -type source and drain region 26. At this time, the ion implantation conditions are the implantation energy is 50 ~ 200 KeV and the dose amount is 10 ¹³ ~ 10 ¹ cm ^-2 . Thereafter, the side surface of the virtual gate 24 is further mesa-etched by about 0.2 μm (d ₃ ). As a result, the bottom surface length of the virtual gate 24 becomes about 1.1 micrometers smaller than the length of a cap metal. The length d ₄ of the upper surface of the virtual gate 24 determines the length of the gate electrode, which will be described later, and may be appropriately determined in consideration of device characteristics. Preferably it is formed in the length of 0.3-0.6 micrometer.

Here, the mesa etching of the virtual gate 24 is because the effective gate length can be made smaller than the conventional vertical holes when the actual gate is formed. That is, the upper surface length d ₄ of the virtual gate 24 becomes the effective gate length.

This is because the lift-off process is easy after the actual gate formation. This will be described later.

After the source and drain regions 26 are formed, and the smaller mesa-etched virtual gate 24 is formed, the photoresist pattern 23 and the Al-capmetal 25 are formed as shown in FIG. ) And a 0.15 μm thick SiO ₂ film 27 formed over the resulting structure, followed by a temperature of 800 ° C. or higher to activate the channel layer 22 and the source and drain regions 26, i.e., the impurity implantation regions. Anneal in The SiO ₂ film 27 is formed to prevent Out diffusion of As in the source and drain regions 26 during annealing.

Subsequently, in order to form the first and second electrodes, that is, the source and drain electrodes 28 as shown in FIG. 2 (e), AuGe / Ni / Au ohmic contacts ( 28) is formed and spin-coated the photoresist 29a indicated by the dotted line. The photoresist 29a is plasma etched until the surface of the virtual gate 24 is exposed.

Finally, as shown in FIG. 2 (f), the inverted pattern is obtained by etching the virtual gate 24 with an H ₄ SO ₄ based etchant. That is, as a result of the structure, mesa-shaped holes of 0.3-0.7 µm in length and 0.65-1.15 µm in depth remain in the photoresist 29.

A metal film 31, for example, a multilayer film of Ti / Pt / Al, Al or Pt, or the like is deposited on the structure, and the photoresist 29 is lifted off. That is, the photoresist 29 is dissolved to remove the metal film 31 thereon. In this process step, the virtual gate 24 is replaced with a metal gate 32 to form a third electrode, the gate electrode 32, of the same size as the hole inlet in the hole.

Here, the gate electrode 32 is formed self-aligned on the channel layer 22 through the mesa-shaped hole remaining after the virtual gate 24 is removed. Therefore, the length of the metal gate d ₅ is determined by the size of the mesa type hole inlet, and the length of the gate electrode 32 thus formed is determined by the length d ₄ of the upper surface of the virtual gate. Therefore, it is easy to form a short effective gate length which is very important for device characteristics. The short effective gate length allows for short formation of the channel length, which increases the mutual conductance and enables high speed field effect transistors.

In the manufacturing process, the gate electrode 32 is formed between the gate electrode and the photoresist during the lift-off process of removing unnecessary portions after formation, thereby facilitating the removal of the photoresist by the action of the photoresist removal liquid.

Therefore, according to the present invention, a virtual gate having a fine line width can be formed, and a high speed field effect transistor can be realized with an effective gate length reduction.

Claims (19)

A first step of forming a first material layer lattice matched with the semiconductor substrate on the semiconductor substrate, a second step of forming a first impurity region on the first material layer and the surface of the semiconductor substrate, and the first impurity region A third step of forming a cap metal thereon, a fourth step of etching the first material layer with the cap metal as a mask, a fifth step of forming a photoresist pattern defining a second impurity implantation region, and A sixth step of forming a second impurity region using a photoresist pattern and a cap metal as a mask, a seventh step of further mesa etching a side surface of the first material layer etched in the fourth step to form a virtual gate, and An eighth step of removing the photoresist pattern and the cap metal; and an oxide film is formed on the entire surface of the semiconductor substrate on which the virtual gate is formed and annealed to activate the first and second impurity regions. A ninth process, a tenth process of opening the oxide film to form first and second electrodes in ohmic contact with a second impurity region, and applying a photoresist over the resulting structure of the tenth process to An eleventh process of etching to expose the surface; a twelfth process of removing the virtual gate to form a hole having the same shape as the virtual gate; and a deposition of a metal material on the resulting structure of the twelfth process. And a thirteenth step of forming a three-electrode, and a fourteenth step of removing the photoresist together with the metal material layer thereon in a lift-off step. The method of manufacturing a field effect transistor according to claim 1, wherein the semiconductor substrate is formed of any one of semi-insulating GaAs, InP, GaP, or InGaP. The method of claim 1, wherein the first material layer is formed of Al _X Ga _1-X As (where x = 0.5). The method of manufacturing a field effect transistor according to claim 1, wherein the first material layer is formed by any one of LPE, MBE, and MOCVD. 5. The method of claim 1, 3 or 4, wherein the first material layer is formed to a thickness of 0.5 to 1 mu m. The method of claim 1, wherein the first impurity region is formed into an n-type by implanting Si ions. 7. The method of manufacturing a field effect transistor according to claim 6, wherein the ion implantation conditions form an implantation energy of 50 to 200 KeV and a dose of 10 ¹² to 10 ¹³ cm ^-2 . The method of claim 1, wherein the cap metal serves as a mask for etching or ion implantation of an underlying layer. The method of claim 1, wherein the second impurity region is formed of n ⁺ by implanting Si ions. The method of manufacturing a field effect transistor according to claim 9, wherein the ion implantation conditions form an implantation energy of 50 to 200 KeV and a dose of 10 ¹³ to 10 ¹⁴ cm ^-2 . The method of claim 1, wherein the mesa etching for forming the virtual gate is formed by a dry or wet etching method. 12. The method of manufacturing a field effect transistor according to any one of claims 1 to 11, wherein the virtual gate is formed so that its upper surface is 0.7-1 m in length and its lower surface is 1.5 m in length. The method of manufacturing a field effect transistor according to claim 1, wherein the first and second electrodes are formed of a multilayer of AuGe / Ni / Au. The method of manufacturing a field effect transistor according to claim 1, wherein the step of removing the surface of the photoresist to expose the virtual gate of the eleventh step is performed by a plasma ashing method. The method of claim 1, wherein the virtual gate is removed by wet etching with an H ₂ SO ₄ based etchant. The method of claim 1, wherein the third electrode is formed on the first impurity layer region in a mesa hole formed by the photoresist. The method of claim 1, wherein the length of the third electrode is determined by an upper width of a mesa hole formed by the photoresist. 18. The method of manufacturing a field effect transistor according to any one of claims 1 to 16, wherein the third electrode is formed to a length of 0.3 to 0.6 mu m. The field effect transistor of claim 1, wherein the first electrode and the second electrode are formed in ohmic contact to act as a source and drain electrode, and the third electrode is formed to be in Schottky contact to act as a gate electrode. Way.