GB2029641A - Monolithic integrated circuits - Google Patents
Monolithic integrated circuits Download PDFInfo
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- GB2029641A GB2029641A GB7928154A GB7928154A GB2029641A GB 2029641 A GB2029641 A GB 2029641A GB 7928154 A GB7928154 A GB 7928154A GB 7928154 A GB7928154 A GB 7928154A GB 2029641 A GB2029641 A GB 2029641A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 150000001875 compounds Chemical class 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 17
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000001657 homoepitaxy Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
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- 239000002019 doping agent Substances 0.000 description 2
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- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- 238000005468 ion implantation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A monolithic integrated circuit comprises field effect transistors, formed in a homostructure of a semiconductor compound comprising a semi-insulating substrate (2), a first active semiconductor layer (4) having a low degree of doping and at least one further active semiconductor layer (6) having a high degree of doping. The circuit comprises a switching transistor (10) having an N-Off structure and a (gateless) load transistor (20) having an N-On structure. The length L of the conductive channel beneath the gate (12) of the switching transistor (10) is at most 2 mu m. Due to this short gate channel length the circuit is suitable for high bit rates. <IMAGE>
Description
SPECIFICATION
Monolithic integrated circuits
The present invention relates to monolithic integrated circuits comprising a field effect transistor, having a relating long and relatively narrow gate electrode formed on a homostructure comprising active semiconductor compound layers on a semiinsulating substrate.
It is known, that integrated digital field effect transistor circuits in a metal-semiconductor junction structure or a p-n junction structure formed on a semi-insulating substrate made of a semiconductor compound, for example, gallium arsenide GaAs, have short switching times when there is used a very short conducting channel beneath the gate electrode of an integrated field effect transistor. Monolithic integrated circuits of this kind are therefore suitable for high bit rates. The semiconductor compounds in question with a high electron mobility, such as
GaAs, or InP, have a high electron speed. These semiconductors compounds can be used for a semi-insulating substrate with which high packing densities of the homostructure can be achieved since undesired couplings between individual components are avoided.This semi-insulating substrate is provided with active layers of the same compound either by homo-epitaxy (i.e. epitaxial deposition of the same compound), or by ion implantation.
Gallium arsenide circuits comprising "normally off" field effect transistors (N-OFF-FET) are superior to circuits comprising normally-on field effect transistors (N-ON-FET) as regards power consumption and thus the packing density attainable. The switching speed of these integrated circuits is the greater, the smaller the channel length of the field effect transistors i.e. the dimension of the gate electrode in the direction from the source electrode to the drain electrode. Gate channel lengths of 2pm are likely to result in delay times of less that 1 nsec for the electronic components of the integrated circuit (see,
GaAs enhancement mode JFET Integrated Circuits,
International Electron Devices Meeting, IEDM,
Washington 1975).
It is an object of the present invention to provide monolithic integrated circuits of this kind comprising field effect transistors, which are suitable for use with high bit rates.
According to the invention, there is provided a monolithic integrated circuit comprising a homostructure of a semiconductor compound comprising a semi-insulating substrate, a first active semiconductor layer having a relatively low n-doping, and a second active semiconductor layer having a relatively high n-doping, said circuit including at least one switching unit comprising a switching transistor having an N-off structure and a gate channel length of at most 2Fum, and a load element having an N-on structure. Preferably the channel length of the switching transistor is at most form.
Such an integrated circuit has a very short delay time and a low power loss.
The non-blocking contacts of the switching tran sistorwhich serve as source and drain electrodes can be arranged on the upper active semiconductor layer which is provided with a relatively high n-doping, so that the junction resistance is low. Such non-blocking contacts are manufactured from the materials which are known for producing nonblocking contacts of low contact resistance.
If desired, a third active semiconductor layer can be provided between the non-blocking contacts and the second active semiconductor layer, which third layer has an-even higher doping and results in a further reduction in the contact resistance.
Such a monolithic integrated circuit can expediently be produced by providing the homostructure with a non-blocking metal contact structure which contains openings one for each gate of the transistors and subsequently providing the n-doped homostructure with a p-conducting or Schottky contact in an opening to form the gate electrode.
In one of the openings, the gate contact zone of the switching transistor may be formed by anistropic etching of the active semiconductor material to produce an overhang transversely to the direction of the gate channel. The active semiconductor material is removed down to the first active layer by this etching step. The strip-shaped gate electrode is then formed within the opening, preferably by vapour deposition of the contact material, the strip width (and thus the length of the gate channel) being determined by the width of the opening in the metal contact structure (i.e. is self-aligned).Forthis purpose, the surface of the first active layer is provided with a gate contact of considerable length and sort width which forms a p-n junction or a metalsemiconductor Schottky junction with the conduction channel of the FET, the contact having a width not exceeding 2Rm. The non-blocking metal contact is provided with an associated source or drain terminal. Under an adjacent opening in the nonblock metal contact structure, the gate channel of the load element is formed by etching away the active semiconductor material to leave only a thin residual part of the second active layer to serve as an N-ON channel.
Owing to the small width of the strip-like gate contact required, the corresponding opening in the metal contact structure must also be very narrow.
Therefore at least the openings for the gate electrodes of the switching transistors are preferably produced by photolithography using the "lift-off" technique, as is described, for example, in "Technology and Microwave Performance of a 1 Rm GaAs
Schottky-Barrier Field Effect Transistor", Siemens Forschungsund Entwicklungsberichte Vol.4, (1975), No. 5, pages 274 to 280 for a field effect transistor. The photographic mask is expediently exposed by electron beam illumination which can produce an opening width, and thus a length of the gate channel, of less than 1 liy, in particular 0.2cm or less.
The gate electrode of the switching transistor is preferably produced by the vapour deposition of material which is subsequently alloyed into the first active semiconductor layer. The gate electrode may consist of a plurality of individual layers, the innermost one of which either exerts a p-doping effect on the adjoining surface zone of the semiconductor layer, or forms Schottky contact therewith. In addition, the layers should be such that the electrode adheres well to the semiconductor material and alloying can be carried out at a low temperature.
If a third active layer having particularly high doping is used between the non-blocking contacts and the second active layer, the non-blocking contacts which serve as source and drain electrodes can advantageously be constructed in a similar way.
The associated load transistor may be produced by removing part of the second semiconductor layer under an adjacent opening of the non-blocking metal contact structure, so as to leave a residual part of a thickness such as to produce a predetermined saturation current. The required thickness is preferably produced by stepped removal of the material, for example, by etching the current produced by each step being measured on a test structure.
The invention will now be further described with
reference to the drawing, in which:
Figure 1 is a circuit diagram of a circuit unit comprising a switching transistor and a load element, which is integrated in a circuit according to the invention;
Figure 2 is a current-voltage diagram for such a unit; and
Figure 3 is a schematic side sectional view of an integrated circuit according to the invention including a unit as shown in Figure 1.
Figure 1 illustrates an integrated circuit unit acting as a reversal stage and comprising a switching transistor 10 and a load element 20, both formed as metal-semiconductor structures. The source electrode of the switching transistor 10 carries earth potential, whilst the output signal UA can be withdrawn from the drain electrode of this transistor. The gate electrode of the switching transistor 10 carries an input voltage UE. The drain electrode of the switching transistor 10 is also connected to the cathode of the load element 20. The anode of the load element 20 carries the supply voltage UDD of for example 1 V. The illustrated reversal stage is required for high switching frequencies. The conventional load resistor has therefore been replaced by the load element 20 which is in the form of an N-ON
FETwhich facilitates both a high switching speed and a high output voltage range.The gate electrode of the switching transistor 10 forms a blocking contact with the underlying semiconductor material, which can be in the form of a metal-semiconductor junction (Schottky contact), or a p-n junction.
In the curves represented in Figure 2, the drain current ID is plotted in dependence upon the drain voltage which is withdrawn as output voltage UA. In the case where a relatively large positive gate voltage is applied to the switching transistor 10 of e.g. 1 V, the space charge zone beneath the gate electrode is drawn upwards and the drain current 11o of the switching transistor 10 flows in accordance with the curve llo which is composed of a rising section corresponding to the starting current and a horizontal section corresponding to the saturation current.However, the current flowing through the overall reversal stage is limited by the broken-line curve 120 of the load element 20 so that when the
switching transistor 10 is open, the current and voltage are determined by the intersection point C
coresponding to an output voltage Uc. With a
positive gate voltage of, for example, 0.2 to 0.4 V, the space charge zone beneath the gate electrode of the switching transistor 10 virtually reaches the bound
ary surface of the semi-insulating substrate and consequently only a small current llo can flow.The current flowing through the overall reversal stage is then limited by this current Ilo, so that when the switching transistor 10 is almost closed, the current and voltage are determined by the intersection point
B corresponding to an outputvltage UB. The range of the output voltage AUA is then given by AUA
Us-Uc.
The output of such a reversal stage can be directly connected to the input of a following stage in which case the switching transistor of the following stage is opened by an input voltage uE = UB and closed by the input voltage UE = Uc.
In the embodiment of the invention shown in
Figure 3, a circuit corresponding to Figure 1 and comprising a switching field effect transistor 10 and a load element 20 is formed in a homostructure made of the same basic semiconductor compound and comprising a semi-insulating substrate 2, a first active semiconductor layer 4, a second active semiconductor layer 6 and, if desired, a third active semiconductor layer 7. The homostructure is covered with a non-blocking metal contact structure 8,18,28 in which the parts 8,18 and 18,28 are separated by openings 21 and 22. The gate electrode 12 of the switching transistor 10 is arranged in the opening 21, and the load element 20 is formed in the opening 22, and comprises a conductive channel 24 which consists of part of the second active layer 6 of reduced thickness.The part 18 of the contact structure is provided with a terminal from which an output signal UA can be withdrawn. The gate electrode 12 is similarly provided with a terminal to which the input voltage UE which serves as a control voltage can be connected. The part 8 of the metal contact structure is connected to earth potential whilst the part 28 of the contact structure is connected to a supply voltage UNDO.
The substrate 2 consists of a semi-insulatng semiconductor compound, preferably gallium arsenide GaAs, which may, for example, contain chromium, iron or oxygen as a dopant. The substrate material is generally doped during a crystal drawing process. The doping concentration is so selected that the substrate has a resistivity of about 1 o8 ohms-cm. The first active layer 4 in which the electrical operations of the switching transistor 10 take place is deposited by homo-epitaxy onto the substrate 2. This layer also consists of gallium arsenide, is relatively thick, and, because of a low doping, has a resistivity of, for example, about 1 ohm-cm. The doping concentration is preferably 1 x 1015 to 3 x 1016 atoms/cm3. With a doping concentration of 1015 the thickness of the first active layer 4 is about 1.7cm. With increasing doping concentration the thickness of the layer is reduced, so that with a doping concentration of 3 x 1015 atoms/cm3, the thickness is about 1 calm. Sulphur is preferably used as the dopant, but tin or silicon are also suitable. The doping concentration is kept low in order that the space charge zone formed beneath the gate electrode 12 may extend through the total thickness of the active layer 4 at a control voltage UE of O V. The second active semiconductor layer 6 is also produced by homo-epitaxy but is substantially thinner than the layer 4 and has a higher doping concentration, which may be in the range of 3 x 1016to 3 x 1017 atoms/cm3.This high doping is used in order that the space charge zone beneath the gate of the load element 20 should not extend through the remaining part 24 of the active layer 6. With a doping concentration of 1 x 1017 atoms/cm3, its thickness is about 0.2clam. When the remaining part 24 has a higher doping concentration, the thickness of this part is reduced; with a doping concentration of 3 x 1017 atoms/cm3, for example, the thickness should be about 0.1cm. This relatively thin active layer 6 is preferably produced by gas phase epitaxy.
Under certain circumstances, a third active layer 7 having an even higher n-doping may be produced on the second active layer as shown by the dashdotted line in Figure 3. This layer 7 is also preferably produced by gas phase epitaxy and may, for example, have a doping concentration of 1018 atoms/cm3.
This very high doping results in a reduction in the junction resistance to the non-blocking metal contact structure 8, 18 and 28.
The metal structure 8, 18 and 28 must possess a low contact resistance to the adjacent active layer 7 and in addition should adhere well to the semiconductor material. The surface of the active layer 7 is first provided with a thin germanium layer having a thickness of, for example, 10 nm onto which a gold layer is vapour deposited in a thickness of, for example, 140 nm. During a subsequent alloying step in which the metal contact structure is alloyed-in at a low temperature of, for example, about 400 C, these two layers form a melt which dissolves the gallium arsenide GaAs. During cooling, a highly n-doped boundary layer is recrystallised from this melt.A further vapour deposited chromium layer having a thickness of, for example, 40 nm produces a good adhesion for a final gold layer having a thickness of, for example, 160 nm which produces a good electrical conductivity. This metal contact structure 8, 18 and 28 which serves as an n-contact is preferably produced with the openings 21 and 22 required for the transistors. Since these openings simultaneously determine the width of the strip-like gate contacts and thus the length of the conductive channel beneath the gate contacts, the width of these openings may not substantially exceed 2lim and in particular amounts to a maximum of 1clam.
The method, which is known perse, of producing a metallic structure on a semiconductor body by the vapour deposition of the metal, partially covering it with photo-lacquer, heating and subsequently etching, cannot be used in this case because of the small dimensions involved ( < 2um). However, in order to obtain the relatively considerable length of the strip-like gate contact with a uniform and yet very small, width, the openings 21 and 22 of the n-contact are produced by the lift-off technique without etching. For this purpose, the homostructure consisting of the substrate 2 and the active layers 4, 6 and 7 is provided with a photo-lacquer structure which covers the areas where the windows are to be formed, but leaves uncovered the areas where the n-contacts 8, 18 and 28 are to be formed.At these areas the upper active layer 7 is then provided with the metallic coating preferably consisting of the layer sequence described above. The photo-lacquer is then dissolved away lifting with it the metal deposited thereon so as to form the openings 21 and 22, with straight and perpendicular edges. The photo-lacquer strips may be dissolved, for example, by spraying with a solvent therefor.
The strip-like gate contact 12 of the switching transistor 10 is produced by removing by anisotropic etching beneath the opening 21, the upper active layers 6 and 7 and, possibly as may be necessary under certain circumstances, also a small part of the first active layer 4. When an anisotropic etching agent is used, the etching rate is dependent upon the crystal orientation of the etched semiconductor material. Therefore a suitable etching front is obtained at right angles to the drawing plane. The crystal orientation of the active layers is so selected that beneath the opening 21 an etching front in the form of an overhanging slope is at both sides of the etched cavity, as indicated in broken lines in Figure 3. A rising slope is formed in the direction at right angles to the plane of the drawing.A p-conducting gate contact 12 is then produced in this cavity through the opening 21, preferably by vapour deposition. This gate contact 12 then has the shape of a strip of very short width and considerable length.
The width of this strip determines the length L of the conductive channel beneath the gate electrode 12.
Thus the length L does not substantially exceed 2calm.
Prior to the vapour deposition of the gate contact 12, the surface of the n-contact 8, 18,28 is covered with a resist layer which may consist, for example, of a photo-lacquer. The adjustment of this mask is not critical, however, since the gate width L is determined by the width of the opening 21.
Residues of the gate metallisation 14 and 16 which are formed during the production of the gate electrode 12 remain at the edges of the opening 21.
The gate contact 12 preferably consists of an initial layer, of a metal, in particular cadmium, which exerts a p-doping effect on the adjacent active semiconductor layer 4. Beryllium, magnesium, manganese, or zinc can alternatively be used for this purpose. This first layer is covered with a second metal layer, preferably of gold, which forms a eutectic with the first layer at a low temperature, for example, below 400 C. The gate contact 12 can thus be alloyed into the semiconductor body at a correspondingly low temperature. The second metal layer is provided with a third metal layer which serves as a blocking layer and preferably consists of titanium; this layer prevents interdiffusion between layers above and below it during the alloying process. Platinum has a similar effect. Under some cicumstances it may be desirable to apply a further blocking layer of platinum in addition to a titanium layer. The terminal of the electrode is formed by a noble metal layer which preferably consists of gold or silver. The gate contact 12 is advantageously alloyed in at a temperature of between 3500C and 450 C, preferably below 400 C.
The gate contact then establishes a rectifying p-n junction beneath which the conductive channel having the length L is then formed in the first active layer 4 when the control voltage UE is connected.
The load element 20 is produced by etching away the semiconductor material of the upper active layer 6 and 7 beneath the opening 22 until only a part of the second active layer 6 remains. The depth of the recess so produced and thus the remaining thickness of the active layer 6 which determines the saturation current 120 in the conductive channel 24 so formed, is preferably fixed by stepwise removal of the material, accompanied by measurement on a test structure.
Line cross-overs may be produced in the monolithic integrated circuit by first providing the exposed surface with an intermediate layer which may consist, for example, of silicon dioxide or of silicon nitride. This intermediate layer is then provided with the required metal conductor paths for example, by vapour deposition of the metal. These conductor paths generally consist of a layer sequence which preferably contains a chromium layer which adheres well to the intermediate layer.
Claims (14)
1. A monolithic integrated circuit comprising a homostructure of a semiconductor compound comprising a semi-insulating substrate, a first active semiconductor layer having a relatively low ndoping, and a second active semiconductor layer having a relatively high n-doping, said circuit including at least one switching unit comprising a switching transistor having an N-off structure and a gate channel length of most 2clam, and a load element having an N-on structure.
2. A circuit as claimed in Claim 1, wherein the length of the gate channel of the switching transistor does not substantially exceed 1 um.
3. A circuit as claimed in Claim 1 or Claim 2, wherein a third active semiconductor layer having a considerably higher degree of n-doping than said second semiconductor layer is provided on said second layer.
4. A monolithic integrated circuit substantially as hereinbefore described with reference to the drawing, and as shown in Figure 3 thereof.
5. A method of manufacturing a monolithic integrated circuit as claimed in any one of Claims 1 to 3 comprising the steps providing the surface of said homostructure with an n-conducting, non-blocking electrical contact structure containing openings at the positions of the gate channels of said switching and load transistors, forming a recess beneath one of said openings to receive the gate contact of said switching transistor by anisotropic etching producing an overhang extending transversely of the gate, the material of second active layer, and the third active layer when present, being removed in said recess down to said first active layer, providing a gate contact in said recess which forms a blocking metal-semiconductor junction (schottky contact) or a p-n junction with the n-conducting channel of the switching transistor, said contact having a width at its boundary with the semiconductor surface of at most lum; and forming below the other of said openings the gate zone of said load element by removing said third active layer, when present, and a major part of said second active layer to leave a relatively thin part thereof to said as an N-on channel of the load element.
6. A method as claimed in Claim 5, wherein the openings in said contact structure (8,18,28) are produced by the "lift-off" technique using a photolacquer.
7. A method as claimed in Claim 6, wherein said photo-lacquer is illuminated for exposure by an electron beam.
8. A method as claimed in any one of Claims 5 to 7, wherein the gate electrode of the switching transistor forms a p-n junction with the semiconductor surface and is produced by vapour deposition of a metal layer sequence and subsequently alloying the deposited material into said first active layer.
9. A method as claimed in Claim 8, wherein within the recess beneath said one opening, the first active layer is provided with a first electrode layer which exerts a p-doping effect in the adjacent surface zone of said first active layer.
10. A method as claimed in Claim 9, wherein said first electrode layer is provided with a further electrode layer which forms a eutectic with said first layer.
11. A method as claimed in Claim 10, wherein said second electrode layer is provided with at least one further electrode layer made of a noble metal.
12. A method as claimed in any one of Claims 5 to 11, wherein layer thickness of the gate zone of said load element is determined by stepwise removal of the material of the second active layer and simultaneous measurement of the saturation current of said element.
13. A method as claimed in any one of Claims 5 to 12, wherein the width of the gate electrode of the switching transistor is determined by the width of said one opening.
14. A method of manufacturing a monolithic integrated circuit substantially as hereinbefore described with reference to Figure 3 of the drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19782835642 DE2835642A1 (en) | 1978-08-14 | 1978-08-14 | MONOLITHIC INTEGRATED CIRCUIT WITH FIELD EFFECT TRANSISTORS AND METHOD FOR THEIR PRODUCTION |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2029641A true GB2029641A (en) | 1980-03-19 |
Family
ID=6047037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7928154A Withdrawn GB2029641A (en) | 1978-08-14 | 1979-08-13 | Monolithic integrated circuits |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5527699A (en) |
| DE (1) | DE2835642A1 (en) |
| FR (1) | FR2433832A1 (en) |
| GB (1) | GB2029641A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2449369A1 (en) * | 1979-02-13 | 1980-09-12 | Thomson Csf | LOGIC CIRCUIT COMPRISING A SATURABLE RESISTANCE |
| US4351706A (en) * | 1980-03-27 | 1982-09-28 | International Business Machines Corporation | Electrochemically eroding semiconductor device |
| JPS58143562A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Gaas integrated circuit |
| JP5012886B2 (en) * | 2009-12-25 | 2012-08-29 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3999281A (en) * | 1976-01-16 | 1976-12-28 | The United States Of America As Represented By The Secretary Of The Air Force | Method for fabricating a gridded Schottky barrier field effect transistor |
-
1978
- 1978-08-14 DE DE19782835642 patent/DE2835642A1/en not_active Withdrawn
-
1979
- 1979-07-23 FR FR7918914A patent/FR2433832A1/en not_active Withdrawn
- 1979-08-13 GB GB7928154A patent/GB2029641A/en not_active Withdrawn
- 1979-08-14 JP JP10392579A patent/JPS5527699A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5527699A (en) | 1980-02-27 |
| DE2835642A1 (en) | 1980-02-28 |
| FR2433832A1 (en) | 1980-03-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |