DE2835642A1 - MONOLITHIC INTEGRATED CIRCUIT WITH FIELD EFFECT TRANSISTORS AND METHOD FOR THEIR PRODUCTION - Google Patents

Description

2635642

SIEMENS AKTIENGESELLSCHAFT Our reference Berlin and Munich VPA 78 P 7 0 78 BRD

Monolithic integrated circuit with field effect transistors and their manufacturing process

The invention relates to a monolithic integrated circuit with field effect transistors with strip-shaped Gate electrodes of great width and very short length on a homostructure made of a compound semiconductor with semi-insulating substrate.

With integrated digital field effect transistor circuits in metal-semiconductor or pn structure on a semi-insulating It is known that a substrate made of a compound semiconductor, for example gallium arsenide GaAs, is obtained with a very short length of the conductive channel under the gate electrode of the integrated field effect transistors short switching times. Such monolithic integrated circuits are therefore suitable for high bit rates. the Compound semiconductors with high electron mobility such as GaAs, InP, considered here have a high electron velocity. With these compound semiconductors, a semi-insulating substrate can be manufactured with the high Packing densities of the homostructure can be achieved because un-Kin 2 Sh / 31.7.19083000 9/0205

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desired couplings between the components are avoided. This substrate is made by homoepitaxy or even provided with active layers by ion implantation.

Gallium arsenide circuits with "normally-off field effect transistors" CN-OFF-FET) are the circuits with "normally-on field effect transistors" CN-ON-FET) in terms of power consumption and thus also the achievable Superior packing density. The switching speed of these integrated circuits is greater, the smaller the channel length, i.e. the extension of the gate electrodes in the direction from the source electrode to the drain electrode the field effect transistors is. Gate channel lengths of 2 pm allow for the electronic components the integrated circuit delay times of less than 1 nsec with low power dissipation expect CGaAs Enhancement Mode JFET Integrated Circuits, - International Electron Devices Meeting, IEDM, Washington 1975).

The invention is based on the object of such monolithic to produce integrated circuits with field effect transistors that are suitable for high bit rates. The length of the conductive channel under the gate, which is the case for field effect transistors with strip-shaped gate electrodes is determined by the short length of the strips, must therefore not and should not significantly exceed 2 pm in particular be at most 1 µm.

This object is achieved according to the invention in that a homostructure made of an η-conductive substrate and a first active semiconductor layer with low n-doping and at least one further active semiconductor layer with a higher η doping with at least one circuit unit from a switching transistor in N-Off design and a length of the gate channel of at most 2 pm and a load element is provided in N-ON design. The length of the gate

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The channel of the switching transistor is preferably not significantly larger than 1 μm, in particular at most 1 μm. This integrated circuit has a very short delay time and low power dissipation.
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The non-blocking contacts of the switching transistor, which serve as source and drain electrodes, can be connected to the Upper semiconductor layer are arranged, which is provided with a high η-doping, so that the contact resistance is as small as possible. These lock-free contacts are made of a material with which Have lock-free contacts made with low contact resistance.

Under certain circumstances, a third active layer can also be used between the non-blocking contacts and the second active layer Layer may be provided which, through particularly high doping, further reduces the contact resistance causes.

To produce this monolithic integrated circuit, the homostructure can expediently initially with a * £ ·· # <# ···· provided with lock-free metal contact structure which contains openings for one gate each of the transistors and later with p-conductive contacts or Schottky contacts is provided.

The gate contact area of the Switching transistor produced by anisotropic etching, which creates a slope across the direction of the gate channel. The active semiconductor material is removed by the etching down to the first active layer. Afterward the strip-shaped gate electrode is preferably located within the opening by vapor deposition of the contact material produced, the strip length being determined by the length of the opening in the metal contact structure

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becomes (self-alignment). For this purpose, the surface of the first active layer is made with gate contact large width and short length provided, the a pn junction or a blocking metal semiconductor junction forms with the duct and a length of at most 2 pm. The lock-free material contact is provided with the associated source or drain connection. Under an adjacent opening of the lock-free metal contact structure becomes the gate contact of the load element by removing the active semiconductor material up to a remaining part of the second active layer is produced as an N-ON channel.

Because of the required small width of the strip-shaped gate contact, the corresponding opening must also be used the metal contact structure can be very narrow. There are therefore at least the openings for the gate electrodes Switching transistors produced by photolithography in lift-off technique, such as, for example in "Technology and Microwave Performance of a 1 pm GaAs Schottky Barrier Field Effect Transistor", Siemens Research and development reports Vol. 4 (1975), No. 5, pages 274 to 280 for a field effect transistor is. The exposure of the photomask is expediently carried out by electron beam exposure, with the one Opening width and thus a length of the gate channel of less than 1 μm, in particular about 0.2 μm and less, is attainable.

The gate electrode of the switching transistor can preferably be produced by vapor deposition of material, which then is alloyed into the first active semiconductor layer. The gate electrode is expediently made up of individual Layers exist, of which at least one is either in the adjacent surface area of the semiconductor acts p-doping or forms a Schottky contact.

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Furthermore, the layers are chosen so that the electrode adheres well to the semiconductor material and that alloying occurs is possible at the lowest possible temperature.

If there is a third active layer between the non-blocking contacts and the second active layer with be * If there is particularly high doping, the non-blocking contacts serving as source and drain electrodes can be advantageous be constructed in the same way.

The associated load transistor is produced by removing part of the second semiconductor layer under an adjacent opening of the barrier-free metal contact structure. The thickness of the remaining part of the required for a predetermined saturation current second active layer can preferably be determined by stepwise removal, for example etching, and measuring the current on a test structure, respectively.

To further explain the invention, reference is made to the drawing, in which Figure 1 shows an electronic Circuit unit with a switching transistor and a load element is illustrated schematically. Figure 2 shows the characteristic field of the two electronic components in one diagram. In Figure 3 is a cross section through an arrangement according to Figure 1 illustrates schematically. According to Figure 1, there is a working as a reverse stage Integrated circuit unit with field effect transistors in a metal-semiconductor structure made from a switching transistor and a load element 20. The source electrode of the switching transistor 10 is at ground potential, while at the Drain electrode, the output signal U. can be tapped. Is connected to the gate electrode of the switching transistor 10 the input voltage U ^. The drain electrode of the switching

Transistor 10 is also connected to the cathode of load element 20. At the anode of the load element 20

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the Yers orgungs voltage Uj _{30 is,} for example, 1 V. The reversing stage shown should be suitable for high switching frequencies. Therefore, instead of the usual load resistor, the load element 20 is provided, which enables both a high switching speed and a high output voltage swing. The unspecified gate electrode of the switching transistor 10 forms a blocking contact, which can preferably be a metal-semiconductor junction (Schottky contact) but also a p junction.

In the family of characteristics according to FIG. 2, the drain current I ^ is plotted as a function of the drain voltage, which is taken as the output voltage U. With a positive gate voltage of the switching transistor 10 of, for example, 1 V, the space charge zone under the gate electrode is pulled up and the drain current 1 ^ _{0 of} the switching transistor 10 alone would follow the characteristic I ₁ q, which consists of a linear range of the starting current and a horizontal part of the saturation current. The current flowing through the entire reversing stage, however, is limited by the dashed characteristic curve I ₂ Q of the load element 20, so that when the switching transistor 10 is open, the current and voltage through the intersection C with the output voltage U are given. With a positive gate voltage of 0.2 to 0.4 V, for example, the space charge zone under the gate electrode of the switching transistor 10 almost reaches the interface with the semi-insulating substrate, and therefore only a small current Iq can flow. The current flowing through the entire reversing stage is limited by this current IQ, so that the current and voltage are given when the switching transistor 10 is almost closed through the intersection point B with the output voltage U _ß . The output voltage swing ^ k U. is then given by ^ U. = Ug-U-.

The output of an inverter can be connected directly to the input connected to a subsequent stage, whereby the switching

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transistor of the following stage is opened by the input voltage Ug = Ug and closed by the input voltage Ug = U _c .

In the section of FIG. 3, a substrate is denoted by 2, a first active semiconductor layer by 4 and a second active semiconductor layer by 6. The gate electrode 12 of the switching transistor 10 is arranged in an opening 21 of a lock-free metal contact structure 8, 18, 28. A load element 20 is arranged in an opening 22 of the metal contact structure 18, 28 and contains a conductive gate channel 24, which consists of part of the second active semiconductor layer 6. The electrode 18 is provided with a connecting conductor from which the output signal U _A can be picked up. The gate electrode 12 is also provided with a connection conductor to which the input voltage Ug serving as a control voltage can be applied. The electrode 8 of the metal contact structure is at zero potential, and the electrode 28 is connected to the supply voltage U ^.

The substrate 2 consists of a semi-insulating compound semiconductor, for example gallium arsenide GaAs, which for example contains chromium. For doping is also Suitable for iron or oxygen. The substrate material generally already receives the doping during crystal pulling. The doping concentration is chosen so that the substrate has an electrical conductivity of approx Ohm-cm received. The first active layer 4, in which the electrical processes of the switching transistor 10 take place, is deposited homoepitaxially on the substrate 2. It also consists of gallium arsenide and is proportionate thick and has a conductivity of, for example, about 1 ohm-cm due to low doping. The doping concentration is preferably about 1 × 10 to 3 × 10 atoms / cm. With a doping concentration of 10, the thickness of the first active layer 4 is approximately

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1.7 μΐη. As the doping concentration increases, the The thickness of the layer is chosen to be smaller and, with a doping concentration of 3 × 10 atoms / cm, is about 1 μm. Sulfur S is preferably used as the doping material. Tin Sn or silicon Si is also suitable. the Doping concentration is kept low so that the space charge zone under the gate electrode 12 at a Control voltage Ug of zero volts through the entire active Layer 4 passes through. The second active semiconductor layer 6 is also produced by homoepitaxy. It is much thinner and contains a higher doping concentration, which is about 3 10 to 3 χ 10 atoms / cm. This high doping is chosen so that the space charge zone is under the gate of the load element does not extend through the remaining part 24 of the active layer 6. With a doping concentration of

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1 × 10 atoms / cm, their thickness is about 0.2 µm. With a higher doping concentration of the remaining part, a smaller thickness of this part is also required, which is the case with a doping concentration of, for example

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3 χ 10 atoms / cm about 0.1 pm must be chosen. This thin active layer 6 is preferably produced by gas phase epitaxy.

On the second active layer, a third active layer 7 with an even higher n-doping, also preferably by gas phase epitaxy, which, for example, have a doping concentration of 10 atoms / cm. This very high doping results in a reduction in the Contact resistance to the lock-free metal contact structure 8, 18 and 28.

The metal structure 8, 18 and 28 should have a low contact resistance to the adjacent active layer 7 and also adhere well to the semiconductor material. It will therefore first the surface of the active layer 7 with

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a thin germanium layer with a thickness of 10 nm, for example, on which a gold layer with a thickness of, for example, 140 nm is evaporated. These two layers form during the subsequent alloy the metal contact structure at a low temperature of, for example, about 400 ° C a melt that Gallium arsenide dissolves GaAs. On cooling, a highly η-doped boundary layer recrystallizes from this melt. Another vapor-deposited chrome layer with a thickness of 40 nm, for example, ensures good adhesion. A final gold layer with a thickness of 160 nm, for example, gives a good electrical one Supply line. This serving as η-contact metal contact structure 8, 18 and 28 is preferably already with the Openings 21 and 22 required for the transistors are produced. Since these openings are also the width of the strip-shaped gate contacts and thus the length of the Determine conductive channel under the gate contacts, the width of these openings must not significantly exceed 2 pm and in particular will be at most 1 µm.

The usual technique for producing a metallic structure on a semiconductor body by vapor deposition of the metal, partial covering with photoresist, baking and subsequent etching can be done because of the small dimensions (· <2 µm) cannot be used. But in order to get the relatively large width of the strip-shaped gate contact with a constant but very short length is obtained, the openings 21 and 22 of the n-contact using the clift-off technique) without etching. For this purpose, the homostructure of the substrate '2 and the active layers 4, 6 and 26 with a Provided photoresist structure which contains the structure of the n-contact 8, 18, 28 to be applied as a window.

In these windows, the upper active layer is then provided with the metallic coating, which is preferably

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can consist of the mentioned sequence of layers. The photoresist is then dissolved and one obtains within the n-contact 8, 18, 28, the openings 21 and 22 with straight and vertical edges. Dissolving the Photoresist strips are made, for example, by spraying on a solvent.

To produce the strip-shaped gate contact 12 of the Switching transistor 10 becomes the upper active layers 6 and 7 below opening 21 and, under certain circumstances, also a small part of the first active layer 4 is still removed by anisotropic etching. In the case of an anisotropically attacking Etchant, the etching rate is dependent on the crystal orientation of the etched semiconductor material. You get therefore an inclined etching front in each case perpendicular to the plane of the drawing. The crystal orientation of the active layers is now chosen so that below the illustrated opening 21 to both sides within the plane of the drawing an etching front receives as a sloping slope, as indicated by dashed lines in the figure. Then in the direction perpendicular to the plane of the drawing is a rising slope. In this opening 21 is then a p-type Gate contact 12, preferably produced by vapor deposition. This gate contact 12 then has the shape of a Strip of short length and great width. The length of this strip determines the length L of the conductive channel below the gate electrode 12. The length L is thus not significantly greater than 2 µm. Before evaporation of the gate contact 12, the surface of the n-contact 8, 18, 28 is covered with a layer which, for example, consists of Photoresist can exist. The adjustment of this mask is not critical, however, since the gate length L is through the opening 21 is exposed.

Remnants of the gate metallization lie on the edges of the opening 21 14 and 16 used in the manufacture of the

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Gate electrode 12 arise. The gate contact 12 preferably consists initially of a metal layer, in particular cadmium Cd, which has a p-doping effect in the adjacent active semiconductor layer 4. In addition, beryllium Be, magnesium Mg, manganese Mn and zinc Zn can also be used, for example. This first layer is covered with a second metallic layer, preferably gold Au, which forms a eutectic with the first layer at a low temperature, for example below 400.degree. The gate contact 12 can thus be alloyed into the semiconductor body at a correspondingly low temperature. The second layer is provided with a third layer which serves as a barrier layer and which preferably consists of titanium and prevents interdiffusion during the alloying process.

Platinum, for example, has this effect. Under certain circumstances it can be useful to apply a further barrier layer made of platinum in addition to the titanium layer. A noble metal cover, which can preferably consist of gold or also of silver, forms the end of the electrode. The gate contact 12 is advantageously alloyed at a temperature between approximately 350.degree. C. and at most 450.degree. C., in particular below 400.degree. The gate contact then produces a rectifying pn junction, under which the conductive channel with the length L is formed in the first active layer 4 _{when the control voltage U E is applied.}

To produce the load element 20, the semiconductor material of the upper active layer 6 is etched away below the opening 22 between the regions 18 and 28 of the n-contact and so far that only a part of the second active layer 6 remains. The depth of the depression and thus the remaining thickness of the active layer 6, which determines the saturation current I ₂₀ in the conductive channel 24, is preferably determined by stepwise removal, in particular etching, and respective measurements on a test structure.

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Line crossings of the monolithic integrated circuits are produced by first providing the free surface with an intermediate layer made, for example, of silicon dioxide SiO ₂ or also of silicon nitride Si-N. can exist. This intermediate layer is then provided with the required metallic conductor track, for example by vapor deposition of the metal. These conductor tracks generally consist of a layer sequence, which preferably contains chromium, which adheres well to the intermediate layer.

T3 claims
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Claims (1)

Claims foj Monolithic integrated circuit with field effect transistors with strip-shaped gate electrodes of great width and very short length on a homostructure made of a compound semiconductor with a semi-insulating substrate., characterized in that a homostructure made of a semi-insulating substrate (2) and a first active semiconductor layer (4) with low η-doping and at least one further active semiconductor layer (6) with high η-doping with at least one circuit unit consisting of a switching transistor (10) in N-Off-Baufdrm with a length CL) of the gate channel of at most 2 pm and a load element (20) is provided in N-On design. 2, circuit according to claim 1, characterized in that that the length (L) of the gate channel of the switching transistor (10) is not significantly greater than T µm, in particular at most 1 µm. 3, A circuit according to claim 1 or 2, characterized characterized in that a third active Semiconductor layer (7) with significantly higher n-doping than the second semiconductor layer (6) is provided. 4 .. A method for producing a monolithic integrated circuit according to any one of claims 1 to 3, characterized in that the homostructure is provided with an η-conductive, non-blocking metal contact structure (8, 18, 28), the openings (21, 22) and that under one of the openings (21) a depression for the gate contact (12) of the switching transistor (10) is produced by anisotropic etching which creates a slope transversely to the direction of the gate channel and the semiconductor material of the active layer 0009/0205 ORiGlNAL INSPECTED - 2 - YPA ^ P 7 O 7 8 FRG th (6, 7) removes up to the first active layer (4) and that within the depression the surface of the first active layer (4) with a gate contact (12) is provided, which has either a blocking metal semiconductor junction or a pn junction with an n-conducting Channel and a length (L) of at most 2 pm and that under an adjacent opening (22) of the lock-free Metal contact structure (8, 18, 28) the gate region of the load element (20) by lowering the active layers (6, 7) except for a remaining part (24) of the second active layer (6) produced as an N-On channel will. 5. The method according to claim 4, characterized in that g e - indicates that the metal structure (8, 18, 28) of the circuit unit is produced using lift-off technology will. 6. The method according to claim 5, characterized by an electron beam exposure of the photoresist. 7. The method according to claim 4, characterized in that the gate contact (12) of the switching transistor (10) consists of a blocking metal-semiconductor junction (Schottky contact). 8. The method according to any one of claims 4 to 6, characterized in that the gate Electrode (12) of the switching transistor (10) produced by vapor deposition of a layer sequence of metals which is then alloyed into the first active layer (4). 9. The method according to claim 7, characterized in that the first active layer (4) 030ÖÖ9 / 02QS below the opening (21) of the metal structure (8, 18, 28) is provided with a first electrode layer which has a p-doping effect in the adjoining surface area of the first active layer (4).
S. 10, method according to claim 8, characterized in, that the first electrode layer is provided with a further electrode layer which forms a eutectic with the first layer. ti, method according to claim 9, characterized in, that the second electrode layer with at least one further electrode layer is made of a precious metal. 12. The method according to claim 4, characterized in that that the layer thickness of the gate region (24) of the load transistor (20) by stepwise Removal of the material of the active semiconductor layer (6, 7) and the respective measurement of the saturation current (I-q) is determined. 13. The method according to any one of claims 4-9, characterized in that the length (L) of the gate electrode (12) of the switching transistor (10) is determined by the length of the opening (21). 030009 / 020B