JPS58143562A - Gaas integrated circuit - Google Patents
Gaas integrated circuitInfo
- Publication number
- JPS58143562A JPS58143562A JP2592782A JP2592782A JPS58143562A JP S58143562 A JPS58143562 A JP S58143562A JP 2592782 A JP2592782 A JP 2592782A JP 2592782 A JP2592782 A JP 2592782A JP S58143562 A JPS58143562 A JP S58143562A
- Authority
- JP
- Japan
- Prior art keywords
- current
- speed
- saturation
- voltage
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 210000000554 iris Anatomy 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H01L27/06—
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の撫する技術分野〕 本発’#J ti、GaA−集積回路に関する。[Detailed description of the invention] [Technical field touched by invention] This publication'#Jti relates to GaA-integrated circuits.
GaAa電界効果トランジスタ(yz〒)を用いた高速
県検回路(IC)が注目を集めている。GaA〔■には
スイッチングトランジスタの種類によID2つC二分け
られる。1つはゲート電極(V’G)が0 の時C二も
電流が流れるタイプのνlτ(ノーマリ・オンff10
1’T、またはデプリーシ曹ン1■〒=D・Fll!T
)を使うものである。もう1つは7.) 冨Q Yの
時に電流が流れないタイプのIB丁(ノー−v IJ・
オフ蓋ν1丁、tたはエンハンスメントm’p’vT=
n・IN丁)t−使うものである。消費電力や集積化の
容易さの点で判断すると、發者がLSI、VLSIに適
している◎
ディジタルICを構成する基本回路はインバータである
がインバータはスイッチングトランジスタと負荷とから
構成される。負荷の形態としては単純1に抵抗(R)を
用い石奄の、ソース・ゲートを共通としえD・11!を
用いるもの、それと電子の遮縦飽和特性を利用した2端
子素子である電流り建ツタなどが代表的tものである。High-speed prefectural detection circuits (ICs) using GaAa field-effect transistors (yz〒) are attracting attention. GaA [■] is divided into two IDs and two Cs depending on the type of switching transistor. One is the type νlτ (normally onff10) in which a current flows when the gate electrode (V'G) is 0
1'T, or Depricy Officer 1■〒=D・Fll! T
) is used. The other one is 7. ) Tomi Q A type of IB in which current does not flow when Y (no-v IJ)
Off lid ν1 piece, t or enhancement m'p'vT=
n・IN ding) t- something to use. Judging from the viewpoint of power consumption and ease of integration, the author is suitable for LSI and VLSI. The basic circuit that constitutes a digital IC is an inverter, and an inverter is composed of a switching transistor and a load. As a load type, simply use a resistor (R) and share the source and gate, D.11! Typical examples include those using it, and electric current vines, which are two-terminal devices that utilize the shielding saturation characteristics of electrons.
このうち、電織り建ツタはスイッチング速度および集積
度の点から最も好ましい負荷と考えられている。Of these, electric ivy is considered the most preferable load in terms of switching speed and degree of integration.
11111gは電流リミッタの電流(1)−電El−,
(V) ’1性を換式的−二示し九ものである。I−V
%性を特徴づけゐバラメータは飽和電fi(Is)と飽
和電圧(Vs)の2つである。これらはそれぞれ、工@
= fn611 !’m −−−
−−−−−−−(1)V、W g、l、 十 工a
Rg −−−−−−−−−−(Kl但し、
で与えられる。11111g is the current limiter current (1) - electric El -,
(V) ``1 character is a commutative - 2 signifier. I-V
There are two parameters that characterize the % property: the saturation voltage fi (Is) and the saturation voltage (Vs). These are respectively
= fn611! 'm ---
-----------(1) V, W g, l, 10 engineering a
Rg ----------(Kl, however, is given by.
第2図Fitfiリミッタを負性とした110L型イン
バータの動作点を求める−でおる。なお第2図(a)で
、(A)は次段ゲート順方向特性、(匂はスイッチング
FETの特性、(0)は電流+) <ツタ特性を示す図
である。B−71テをスイッチングトランジスタとして
使用する回路ではショットキー接合を順方向≦ニバイア
スして使うので、その立上り電圧V7 Uo、7〜0.
8v位でクランプがかかる0すなわち%論地動作電圧は
10ルベル(50,IV)と0.7−0.8vの11ル
ベルの間にある。こうした回路6二使われる電流リミッ
タは、この範囲で定電流と見なせるよう一動作すること
が望ましい。しかもGaAs工O,Lε工などは低消費
電力性を大きな%像とするから電源電圧(VDO)は〜
1v前後になることが予想される0この2つを考え合せ
ると、負性としての1tfilJ<ツタの特性として
v、≦VDD −V/ −1−0,7−0,3(V)−
(a+が賛求される□ GaA−でFi#、=3KV/
e、であり、フオトリノダラフイで比較的容易かつ確実
にパターン二ングしうる最小寸法は1μであることを考
えると
’aL ” 3xlO”xlO−’ = 0.3 (
V) −−−−−(41と表る。すなわち現在の技術で
はtSt式の条件はかなり厳しいものである。v8を小
さくするには、Lを小さくすることが必要であることは
勿論であるが、(1)式かられかるように[夕1j抵抗
R8の動勢を小さくする方がより現実的な問題である。Fig. 2 - Determining the operating point of a 110L type inverter with a negative FitFi limiter. In FIG. 2(a), (A) is a diagram showing the forward direction characteristic of the next stage gate, (the odor is the characteristic of the switching FET, and (0) is the current +). In a circuit that uses B-71TE as a switching transistor, the Schottky junction is used in a forward direction ≦ double bias, so its rising voltage V7 Uo, 7 to 0.
The zero or % logic operating voltage that is clamped at about 8 volts is between 10 levels (50, IV) and 11 levels of 0.7-0.8v. It is desirable that the current limiter used in the circuit 62 operates within this range so that it can be regarded as a constant current. Moreover, the power supply voltage (VDO) is ~
It is expected that it will be around 1v.0 Considering these two, 1tfilJ as a negative value<v as a characteristic of ivy, ≦VDD -V/ -1-0,7-0,3(V)-
(a+ is approved □ Fi# at GaA-, = 3KV/
e, and considering that the minimum dimension that can be patterned relatively easily and reliably with Phototorinodara phi is 1μ, 'aL ''3xlO''xlO-' = 0.3 (
V) -------(Represented as 41. In other words, with the current technology, the conditions for the tSt equation are quite strict. Of course, in order to reduce v8, it is necessary to reduce L. However, as can be seen from equation (1), it is a more realistic problem to reduce the movement of the resistor R8.
これ壕で提案されている電流リミッタの構造は第3図(
a) (b)のようなものである。すなわち半絶縁性G
aムー結晶31 rニドナ不純物をイオン注入した層3
2の絢端礪二AuG・系のオー建ツク電極33不・炬成
したものである。従って1stljとりもなおさず2つ
のオーミック電極33のコンタクト抵抗2RoとなるO
Ro Fi粗い近似として。The structure of the current limiter proposed in this area is shown in Figure 3 (
a) It is like (b). That is, semi-insulating G
a Mu crystal 31 r Layer 3 in which Nidna impurities are ion-implanted
The electrode 33 is made of a two-layered AuG-based structure. Therefore, the contact resistance of the two ohmic electrodes 33 becomes 2Ro without changing the 1stlj.
Ro Fi as a rough approximation.
RO=v Fη−−−−−−−−−−−−−−−−−−
(5)p8:電一部のシート抵抗 (Ω10)Io:固
有】ンタクト抵抗 (Ω・−)で表わせる。電流Vtツ
タの活性層は通常I・11テの活性層と同一条件で作ら
れることが多い。すなわち、電子線板n : I X
10”α−1,活性層の厚さO1〜02μ、根鼓でおる
0これに対応したり、I#0はほはρ8:: 1000
−2000Ωk + IO”: 5 X 10−’〜
l X 10−’と考えられる。従って、コンタクト抵
抗は(6)式から暢W=1μあたり2〜4にΩとなる。RO=v Fη−−−−−−−−−−−−−−−−−−
(5) p8: Sheet resistance of electrical part (Ω10) Io: Intrinsic] Contact resistance (Ω・-). The active layer of the current Vt vine is usually made under the same conditions as the active layer of the I.11te. That is, electron beam plate n: I
10"α-1, active layer thickness O1~02μ, root drum 0 corresponds to this, I#0 is ρ8:: 1000
-2000Ωk + IO": 5 x 10-'~
It is considered that l x 10-'. Therefore, the contact resistance is 2 to 4 Ω per 1μ of W = 1μ from equation (6).
通常スイッチングI−アITのゲート幅FiIG〜20
μであることが多く、これに対する電流りンツタ負佑の
幅は2〜5μ程度である。そのためコンタクト抵抗Fi
l電極あたり0.4〜2KQ(二本達する0これにより
v8が上昇してしまう0
〔発明の目的〕
本発明はこうした従来の電流りiツタの欠点な改良した
もので、直列抵抗R8を低減化させることにより電流飽
和電圧を下けて為速GaAsl0を実機することを目的
としている。Normal switching I-IT gate width FiIG~20
It is often μ, and the width of the current fluctuation relative to this is about 2 to 5 μ. Therefore, contact resistance Fi
0.4 to 2 KQ per electrode (reaching two) This increases v8. [Objective of the Invention] The present invention is an improvement on the drawbacks of the conventional current regulator, reducing the series resistance R8. The purpose is to reduce the current saturation voltage by increasing the current saturation voltage and to realize a practical device of high speed GaAsl0.
本発明では電子が飽和速度で走行する領域の−より2つ
のオーミンクiIk跡の輪が広いことを特徴とする電織
り建ツタを負葡として用いる0第4図はこのような条件
をみ友す電流リミッタの一例である。電子が飽和速度て
足口する置載の−をW。In the present invention, electric woven ivy, which is characterized by a wider ring of two Ohminck iIk traces than in the region where electrons travel at a saturation speed, is used as a negative vine. Figure 4 meets these conditions. This is an example of a current limiter. W is the position where the electrons reach their saturation speed.
長さをLとする。この領域たけでみる眠すは第3図と同
じである。以下で、菖4−の構造により直列抵抗R8が
どの位小さくしうるかを計算式をもととなる。いま、L
′;2戸、v’=20μ、W=4声であったとすると。Let the length be L. The sleep seen in this area is the same as in Figure 3. The following will be based on a formula for calculating how much the series resistance R8 can be reduced depending on the structure of the irises 4-. Now, L
': Assume that there are 2 houses, v' = 20μ, and W = 4 voices.
Bll′=±・(0,4〜2)+(1〜2)・又=0.
2〜0.6にΩ20
20−−一−−−−−〜 (テ)
となり、従来構造に比べ直列抵抗かなり小さくかつ、は
らつきも小さくなる。Bll'=±・(0,4~2)+(1~2)・Also=0.
Ω20 to 2-0.6
20--1-- (TE) Compared to the conventional structure, the series resistance is considerably smaller and the fluctuation is also smaller.
このよう≦二2つのオーミンク電極部を拡大すること(
二よりそのコンタクト抵抗を小さくすることがi2J詫
となる。In this way, enlarging the two Ohmink electrode parts (
The i2J solution is to make the contact resistance smaller than the second one.
以上の説明から明らかなよう1′一本発明1:よる電故
リミッタは直列抵抗CRm )が小さいため、(2)式
鑑二あるところのIBR,が小さくなり飽和電圧Vaを
小さくすることができる。その結果、電源電圧がIVi
il稜と低くても定電流負荷として振る舞い。As is clear from the above explanation, the electric fault limiter according to the present invention 1 has a small series resistance CRm), so that IBR, in equation (2), becomes small, and the saturation voltage Va can be made small. . As a result, the power supply voltage is IVi
Behaves as a constant current load even if the il edge is low.
一連かつ安定なGaAs工Oが構成できる。またオーミ
ック電極のコンタクト抵抗に多少のパッツ午があっても
V/のバラツキが小さくなるという効果もおる。A series of stable GaAs fabrics can be constructed. Another effect is that even if there is some resistance in the contact resistance of the ohmic electrode, the variation in V/ is reduced.
以下で不発1pH二基づいて設計された電流り建ツタを
用いたノーマリオフff1Gaム−ICの試作例な紹介
する。半絶縁性Ga人−結晶に81イオンを100 K
vで2×10 注入し%850℃で15分アニールし。Below, we will introduce a prototype example of a normally-off FF1Ga MU-IC designed based on the unexploded 1pH2 using a current building block. Semi-insulating Ga-crystal with 81 ions at 100 K
2 × 10 cells were implanted at 8% v and annealed at 850 °C for 15 min.
活性層を形成した。スイッチングトランジスタのゲート
幅は20声、ゲート長は1μで閾偽電圧が約0.1vと
なるよう1ニゲ一ト部をエツチングして関節した。一方
、負荷としての電流リミッタは第5図(1)のような構
造のものとした。比較のために第5図(匂のような一般
的なものも同時(二作った。第6図に2つの電流リミッ
タの電流−電圧特性を比較して示す。前述の予測どうり
、飽和電圧が0,7vから0.45 Vへと約0.25
7も小さくなっていることがわかる。なお、これら2つ
を負荷としたインバータを用いて15Rのりンダ発振器
を!成してスイッチング時間を欄定した結果本発明のリ
ミッタな用いた方が約16−も為遭であつ九。An active layer was formed. The gate width of the switching transistor was 20 tones, the gate length was 1μ, and one gate was etched so that the threshold false voltage was about 0.1V. On the other hand, the current limiter as a load had a structure as shown in FIG. 5(1). For comparison, Figure 5 (general items such as odor were also made at the same time). Figure 6 shows a comparison of the current-voltage characteristics of the two current limiters.As predicted above, the saturation voltage is about 0.25 from 0.7v to 0.45 V
It can be seen that 7 has also become smaller. By the way, you can create a 15R Linda oscillator using an inverter with these two loads! As a result, when using the limiter of the present invention, it was found that approximately 16 times the switching time was determined.
@1図は電流リミッタの電流−電圧特性の模式図、1m
2図は電流り電ツタを負荷としたノーマリオフ型GaA
3インバータの動作点を求める図、第3図は従来の電流
す(ツタを負荷としたJ PETのWt成図。
i11%4凶ej本%明を説明するための電流リミッタ
を負へとじよj FETの平面図、M5図は本発明を用
いて構成した実際の電流リミッタな負荷としたJPET
の平面図とこのFETと比較するための、TFITの平
面図、al16凶は第5図に示す2つの電流リミッタの
電流−電圧特性を示した図である。
図において、31はチ絶縁性GaAs M晶、32i1
を活性層、33はオーミック電憔でろる。
(7317)代場人 升埋士 則 近 應 佑 (はが
1名)7第 1 図
$2図
rat tly)第
5 図
(α)
第6図
(bン@Figure 1 is a schematic diagram of the current-voltage characteristics of a current limiter, 1m
Figure 2 shows a normally-off type GaA with a current-fed vine as a load.
Figure 3 is a diagram to find the operating point of an inverter. J FET's top view, M5 diagram shows JPET as an actual current limiter load constructed using the present invention.
5 is a plan view of a TFIT for comparison with this FET, and a diagram showing the current-voltage characteristics of the two current limiters shown in FIG. In the figure, 31 is insulating GaAs M crystal, 32i1
is the active layer, and 33 is an ohmic electric layer. (7317) Daiba person Masuji Nori Chikao Yu (1 person) 7th 1st figure $2 figure rat tly) th
5 Figure (α) Figure 6 (b)
Claims (1)
領域と電気的に継がるより幅の広い領域を2つ有し、そ
こ1ニオ−建ツク電極を設け、電流リミッタを負荷とし
たことを特徴とするGaA−集積(ロ)路。It has an electrically active region in which electrons travel at a saturation speed, and two wider regions that are electrically connected to that region, where a 1-nitrogen electrode is installed and a current limiter is used as a load. A GaA-accumulating path characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2592782A JPS58143562A (en) | 1982-02-22 | 1982-02-22 | Gaas integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2592782A JPS58143562A (en) | 1982-02-22 | 1982-02-22 | Gaas integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58143562A true JPS58143562A (en) | 1983-08-26 |
Family
ID=12179402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2592782A Pending JPS58143562A (en) | 1982-02-22 | 1982-02-22 | Gaas integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58143562A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60151149U (en) * | 1984-03-21 | 1985-10-07 | 沖電気工業株式会社 | GaAs semiconductor device |
JPS63311752A (en) * | 1987-06-15 | 1988-12-20 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
US7030728B2 (en) * | 2002-01-04 | 2006-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Layout and method to improve mixed-mode resistor performance |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49126287A (en) * | 1973-04-04 | 1974-12-03 | ||
JPS5527699A (en) * | 1978-08-14 | 1980-02-27 | Siemens Ag | Monolithic integrated circuit and method of manufacturing same |
JPS5563859A (en) * | 1978-11-08 | 1980-05-14 | Fujitsu Ltd | Field-effect transistor integrated circuit |
JPS55134955A (en) * | 1979-04-09 | 1980-10-21 | Nec Corp | Gaas integrated circuit |
-
1982
- 1982-02-22 JP JP2592782A patent/JPS58143562A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49126287A (en) * | 1973-04-04 | 1974-12-03 | ||
JPS5527699A (en) * | 1978-08-14 | 1980-02-27 | Siemens Ag | Monolithic integrated circuit and method of manufacturing same |
JPS5563859A (en) * | 1978-11-08 | 1980-05-14 | Fujitsu Ltd | Field-effect transistor integrated circuit |
JPS55134955A (en) * | 1979-04-09 | 1980-10-21 | Nec Corp | Gaas integrated circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60151149U (en) * | 1984-03-21 | 1985-10-07 | 沖電気工業株式会社 | GaAs semiconductor device |
JPS63311752A (en) * | 1987-06-15 | 1988-12-20 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
US7030728B2 (en) * | 2002-01-04 | 2006-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Layout and method to improve mixed-mode resistor performance |
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