JPS63311752A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63311752A JPS63311752A JP62148581A JP14858187A JPS63311752A JP S63311752 A JPS63311752 A JP S63311752A JP 62148581 A JP62148581 A JP 62148581A JP 14858187 A JP14858187 A JP 14858187A JP S63311752 A JPS63311752 A JP S63311752A
- Authority
- JP
- Japan
- Prior art keywords
- load
- semiconductor integrated
- integrated circuit
- circuit device
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000005684 electric field Effects 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- OOYGSFOGFJDDHP-KMCOLRRFSA-N kanamycin A sulfate Chemical group OS(O)(=O)=O.O[C@@H]1[C@@H](O)[C@H](O)[C@@H](CN)O[C@@H]1O[C@H]1[C@H](O)[C@@H](O[C@@H]2[C@@H]([C@@H](N)[C@H](O)[C@@H](CO)O2)O)[C@H](N)C[C@@H]1N OOYGSFOGFJDDHP-KMCOLRRFSA-N 0.000 description 1
- 210000003734 kidney Anatomy 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor integrated circuit device.
従来の技術
インバータ回路において負荷としてＦＥＴ１用いた回路
を第５図ａに示す。この場合、負荷として抵抗を用いた
場合に比べて、第６図すに示されるように定電流源的な
負荷特性を示すので第６図す内に示される動作点におい
ては極めて大きな利得が得られる。A conventional inverter circuit using an FET 1 as a load is shown in FIG. 5a. In this case, compared to the case where a resistor is used as the load, as shown in Figure 6, the load characteristics are like a constant current source, so an extremely large gain can be obtained at the operating point shown in Figure 6. It will be done.
発明が解決しようとする問題点
しかしながら、このような従来の回路では、負荷のＦＩ
ＣＴのゲートに寄生する容量成分の存在のために高速ス
イッチング性を損う問題があった。Problems to be Solved by the Invention However, in such conventional circuits, the load FI
There is a problem in that high-speed switching performance is impaired due to the presence of a parasitic capacitance component in the gate of the CT.
本発明はかかる問題点に鑑みてなされたもので、定電流
的な負荷特性を有する低寄生容量の負荷を有する半導体
集積回路装置を提供すること全目的としている。The present invention has been made in view of these problems, and its entire purpose is to provide a semiconductor integrated circuit device having a constant current load characteristic and a low parasitic capacitance load.
問題点を解決するための手段
本発明は上記問題点を解決するため、負荷として、回路
の使用電圧においてキャリアの速度飽和の生じる二端子
素子をそなえて構成されている。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is configured to include a two-terminal element as a load in which carrier velocity saturation occurs at the voltage used in the circuit.
作用
本発明は上記した構成により５速度飽和の生じる二端子
負荷が定電流源的な特性あるいは微分負性抵抗特性を示
す点から、インバータ回路において利得が大きく、かつ
抵抗的な二端子素子であるため、寄生容量の小さい負荷
を実現できる。Operation The present invention is a two-terminal element with a large gain and resistance in an inverter circuit, since the two-terminal load in which 5-speed saturation occurs exhibits constant current source-like characteristics or differential negative resistance characteristics due to the above-described configuration. Therefore, a load with small parasitic capacitance can be realized.
実施例
第１図は本発明の一実施例における負荷を実現するため
の半絶縁性ＧａＡｓ基板に形成する場合のマスクレイア
ウト図である。第１図において１はキャリアの速度飽和
を生じるｎ型抵抗領域、２はコンタクトのためのｎ 型
領域、３はオーミック電極となる人ｕＧｅ ／ Ｎｉ
／ムＵ領域、４は半絶縁性ＧａＡｓ基板、５は電界の印
加される領域長である。Embodiment FIG. 1 is a mask layout diagram for forming a load on a semi-insulating GaAs substrate in an embodiment of the present invention. In Figure 1, 1 is an n-type resistance region that causes carrier velocity saturation, 2 is an n-type region for contact, and 3 is a uGe/Ni layer that becomes an ohmic electrode.
4 is a semi-insulating GaAs substrate, and 5 is the length of the region to which an electric field is applied.
半絶縁性Ｇ２ＬＡＳ基板４ Ｋ ２ ｘ １０” ｃｍ
−２（ｒ）ドーズ量、６０に６Ｖの加速電圧でＳｉ＋イ
オンをイオン注入し負荷の形成される領域１を、６×１
ｏ１５ｆｆ−２のドーズ量、１００ＫｅＶの加速電圧で
Ｓｉ＋イオンをイオン注入しコンタクトのためのｎ＋領
域２を【ハム−Ａよ 矛／７−Ｉ菅襦Ｉ古ｌ汁辻ス１舟
ｇ４＋ス小ソのマー形成する。８ｏｏ℃２０分のアニー
ル後、ＡｕＧｅ／Ｎｉ／人ｕｉ各々６００人１５０人／
１５００人蒸０し電極３を形成した後、Ｈ２雰囲気で５
００℃。Semi-insulating G2LAS substrate 4 K 2 x 10” cm
-2(r) dose and an accelerating voltage of 6V to 60V to ion-implant Si+ ions to form a 6×1
Si+ ions were ion-implanted at a dose of o15ff-2 and an accelerating voltage of 100 KeV to form the n+ region 2 for contact. Form a mer. After annealing at 80°C for 20 minutes, AuGe/Ni/Human ui 600 and 150 people/
After evaporating for 1500 people and forming the electrode 3, 5
00℃.
５分間の合金化を行なった。このようにして形成した二
端子負荷の電流・電圧特性は第２図に示されたような特
性となる。第２図はＬの大きさ６を１．５ 、３ 、８
７１ｍの３条件で振り分けた結果である。Ｌが小さい程
、同一の印加電圧で領域１内の電界が高く、小さい電圧
でキャリアの速度飽和を生じ、二端子間を一定電流が流
れる特性を示す。Alloying was carried out for 5 minutes. The current/voltage characteristics of the two-terminal load thus formed are as shown in FIG. Figure 2 shows the size 6 of L as 1.5, 3, 8
These are the results of 71m divided into three conditions. The smaller L is, the higher the electric field in region 1 is with the same applied voltage, the carrier velocity saturation occurs with a smaller voltage, and a constant current flows between the two terminals.
この時に負荷は一定電流が流れるような条件である程度
以上の電圧を加えるとホットエレクトロンの移動度の変
化のために電流が減少する傾向が見られる。At this time, if a voltage above a certain level is applied to the load under conditions such that a constant current flows, the current tends to decrease due to changes in the mobility of hot electrons.
第３図は本発明の他の実施例としての差動増幅器の回路
である。２１は上記の負荷、２２は電流源としての上記
負荷、２３．２４はＧａＡｓ ＭＥＳＦＥＴである。ま
た２５．２６は差動入力端子、２７は出力端子である。FIG. 3 shows a differential amplifier circuit as another embodiment of the present invention. 21 is the above-mentioned load, 22 is the above-mentioned load as a current source, and 23.24 is a GaAs MESFET. Further, 25 and 26 are differential input terminals, and 27 is an output terminal.
回路で負荷２１は、定電流源的な特性を持って−ル時の
活性化率などで変動しやすい。ここで負荷のｌを全て同
一にして、Ｗの大きさを変更すれば、（例えば、２２の
Ｗを２１のＷよりも小さく設計すれば）回路は確実に動
作する。In the circuit, the load 21 has characteristics like a constant current source, and is likely to fluctuate depending on the activation rate when the load is applied. Here, if all the loads l are the same and the size of W is changed (for example, if W of 22 is designed to be smaller than W of 21), the circuit will operate reliably.
第４図ａは微分負性抵抗を有するインバータ回路図すの
動作を示したものである。この回路の利得ＡｖはＦＩＴ
のドレインコンダクタンスをλ。FIG. 4a shows the operation of an inverter circuit having differential negative resistance. The gain Av of this circuit is FIT
The drain conductance of λ.
相互コンダクタンス’ｋ ｇ” ＋負荷の微分コンダ
クタンスをλｌとすれば（１）式で表される。If the mutual conductance 'kg g'' + the differential conductance of the load is λl, it is expressed by equation (1).
Ａｖ ＝ ｇｍ −ニとり
、Ａ＋。ｌ ・・・・・・（１）この時負荷の
微分コンダクタンスが負であり、λとほぼ等しければ、
ＡＶは無限大に大きくできる。Av = gm - two, A+. l...(1) At this time, if the differential conductance of the load is negative and approximately equal to λ,
AV can be made infinitely large.
発明の効果
以上述べてきたように本発明によれば、極めて簡易な構
成で寄生容量の低い負荷を実現でき、低’ＩＩＩ界でキ
ャリアの速度飽和を生じるＧａＡｓ等の半導体集積回路
の高速化に寄与することが期待でき、その実用性は極め
て高い。Effects of the Invention As described above, according to the present invention, it is possible to realize a load with low parasitic capacitance with an extremely simple configuration, and it is useful for increasing the speed of semiconductor integrated circuits such as GaAs, which suffer from carrier velocity saturation in the low 'III field. It can be expected to make a contribution, and its practicality is extremely high.
一one
第１図は本発明の一実施例におけるキャリアが使用電圧
で速度飽和を起こすように端子間間隔を狭めた負荷のマ
スクレイアウト図、第２図は本発明の一実施例における
負荷の電流・電圧特性図、第３図は本発明の一実施例に
おける差動増幅回路１・・・・・・ｎ型領域、２・・・
・・・ｎ 型領域、３・・・・・・オーミック電極、４
・・・・・・基板。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名：３
８−
第１図
１−−−ｎ ’７頒武
２−ｆｉ↑！・／
第２図
叶 〕＋］ 寛 工 入１
第４図
（ｂ）
腎′し！ノ旬１′ノ
第５図
Ｖし１′Ｖ貫１Fig. 1 is a mask layout diagram of a load in which the spacing between terminals is narrowed so that the carrier causes speed saturation at the working voltage in one embodiment of the present invention, and Fig. 2 is a current/voltage diagram of the load in one embodiment of the present invention. The characteristic diagram, FIG. 3, shows the differential amplifier circuit 1, n-type region, 2, etc. in one embodiment of the present invention.
... n-type region, 3 ... ohmic electrode, 4
······substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person: 3
8-Fig.・/ Figure 2 Kano 〕+] Hiro Kogyo 1 Figure 4 (b) Kidney'shi! No-Jun 1' No. 5 V-shi 1' V-kan 1
Claims (4)
、前記負荷へ電圧を印加した時に生じる電界強度におい
て半導体内キャリアの速度飽和を生じる長さ以下である
ことを特徴とする半導体集積回路装置。(1) A semiconductor integrated circuit characterized in that the distance between the terminals of a two-terminal load formed in the semiconductor is less than or equal to the length that causes velocity saturation of carriers in the semiconductor at the electric field intensity generated when voltage is applied to the load. circuit device.
請求の範囲第１項記載の半導体集積回路装置。(2) The semiconductor integrated circuit device according to claim 1, wherein the load functions as a current source.
て等しいことを特徴とする特許請求の範囲第１項記載の
半導体集積回路装置。(3) The semiconductor integrated circuit device according to claim 1, wherein there are a plurality of loads, and the distances between the terminals of the loads are all equal.
請求の範囲第１項記載の半導体集積回路装置。(4) The semiconductor integrated circuit device according to claim 1, wherein the load includes a negative resistance region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62148581A JPS63311752A (en) | 1987-06-15 | 1987-06-15 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62148581A JPS63311752A (en) | 1987-06-15 | 1987-06-15 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63311752A true JPS63311752A (en) | 1988-12-20 |
Family
ID=15455944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62148581A Pending JPS63311752A (en) | 1987-06-15 | 1987-06-15 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63311752A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563859A (en) * | 1978-11-08 | 1980-05-14 | Fujitsu Ltd | Field-effect transistor integrated circuit |
| JPS58143562A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Gaas integrated circuit |
-
1987
- 1987-06-15 JP JP62148581A patent/JPS63311752A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563859A (en) * | 1978-11-08 | 1980-05-14 | Fujitsu Ltd | Field-effect transistor integrated circuit |
| JPS58143562A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Gaas integrated circuit |
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