JP2918979B2 - Semiconductor device and logic circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a semiconductor device having an insulated gate (MIS) field-effect transistor using energy quantization by one-dimensional conduction and a logic circuit using the field-effect transistor, and more particularly to an MIS-type electric field having nonlinear characteristics. The present invention relates to a semiconductor device having an effect transistor and a logic circuit using the field effect transistor.

[Prior art]

Most of the conventional transistors using the one-dimensional conduction of electrons utilize the increased mobility, and there is no transistor which controls the discontinuous energy level to realize a new conduction characteristic. Regarding the one-dimensional conduction of electrons, for example, Japanese Journal of Applied Physics, Volume 19, Number 12, December, 1980, pp.L735-L
738 (Japanese Journal of Applied Physics, vol.19, N
o.12, December, 1980, pp. L735-L738).
It has been pointed out that in dimensional conduction, the scattering is significantly suppressed and the mobility increases.

The above prior art utilizes an increase in mobility in one-dimensional conduction, and does not control its discrete energy levels. An object of the present invention is to control a discrete energy level caused by one-dimensional conduction, and to use a semiconductor device having an MIS field-effect transistor realizing a new conduction characteristic which has not existed in the past and using the field-effect transistor. It is to provide a logic circuit.

[Means for Solving the Problems]

In order to achieve the above object, a semiconductor device of the present invention
A semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type formed at predetermined intervals on the surface of the semiconductor substrate and having a conductivity type different from the first conductivity type;
An insulated gate field effect transistor including a first gate electrode formed on a semiconductor substrate between the drain regions with a gate insulating film interposed therebetween, and the width of the first gate electrode is reduced by the width of the first gate electrode. And a second gate electrode is disposed on a portion of the first gate electrode with an insulating film interposed therebetween so as to reduce the width of the channel. It is something to do. The width of the first gate electrode of this semiconductor device is 0.1 μm
The following is preferred. Also, the width of the second gate electrode is preferably 0.1 μm or less. In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type and a conductivity type formed at a predetermined interval on a surface of the semiconductor substrate and different from the first conductivity type. An insulated gate field effect transistor comprising a source and drain region of a certain second conductivity type and a gate electrode formed on a semiconductor substrate via a gate insulating film to form a channel between the source and drain regions And controlling the width of the gate electrode so that the channel formed by the gate electrode constitutes one-dimensional conduction of electrons, and further increasing the quantized energy level of the energy of the electrons traveling through the channel. This is provided with a means for performing. The control of the quantized energy level of the semiconductor device is preferably performed by a second gate electrode which is electrically insulated from the gate electrode via an insulating film. Further, it is preferable that the portion of the channel whose energy level is controlled has a length of 0.1 μm or less. In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, and a semiconductor substrate having a conductivity type different from the first conductivity type formed at predetermined intervals on a surface of the semiconductor substrate. It has an insulated gate field effect transistor composed of two conductivity type source and drain regions and a channel formed between the source and drain regions. The width of the channel, and one part of the channel via an insulating film.
The gate electrode is arranged so as to reduce the width of the channel. The channel width of this semiconductor device is preferably 0.1 μm or less. The width of the gate electrode is 0.1
It is preferably not more than μm. In order to achieve the above object, a logic circuit of the present invention has a semiconductor substrate of a first conductivity type and a conductivity type formed at a predetermined interval on a surface of the semiconductor substrate and different from the first conductivity type. A second conductivity type source / drain region, a first gate electrode provided on the semiconductor substrate between the source / drain region via a gate insulating film, and an insulating film provided on a portion of the first gate electrode And an insulated gate field effect transistor including a second gate electrode provided through the first gate electrode. The width of the first gate electrode is increased by the channel formed by the first gate electrode. The second gate electrode is configured to have a narrower channel width, two input terminals respectively connected to the second gate electrode via a resistor, and one of a source and a drain region. Output terminal connected to And a power supply terminal connected via a resistor, is obtained by the provided source, and a ground terminal connected to the other drain regions. In order to achieve the above object, a logic circuit of the present invention has a semiconductor substrate of a first conductivity type and a conductivity type formed at a predetermined interval on a surface of the semiconductor substrate and different from the first conductivity type. Source and drain regions of the second conductivity type, and a gate electrode provided on the semiconductor substrate via a gate insulating film to form a channel between the source and drain regions;
Means for controlling the energy of electrons traveling through the channel to increase the quantized energy level, the insulated gate field effect transistor comprising: a gate electrode having a width formed by the gate electrode; And two input terminals connected to the means for controlling the energy level via resistors, respectively, and an output terminal connected to one of the source and drain regions and connected via the resistor. And a ground terminal connected to the other of the source and drain regions. In order to achieve the above object, a logic circuit of the present invention has a semiconductor substrate of a first conductivity type and a conductivity type formed at a predetermined interval on a surface of the semiconductor substrate and different from the first conductivity type. An insulated gate field effect transistor comprising a second conductivity type source / drain region, a channel provided between the source / drain regions, and a gate electrode provided on one portion of the channel via an insulating film. The width of the channel is such that the channel constitutes one-dimensional conduction of electrons, the gate electrode is configured to reduce the width of the channel, and each of the channels is connected to the gate electrode via a resistor.
Input terminals, an output terminal connected to one of the source and drain regions, and a power terminal connected via a resistor,
A ground terminal connected to the other of the source and drain regions is provided.

[Action]

FIG. 1 (a) is a plan view of an example of the field-effect transistor of the present invention, and FIG. 1 (b) is a sectional view taken along the line AA 'thereof, for explaining the operation of the present invention. A first gate electrode 3 for forming a channel is provided between the source region 1 and the drain region 2, and a second gate electrode 4 is provided on a part of the first gate electrode 3. The discussion will proceed with the N-MOS field effect transistor in FIG. First, in FIG. 1, the drain current and the gate voltage characteristics when the second gate electrode 4 is not provided will be described. When a positive potential is applied to the first gate electrode to form a channel,
If the width of the first gate electrode is sufficiently small, at a low temperature, energy is quantized due to one-dimensional conduction.
FIG. 2 shows the energy level of the channel 8 at that time. In the case of a one-dimensional electron, the density of states DOS ₁ (E) is given by DOS ₁ (E) ∝E ^−1/2 . At this time, if the potential under the first gate is assumed to be a well-type potential, the energy level interval ΔE is given by the following equation (1). ΔE = (2n + 1) h ² / 8mW ² (1) n is a quantum number counted from a band with a low energy, h
Is Planck's constant, m is the effective mass of electrons, and W is the channel width. Now, here, the first gate voltage is increased. As the first gate voltage increases, the electron density in the channel increases. By the way, Fermi energy E _F is electron density
Given by n _s : E _F = h ² _ns ² / 8m In other words, increasing the gate voltage is equivalent to increasing the Fermi energy of electrons. Second
Referring to the figure, the Fermi energy increases as the gate voltage increases. That goes up the E _F from below in Figure 2. When E _F matches the quantized energy level, current flows. Further E _F increases this time, the current is reduced. When the next quantized energy level coincides, the current increases again. Thus, the current value when E _F matches the energy levels of the quantized takes the maximum value, dependent on the gate voltage of the current is that shown in Figure 3. Now, consider a case in which a second gate electrode which is electrically insulated is provided. When a negative potential is applied to the second gate electrode 4 in FIG. 1, the inversion of the peripheral portion of the first gate electrode 3 is suppressed as shown in FIG. The width of the channel 8 to be formed can be reduced. FIG. 4 (a) shows that the second gate voltage is 0V
FIG. 4B shows the width of the channel 8 when the second gate voltage is at a negative potential. That is, it means that the width of the channel 8 can be changed by the second gate electrode 4. In fact, band narrowing of 10-15% is possible. By the way, as can be seen from the equation (1), changing the channel width means changing the interval between energy levels. Specifically, as the channel width decreases, the interval between energy levels increases. Focusing on the same energy level, the energy level will increase. When a negative potential is applied to the second gate electrode to increase the energy level, no current flows. When the level further rises and matches the next level, a current flows. Therefore, the dependence of the current in the device on the second gate voltage is, for example, the fifth gate voltage.
FIG. 5A and the current-voltage characteristics are as shown in FIG. 5B.

【Example】

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Embodiment 1 FIG. 6 is a manufacturing process diagram of a semiconductor device having an MIS field-effect transistor according to one embodiment of the present invention. Specific resistance
An element isolation region 9 is formed on a p-type Si substrate 5 of 10 Ω · cm by a normal LOCOS method. Next, a gate oxide film 6 of 10 nm is formed by a tri-oxidation method at 850 ° C. for 30 minutes. 50 nm polycrystalline silicon 1 by CVD for the purpose of protecting gate oxide film 6
Deposit 0. A resist is applied to a thickness of 1 μm, and openings are formed in predetermined portions by photolithography, that is, two n ⁺ diffusion layer regions for a source region 1 and a drain region 2.
Arsenic ions are implanted at an acceleration voltage of 0 kV. The implantation amount was 1 × 10 ¹⁵ cm ⁻² . Of course, these n ⁺ diffusion layer regions may be formed using phosphorus ions. An annealing step is performed in a nitrogen atmosphere at 900 ° C. for 10 minutes (FIG. 6A). Next, 50 nm of polycrystalline silicon is deposited by CVD, and 875
Deposit phosphorus at 20 ° C. for 20 minutes. Thereafter, the polycrystalline silicon film is processed into a fine line shape having a width of 0.08 μm by photolithography and dry etching to form a first gate electrode 3 (FIG. 6B). Next, as an interlayer insulating film 7, PSG (Phospho
A silicon oxide film (silicate glass) film is deposited by an LPCVD method. Next, 100 nm of polycrystalline silicon is deposited by the CVD method, and phosphorus deposition is performed at 875 ° C. for 20 minutes. After that, the width is formed into a shape covering a part of the fine line-shaped first gate formed by photolithography and dry etching.
The polycrystalline silicon film is processed to a thickness of 0.3 μm to form a second gate electrode 4 (FIG. 6C). Then, PSG (Phospho Silicate Glas
s) A silicon oxide film 7 such as a film is deposited by an LPCVD method to form an interlayer insulating film, a contact hole is opened by photolithography and dry etching, and an aluminum wiring 11 is formed, as shown in FIG. 6 (d). As a result, a desired semiconductor device having a plan view of a main part in FIG. 1A and a cross-sectional view along the line AA 'in FIG. 1B was obtained. The device obtained as described above exhibited conduction characteristics as shown in FIGS. 5 (a) and 5 (b). In this embodiment, a p-type substrate is used, but if all the polarities are changed, a p-channel MIS field-effect transistor using an n-type substrate can be realized. Example 2 A semiconductor device shown in FIG. 7 was obtained by the same process as in Example 1. The difference from the first embodiment is that the width of the second gate electrode is 0.05 μm, the electrons in the portion under the control of the energy level are close to zero-dimensional, and the state density is shown in FIG. It is completely discontinuous as shown in FIG. In addition, as a result of suppressing the influence of scattering in this portion, the conduction becomes close to ballistic. FIG. 8 (b) shows, for comparison, the state density of electrons below the first gate electrode where the second gate electrode is not located. As a result, in this embodiment, as shown in FIG. 9, the vibration could be made clearer than in the first embodiment. Third Embodiment FIG. 10 is a process chart of manufacturing a semiconductor device having an MIS field-effect transistor according to another embodiment of the present invention. Specific resistance
An element isolation region (not shown) is formed on a 10 degree-cm 0 degree off p-type Si substrate 5 by a normal LOCOS method. Next, a resist was applied to a thickness of 1 μm, and the shape shown in FIG. 10A was obtained by photolithography and hydrazine etching.
Of course, instead of hydrazine etching, an etching technique having a plane orientation dependency may be used. In short, the tenth
This is to form a swirled shape as shown in FIG. Thereafter, a resist is applied to a thickness of 1 μm, and an opening is provided at a predetermined portion by photolithography, that is, at the apex of the center triangle in FIG. 10A, which is a channel region, to control the threshold voltage. At a 40 kV accelerating voltage, 1 × 10 ¹³
Drive in only cm- ² . Of course, this implantation may use arsenic ions. Next, SiO ₂ 6 ′ is deposited by a CVD method. Thereafter, a resist is applied to a thickness of 1 μm, and a predetermined portion, that is, a source region 1, is formed by photolithography.
Openings are provided in the two n ⁺ diffusion layer regions of the drain region 2,
Arsenic ions are implanted at an acceleration voltage of 120 kV. The implantation amount was 1 × 10 ¹⁵ cm ⁻² . Of course, these n ⁺ diffusion layer regions may be formed using phosphorus ions. 900 ℃, 10
10 (b) by the annealing process in a nitrogen atmosphere
become that way. Then deposit 10nm polycrystalline silicon,
Deposit phosphorus at 875 ° C for 20 minutes. afterwards,
The polycrystalline silicon film is processed by photolithography and dry etching to form a second gate electrode 4 having a width of 0.3 μm.
0 As shown in FIG. Thereafter, when the aluminum electrode wiring 17 was applied in the same process as in Example 1, the result was as shown in FIG. 10 (d). According to the present embodiment, since a channel is formed at the apex of the triangle, a channel that is extremely narrower than that of the first embodiment can be formed, so that the characteristics (vibration) are clearer than those shown in FIG. Can be obtained. In this embodiment, a p-type substrate is used. However, if all the polarities are changed, a p-channel MIS field-effect transistor using an n-type substrate can be realized. Example 4 A semiconductor device shown in FIG. 11 was obtained by the same process as in Example 3. The difference from the third embodiment is that the width of the second gate is 0.05 μm, the electrons in the portion subjected to the control of the energy level are nearly zero-dimensional, and the state density is shown in FIG. ) Is completely discontinuous. Further, as a result of suppressing the influence of scattering, the conduction is close to ballistic. As a result, in this embodiment, the vibration could be clarified more than in the third embodiment. Fifth Embodiment FIG. 12 is a circuit diagram of an example in which an exclusive OR circuit is configured using the semiconductor device according to the first to fourth embodiments.
The two output terminals V _IN 1 and V _IN 2 are connected to the second
The output terminal V _OUT is connected to one of the source 1 ′ or the drain 2 ′, and the power supply terminal V _D is connected to one of the source 1 ′ or the drain 2 ′ via a resistor. Or the other of the drain 2 'is grounded. When a semiconductor device having the characteristics shown in FIG. 13 was used, the output corresponding to the input was as shown in Table 1, and an exclusive OR circuit could be formed.

【The invention's effect】

According to the present invention described above, the conductivity of the MIS field effect transistor is periodically controlled by the second gate electrode by utilizing the control of the discontinuous energy level formed due to the one-dimensional conduction. Can be modulated. this is,
In a macro device, a characteristic that requires a complicated circuit configuration is realized by a fine and single element.
In this sense, the present invention can be effective for future LSIs and the like.

[Brief description of the drawings]

1 (a) is a plan view of one embodiment of the field effect transistor of the present invention, FIG. 1 (b) is a sectional view taken along the line AA ', FIG. 2 is a view showing energy levels, FIG. One-dimensional channel MO
FIG. 4 is a diagram showing voltage-current characteristics of an S-type field effect transistor, FIG. 4 is a cross-sectional view of an element for explaining the function of a second gate electrode, and FIG. 5 is a diagram showing the second gate voltage dependence of current. FIG. 6 is a view showing a manufacturing process of the field-effect transistor according to the first embodiment, FIG. 7 is a cross-sectional view of the field-effect transistor according to the second embodiment, and FIG. FIG. 9 is a view showing the density, FIG. 9 is a view showing the characteristics of the field-effect transistor of the second embodiment, FIG. 10 is a view showing the manufacturing process of the field-effect transistor of the third embodiment, and FIG. , FIG. 12 is an exclusive OR circuit diagram constructed according to the present invention, and FIG. 13 is a characteristic diagram of a semiconductor device when an exclusive OR circuit is realized. DESCRIPTION OF SYMBOLS 1 ... Source area, 2 ... Drain area 1 '... Source, 2' ... Drain 3 ... 1st gate electrode 4 ... 2nd gate electrode 5 ... Si substrate, 6 ... Gate oxidation film 6 '...... SiO _2, 7 ...... interlayer insulating film 8 ...... channel 9 ...... isolation region 10 ...... polycrystalline silicon, 11 ...... aluminum electrode

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-154668 (JP, A) JP-A-61-57119 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/78

Claims (12)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, and source and drain regions of a second conductivity type formed on the surface of the semiconductor substrate at predetermined intervals and having a conductivity type different from the first conductivity type. A first gate electrode formed on the semiconductor substrate between the source and drain regions with a gate insulating film interposed therebetween, comprising: an insulated gate field effect transistor; The width is such that the channel formed by the first gate electrode forms one-dimensional conduction of electrons, and the width of the channel is reduced in one portion of the first gate electrode via an insulating film. Semiconductor device, wherein the second gate electrode is arranged as described above. 2. The semiconductor device according to claim 1, wherein said first gate electrode has a width of 0.1 μm or less. 3. The semiconductor device according to claim 1, wherein a width of said second gate electrode is 0.1 μm or less. 4. A semiconductor substrate of a first conductivity type, and source and drain regions of a second conductivity type formed on the surface of the semiconductor substrate at predetermined intervals and having a conductivity type different from the first conductivity type. A gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween to form a channel between the source and drain regions, a semiconductor device having an insulated gate field effect transistor, The width is such that the channel formed by the gate electrode constitutes one-dimensional conduction of electrons, and has a means for controlling so as to increase the quantized energy level of the energy of the electrons traveling through the channel. Semiconductor device. 5. The semiconductor device according to claim 4, wherein the control of the quantized energy level is performed by a second gate electrode which is electrically insulated from said gate electrode via an insulating film. Semiconductor device. 6. The semiconductor device according to claim 4, wherein a portion of the channel whose energy level is controlled has a length of 0.1 μm or less. 7. A semiconductor substrate of a first conductivity type, and source and drain regions of a second conductivity type, which are formed at predetermined intervals on a surface of the semiconductor substrate and have a different conductivity type from the first conductivity type, A semiconductor device having an insulated gate field effect transistor comprising a channel formed between the source and drain regions, wherein the width of the channel is such that the channel forms one-dimensional conduction of electrons; A semiconductor device, wherein a gate electrode is arranged at one portion of the semiconductor device via an insulating film so as to reduce the width of the channel. 8. The semiconductor device according to claim 7, wherein the width of the channel is 0.1 μm or less. 9. The semiconductor device according to claim 7, wherein said gate electrode has a width of 0.1 μm or less. 10. A semiconductor substrate of a first conductivity type, and source and drain regions of a second conductivity type formed on the surface of the semiconductor substrate at predetermined intervals and having a conductivity type different from the first conductivity type. A first gate electrode provided on the semiconductor substrate between the source and drain regions via a gate insulating film, and a second gate provided on a portion of the first gate electrode via an insulating film An insulated gate field effect transistor comprising: an electrode; and a width of the first gate electrode is such that a channel formed by the first gate electrode constitutes one-dimensional conduction of electrons; The gate electrode is configured to reduce the width of the channel, and is connected to two input terminals connected to the second gate electrode via resistors, respectively, and to one of the source and drain regions. Output terminal and resistance Power source terminal connected via
A logic circuit having a ground terminal connected to the other of the drain regions. 11. A semiconductor substrate of a first conductivity type, and source and drain regions of a second conductivity type, which are formed at predetermined intervals on the surface of the semiconductor substrate and have a conductivity type different from the first conductivity type. A gate electrode provided on the semiconductor substrate via a gate insulating film to form a channel between the source and drain regions, and a step of increasing a quantized energy level of energy of electrons traveling through the channel. The width of the gate electrode is a width of a channel formed by the gate electrode constituting one-dimensional conduction of electrons, and the energy level is controlled. Means, two input terminals connected to each other via a resistor, an output terminal connected to one of the source and drain regions, and a power supply connected via a resistor. Logic circuit and having a terminal, the source, and a ground terminal connected to the other drain regions. 12. A semiconductor substrate of a first conductivity type, and source and drain regions of a second conductivity type formed on the surface of the semiconductor substrate at predetermined intervals and having a conductivity type different from the first conductivity type. A channel provided between the source and drain regions, and an insulated gate field effect transistor including a gate electrode provided on one portion of the channel with an insulating film interposed therebetween. The channel has a width that constitutes one-dimensional conduction of electrons, the gate electrode is configured to reduce the width of the channel, and two input terminals connected to the gate electrode via resistors, respectively, An output terminal connected to one of the source and drain regions, a power terminal connected via a resistor, and a ground terminal connected to the other of the source and drain regions. Circuit.