JP2888878B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device formed on a semiconductor film laminated on an insulating film, and more particularly to an improvement in performance.

(Prior Art) As a field effect transistor (FET) formed on a semiconductor film (SOI film) formed on an insulating film, for example, a MOS transistor, there is a structure as shown in FIG. 9, for example.

In FIG. 9, an insulating film 2 is formed on, for example, a silicon substrate 1 as a semiconductor substrate, and an SOI film 3 which is thinned to be an element formation region is formed on the insulating film 2.

In the SOI film 3, a source region 4 and a drain region 5 formed of, for example, n ⁺ -type impurity regions are formed at a predetermined distance from each other. A gate electrode 8 made of, for example, a polycrystalline silicon film is formed via a gate insulating film 7 on a P-type channel region 6 formed in the SOI film 3 sandwiched between these two regions. In the source region 4 and the drain region 5, an electrode wiring 10 is formed with an opening in an insulating film 9 covering the surface.

In such an SOI structure FET, the SOI film 3 is
It has been reported that many properties can be improved by thinning to a thickness of about Å (M. Yoshimi
IEDM, Technical Digest, P640, 1987).

However, as the thickness of the SOI film becomes thinner, drain breakdown in which the drain current rapidly increases with the drain voltage has been apt to occur. In addition, since the drain breakdown is conspicuous in an N-type transistor, it causes a disadvantage that the power supply voltage is restricted.

The holes generated in the drain region and moving to the source region through the channel region are transferred to the source region due to an energy barrier generated in a valence band at a PN junction between the SOI film in the channel region and the source region. Hindered.
As a result, holes whose movement has been prevented are accumulated near the PN junction region between the source region and the channel region, and the PN junction is biased in the forward direction. For this reason, the number of electrons injected into the drain region increases, the electric field at the junction region between the drain region and the channel region increases, and the drain is destroyed.

In addition, since the depth of the drain region is equal to the thickness of the SOI film, the curvature of the junction surface of the drain region with the channel region becomes sharper as the SOI film becomes thinner, which facilitates concentration of the electric field, The electric field near the dray increases.

Further, in the case of an N-channel transistor, the n-type impurity ion-implanted into the drain region diffuses in the SOI film in the lateral direction, and the impurity concentration near the junction surface with the channel region increases. Destruction was likely to occur.

As a countermeasure against such a problem, a conventionally known LDD (Lightly-Doped Drain) structure is used for the drain structure, so that the drain electric field can be reduced and the drain withstand voltage can be improved. However, the effect was not sufficient, and further improvement was required.

On the other hand, for SOI-structured FETs, the threshold voltage is almost uniquely determined by the difference in the work relationship between the gate electrode material and the SOI film in the channel region. Magazine, C-2, Vol.J72-C-2: No. 5,
p.510 "and the like. Therefore,
A threshold voltage stable in process can be obtained.

FIG. 10 is a diagram showing threshold voltages of N-channel and P-channel FETs when three typical gate electrode materials are used. The threshold voltage shown in the figure is a value when the SOI film contains a P-type impurity of about 10 ¹⁵ cm ⁻³ and the thickness is about 500 °.

In FIG. 10, when phosphorus-doped (N.sup. ⁺ ) Polysilicon, which is most commonly used, is used, the N-channel FET becomes a depletion type, as is apparent from FIG. For this reason, there has been a disadvantage that a sufficient logic amplitude cannot be obtained in the CMOS circuit.

Therefore, if a P-type impurity is introduced into the SOI film to about 10 ¹⁷ cm ⁻³ , the N-channel FET becomes an enhancement type. However, in such a case, the advantage of lowering the concentration of the SOI film, which is a feature of the SOI structure, is significantly impaired.

On the other hand, when polon-doped (P ⁺ ) polysilicon is used for the gate electrode, the N-channel FET is an enhancement type, as is apparent from FIG. However, the P-channel FET becomes a depletion type, and the situation is not improved.

Therefore, as a method of making both N-channel and P-channel enhancement types, boron-doped polysilicon is used for the gate electrode of the N-channel FET, and the P-channel FE is used.
A method using phosphorus-doped polysilicon for the T gate electrode is considered. However, such a method causes a problem that the manufacturing process is complicated.

The threshold voltage obtained by the above structure is +0.9 V for the N channel and -0.9 V for the P channel. For this reason, it is too high to cope with a reduction in power supply voltage due to miniaturization of elements and an increase in the speed of circuit operation. Furthermore, SO
It was not possible to arbitrarily set the threshold voltage according to the characteristics of the circuit without deteriorating the advantages of the I structure.

On the other hand, as a second method, it is conceivable to use a metal material such as tungsten (W) or molybdenum (Mo). However, in such a method, since the processing of the metal material is difficult, there is a problem that the manufacturing becomes difficult. Further, the disadvantage that the threshold voltage is uniquely set is still not solved.

(Problems to be Solved by the Invention) As described above, in a conventional SOI-structure FET, drain breakdown is likely to occur as the SOI film becomes thinner, and the power supply voltage is limited.

Also, it has been difficult to make both N-channel and P-channel FETs enhancement type without deteriorating the features of the SOI structure. Furthermore, the threshold voltage cannot be set arbitrarily according to the characteristics of the circuit to be used, which has been a serious obstacle to circuit design.

Therefore, the present invention has been made in view of the above, and it is an object of the present invention to increase the drain withstand voltage and extend the usable range of the power supply voltage without impairing the characteristics of the SOI structure. The present invention is to provide a semiconductor device in which FET performance is improved.

In addition, the present invention has the object of not impairing the characteristics of the SOI structure, and further complicating the manufacturing method,
It is an object of the present invention to provide a semiconductor device in which the degree of freedom in setting a threshold voltage is greatly improved without causing difficulty, and the performance of an FET in an SOI structure is improved.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the above object, a pair of second conductive layers provided at a predetermined distance from a first conductive type semiconductor film formed on an insulating film is provided. In a semiconductor device provided with a conductive impurity region and a gate electrode formed on a channel region interposed between the two regions via a gate insulating film, the present invention provides a semiconductor device in which at least one of the impurity regions comprises the semiconductor The forbidden band width is narrower than that of the film.

(Operation) In the above one configuration, the first invention suppresses the accumulation of carriers in the junction region by relaxing the energy barrier at the junction between the one impurity region and the channel region, and suppresses the accumulation of carriers in the other impurity region. An increase in the electric field is suppressed.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor device having an SOI structure according to an embodiment of the first invention.

The feature of the N-channel FET in the SOI structure shown in FIG. 1 is that a source region 11 and a drain region 12 are formed and a channel region 6 is formed in the structure shown in FIG.
A mixed crystal of silicon and germanium (SixGe) that has a narrower energy band gap (bandgap) than silicon in the SOI film
(1-x)). Further, in the junction between the channel region 6 and the source region 11, the forbidden band width of silicon / germanium is adjusted by adjusting the ratio of a mixed crystal of silicon and germanium and the amount of impurities such as phosphorus, so that The valence band junction state in the PN junction with the source region 11 is made substantially flat.

For example, when the thickness of the SOI film is reduced to about 1000 °, when the mixed crystal ratio of silicon and germanium is x = 0.1 and the source region 11 is formed using Si _0.1 Ge _0.9 ,
Silicon in the channel region 6 and silicon in the source region 11
The difference in band gap from germanium is about 0.2 eV. For this reason, in conventional junctions using only silicon, 0.
The band gap difference that existed at about 2 eV disappears.

Therefore, in the energy band structure of the SOI film 3, the valence band in the source region 11 and the drain region 12 has conventionally existed as shown by the dotted line (conventional example) to the solid line (example) in FIG. The energy gap (Eg) increases, and the valence band between the source region 11 and the channel region 6 becomes substantially flat. At this time, the position of the Fermi level in the silicon-germanium mixed crystal is determined so that when the silicon-germanium and silicon are joined and the Fermi levels coincide, the valence bands in both regions become almost flat. Has been adjusted.

Thereby, the valence band energy barrier at the PN junction between the source region 11 and the channel 6 is almost eliminated.
For this reason, holes flowing from the channel region 6 toward the source region 11 quickly flow out to the source region 11, and the accumulation of holes in the junction region is suppressed.

Therefore, a rapid increase in electrons injected into the drain region 12 is suppressed, and in a FET having a channel length of about 2 μm, the drain withstand voltage can be improved by about 3 V as shown in FIG. Become.

On the other hand, the energy gap of the valence band at the PN junction between the source region 11 and the channel region 6 is effectively relaxed,
In order to improve the drain withstand voltage, it is necessary to reduce the thickness of the SOI film forming the source region 11 and the channel region 6. This film thickness (T) is defined as the maximum thickness that can completely deplete the channel region, and is expressed by the following equation.

T = 2 [εF / (qNs)] _1/2 where ε is the dielectric constant, and φF is the Fermi energy (e
V) and q are basic electron charges (cooling), and Ns is an impurity concentration (cm ^-3 ).

If the SOI film is set to be equal to or less than the film thickness (T) represented by the above equation, the drain withstand voltage can be improved as shown in FIG.

Next, a method of manufacturing the FET having the SOI structure shown in FIG. 1 will be described with reference to the manufacturing process sectional views shown in FIG.

First, oxygen ions are applied to a single crystal silicon substrate 1 for 120K.
Ion implantation is performed at an acceleration voltage of about V and a dose of about 2 × 10 ¹⁸ cm ⁻² . Thereafter, an annealing process is performed at a temperature of about 1300 ° C. for about 20 hours. As a result, a silicon oxide film (SiO ₂ film) 2 of about 2000 °
An SOI film 3 having a reduced thickness is formed (FIG. 5A).

Next, the SOI film 3 is separated into islands by etching,
An element formation region of the OI film 3 is formed. Thereafter, a gate oxide film 7 is deposited on the surface of the SOI film 3 to a thickness of about 500 °. Subsequently, for example, boron which becomes a P-type impurity is ion-implanted into the SOI film 3 to make the SOI film 3 P-type (FIG. 5B).

Next, a polysilicon film 13 serving as the gate electrode 8 is formed on the entire surface.
Deposited by CVD. After that, phosphorus is diffused and introduced into the deposited polysilicon film 13 so that the polysilicon film 13 is
Reduce the resistance to about Ω / □. Subsequently, the polysilicon film 13
A patterned resist 14 is formed thereon (FIG. 5 (c)).

Next, using the resist 14 as a mask, a part of the polysilicon film 13 is etched and removed by RIE to form a gate electrode 8. Subsequently, after removing the resist 14, an oxidation process is performed in an oxidizing atmosphere to form an oxide film on the entire surface. At this time, the thickness of the oxide film formed on the surface of the gate electrode 8 is larger than the thickness of the oxide film formed on the surface of the SOI film 3 due to the difference in oxidation rate between the polysilicon film and the silicon film. It grows and forms. Therefore, the oxide film formed on the SOI film 3 by the wet etching method is removed.
Thus, the gate electrode 8 is covered with the gate oxide film 7, and the surface of the SOI film 3 is exposed (FIG. 5D).

Next, the exposed SOI film 3 is etched away by about several hundreds of mm. After that, molecular beam epitaxy (MBE)
As a result, a mixed crystal of silicon and germanium (SixGe (1-x)) having a thickness (T) having the thickness (T) is formed on the portion removed by etching, using the SOI film 3 exposed and remaining on the insulating film 2 as a growth seed. It grows and forms so as to satisfy the conditions. As a result, the source region made of a mixed crystal of silicon and germanium
11 and a drain region 12 are formed (FIG. 5E).

When a mixed crystal of silicon and germanium is grown and formed, the SOI film 3 exposed and left on the insulating film 2 is not formed as a growth seed, and the SOI film 3 is not left on the insulating film 2. The source region 11 and the drain region 12 are directly formed on the insulating film 2.
May be formed.

Finally, an insulating film 9 for protecting the surface is deposited and formed on the entire surface, and a contact hole is formed in the insulating film 9 on the source region 11 and the drain region 12, and the source region 11 and the drain region 12 are formed through the contact hole. Top electrode wiring 10
Is formed (FIG. 5 (d)), and the structure as shown in FIG. 1 is obtained.

It should be noted that the present invention is not limited to the above embodiment. For example, in the case of an N-channel FET, it is only necessary to relax the energy barrier of the valence band with respect to holes. The same effect can be obtained by forming the layer 6 from a material having a smaller band gap than that of the material constituting 6.

Further, the band gap is narrower than that of the SOI film, and the material for forming the source region and the drain region which relaxes the energy barrier at the junction with the SOI film is not limited to silicon germanium. For example, Ge (Eg = 0.6e
V), GaSb (Eg = 0.72 eV), InAs (Eg = 0.36 eV), PbS
(Eg = 0.41 eV), PbTe (Eg = 0.31 eV), or the like.

 Next, an embodiment of the second invention will be described.

FIG. 6 is a view showing a cross-sectional structure of a CMOSFET in an SOI structure according to an embodiment of the second invention.

The feature of this embodiment is that in FIG.
A CMOS in which an N-channel FET 21a and a P-channel FET 21b are formed adjacent to each other on an SOI film 3 separately formed on an insulating film 2 on a P-type single crystal silicon substrate 1.
In the structure, an n ⁺ -type high-concentration impurity region 22a is formed in the junction region with the insulating film 2 in the substrate 1 below the N-channel FET 21a, and the insulating film 2 in the substrate 1 below the P-channel FET 21b is formed.
A p ⁺ -type high-concentration impurity region 22b is formed in the junction region with the wirings 2a and 2b connected to the respective regions 22a and 22b.
A substrate bias voltage is applied independently via 3a and 23b, thereby controlling the threshold voltage of each FET.

FIG. 7 is a diagram showing the relationship between the substrate bias voltage applied to each of the impurity regions 22a and 22b and the threshold voltage of the FET of each channel. In the figure, when an n ⁺ -type polysilicon doped with, for example, phosphorus is used as the material of the gate voltage, the substrate bias voltage (Vsub) is a positive value, and the threshold voltage is indicated by a solid line. On the other hand, when p ⁺ type polysilicon doped with, for example, boron is used as the material of the gate electrode, the substrate bias voltage (Vsub) is a negative value, and the threshold voltage is indicated by a dotted line.

As is clear from FIG. 7, it is possible to apply a substrate bias voltage independently to each of the high-concentration impurity regions 22a and 22b, so that the N-channel FET and the P-channel FET can be applied independently. The threshold voltage can be set arbitrarily within the range of | 1 | V or less. Also, the FE of both channels
Even if the same gate electrode material is used for both T, both channel FETs can be of enhancement type.

From these, without complicating manufacturing fixation,
Further, it is possible to arbitrarily set a threshold electrode according to the characteristics of a circuit to be used without deteriorating the advantage of the SOI structure. Therefore, the degree of freedom in designing a circuit using the CMOS having the SOI structure is expanded, and it is possible to contribute to the high performance of the circuit.

Note that the substrate bias voltage applied to each of the impurity regions 22a and 22b is different from that of each of the impurity regions 22a and 22b in a voltage relationship where the two impurity regions 22a and 22b do not enter the forward bias state.
shall be given to b.

Next, a method of manufacturing the CMOS having the SOI structure shown in FIG. 6 will be described with reference to the manufacturing process sectional views shown in FIG.

First, oxygen ions are implanted into a P-type single crystal silicon substrate 1 at an acceleration voltage of about 120 KV and a dose of about 2 × 10 ¹⁸ cm ⁻² . Thereafter, annealing is performed at a temperature of about 1300 ° C. for about 20 hours. Thus, an insulating film 2 made of a silicon oxide film having a thickness of about 2000 ° and an SOI film 3 having a thickness of about 750 ° are formed on the silicon substrate 1 (FIG. 8A).

Next, a resist pattern 24 having an opening in a region for forming an N-channel FET is formed on the SOI film 3. Thereafter, using this resist pattern 24 as a mask, phosphorus ions are implanted into the substrate 1 under the N-channel FET formation region at an acceleration voltage of about 1 MV and a dose of about 10 ¹⁵ cm ⁻² (FIG. 8). (B)).

As a result, the bonding area with the insulating film 2 in the substrate 1
N ⁺ -type high-concentration impurity region containing about ¹⁹ to 10 ²⁰ cm ^-3 of phosphorus
Form 22a. Similarly, a p ⁺ -type high-concentration impurity region 22b containing, for example, boron having the same concentration is formed under the P-channel FET formation region. Thereafter, a resist pattern (not shown) remaining only on the formation regions of both channels is formed.
The SOI film 3 is formed on the SOI film 3 and a part of the SOI film 3 is removed by etching using the resist pattern as a mask to form an element forming region 25 made of the island-shaped SOI film 3. Subsequently, a gate oxide film 26 having a thickness of about 500 ° is formed on the surface of each element formation region 25 (FIG. 8C).

Next, a polysilicon film to be the gate electrode 8 is formed on the entire surface by CV.
Deposition is formed by the D method. After that, phosphorus is diffused and introduced into the deposited polysilicon film to form the polysilicon film at 20Ω / □.
The resistance is reduced to the extent. Subsequently, using the patterned resist as a mask, a part of the polysilicon film is removed by etching by the RIE method, and gate electrodes 8 of both FETs are formed at substantially central portions on the respective element formation regions 25 (FIG. 8). (D)).

Next, for example, arsenic impurities are ion-implanted into the SOI film 3 in one element formation region 25 at a high concentration at an acceleration voltage of about 40 KV. Thus, source and drain regions 27a and 28a of the N-channel FET 21a are formed. In addition, for example, boron ions are implanted into the SOI film 3 in the other element formation region 25 at a high concentration at an acceleration voltage of about 20 KV. This allows
Source and drain regions 27b, 28 of P-channel FET 21b
b is formed (FIG. 8 (e)).

Next, an insulating film 9 made of, for example, a silicon oxide film is formed on the entire surface.
A contact hole 29 having a depth reaching the source and drain regions 27a, 27b, 28a, 28b of both FETs and a contact having a depth reaching the respective high-concentration impurity regions 22a, 22b are formed in the insulating film 9. Open the hole 30 (eighth
Figure (e).

Finally, electrode wirings 10, 23a, 23b are formed through these contact holes 29, 30, and the CMOS structure shown in FIG. 8 is completed.

Note that the second invention is not limited to the above embodiment,
For example, the concentration of each of the high-concentration impurity regions to which the substrate bias voltage is applied is such that when the substrate bias voltage is applied, the impurity region is not depleted, and the electric field due to the substrate bias voltage effectively acts on the channel region of the FET. Any degree is acceptable.

Further, the conductivity type of the high-concentration impurity region does not always match the conductivity type of the FET, and an appropriate conductivity type may be selected according to the material of the gate electrode of the FET.

[Effects of the Invention] As described above, according to the first invention, at least one impurity region to be joined to the channel region is formed with a material having a narrower band width than the channel region. The energy barrier at the junction with the channel region can be reduced, and the accumulation of carriers can be controlled. Thereby, an increase in the electric field in the other impurity region is suppressed, and the drain withstand voltage can be improved.
As a result, the performance of the semiconductor device in the SOI structure can be improved.

On the other hand, according to the second invention, a predetermined bias potential is independently applied to each of the impurity regions formed separately corresponding to each FET. Therefore, the threshold voltage of each FET is reduced. , Can be independently set to an arbitrary value according to the substrate bias potential. Thus, the threshold voltage can be selected according to the characteristics of the circuit, and the degree of freedom in circuit design can be greatly improved. As a result, the performance of the semiconductor device in the SOI structure can be improved.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a semiconductor device according to an embodiment of the first invention, FIG. 2 is an energy band diagram of the device shown in FIG. 1, and FIG. FIG. 4 is a diagram showing the relationship between the drain breakdown voltage and the drain film thickness of the device shown in FIG. 1, and FIG. 5 is a process sectional view showing a method for manufacturing the device shown in FIG. 6, FIG. 6 is a sectional view showing the structure of a semiconductor device according to an embodiment of the second invention, FIG. 7 is a diagram showing the characteristics of the threshold voltage of the device shown in FIG. 6, and FIG. 9 is a cross-sectional view showing one structure of a semiconductor device having a conventional SOI structure. FIG. 10 is a sectional view showing a threshold voltage and a gate electrode of a semiconductor device having a conventional SOI structure. FIG. 3 is a diagram showing a relationship with a material. 1 ... semiconductor substrate, 2,9 ... insulating film, 3 ... SOI film, 4,1
1, 27a, 27b ... source region, 5, 12, 28a, 28b ... drain region, 6 ... channel region, 7, 26 ... gate insulating film, 8
... Gate electrode, 10, 23a, 23b ... Electrode wiring, 13 ... Polysilicon film, 14, 24 ... Resist, 21a ... N-channel FE
T, 21b... P-channel FET, 22a... N ⁺ -type high concentration impurity region, 22b... P ⁺ -type high concentration impurity region, 25...

Claims (3)

(57) [Claims] A first conductive type semiconductor film formed on an insulating film and a pair of second conductive type impurity regions provided at a predetermined distance from each other; and a channel region interposed between the pair of second conductive type impurity regions. A semiconductor device provided with a gate electrode formed with a gate insulating film interposed therebetween, wherein at least one of the impurity regions has a narrower forbidden band width than the semiconductor film. 2. The semiconductor device according to claim 1, wherein a thickness of said semiconductor film is equal to or less than a thickness capable of completely depleting said channel region. 3. The semiconductor device according to claim 1, wherein said impurity region having a narrower forbidden band width than said semiconductor film contains silicon and germanium.