JP2013232471A - Complementary semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a complementary semiconductor device which achieves a CMOS structure using a Ge channel at a low temperature and at a low cost, enhances performance, and reduces power consumption.SOLUTION: A complementary semiconductor device using a Ge channel comprises: n-type first and second semiconductor layers 21 formed on an underlayer insulating film 12, and whose main component is Ge; an nMOSFET whose gate electrode 23 is formed on the first semiconductor layer 21 via a gate insulating film 22, and whose channel and source/drain are semiconductor layers of the same conductivity type; and a pMOSFET whose gate electrode 23 is formed on the second semiconductor layer 21 via the gate insulating film 22, and whose source/drain region is formed of an alloy layer 25 of the second semiconductor layer 21 and a metal.

Description

  Embodiments described herein relate generally to a complementary semiconductor device using a Ge channel and a method for manufacturing the same.

  In high performance and low power consumption of semiconductor integrated circuits, three-dimensional stacking of transistors is effective for reducing parasitic capacitance and parasitic resistance by shortening the wiring length. Three-dimensionalization is already underway to develop a technology for stacking Si chips and connecting them with TSV (Through Silicon Via). However, since the TSV size is more than two digits larger than the wiring interval of a normal CMOS process, the connection density is increased. Therefore, there is a limit to improving wiring efficiency. In addition, since the area penalty for TSV is so large that it cannot be ignored, circuit design is hindered and costs are increased. Therefore, a technology capable of wiring connection with higher density is required.

  As such a technique, a technique in which a part of a circuit is extracted and laminated as an a-Si-TFT during or after the CMOS wiring process is reported (for example, see Non-Patent Document 1). However, since the performance of a-Si-TFT is extremely poor compared to normal Si-CMOS, there are various restrictions such as high driving voltage or insufficient performance, and the three-dimensional advantage cannot be fully enjoyed. .

  In addition, in a structure in which crystalline Si is bonded onto a CMOS wiring layer, performance comparable to that of the underlying CMOS can be obtained (see, for example, Non-Patent Document 2). However, in this case, since the process temperature is as high as 600 degrees, the materials and processes that can be used for the underlying CMOS are limited.

T. Naito et al., 2010 Symposium on VLSI Technology, Technical Digest Papers, p.219 P. Batude et al., IEDM Technical Digest, p.151

  The problem to be solved by the present invention is to provide a complementary semiconductor device capable of realizing a CMOS structure using a Ge channel at a low temperature and at a low cost, and capable of achieving high performance and low power consumption, and a manufacturing method thereof. That is.

  The complementary semiconductor device according to the embodiment includes an n-type first and second semiconductor layers mainly composed of Ge formed on a base insulating film, and a gate insulating film on the first semiconductor layer. The gate electrode is formed, the channel and the source / drain are nMOSFETs having the same polarity semiconductor layer, the gate electrode is formed on the second semiconductor layer via the gate insulating film, and the source / drain region is A pMOSFET formed of an alloy layer of a second semiconductor layer and a metal.

  According to the present invention, by using the Ge channel on the base insulating film, it is possible to lower the process temperature and to improve the performance (lower voltage) by higher mobility than Si. In addition, by sharing the n-type Ge channel between the pMOSFET and the nMOSFET, the cost of the CMOS process can be reduced. Furthermore, by selecting an n-type Ge channel that is advantageous in reducing the resistance of the nMOSFET, the problem that it is difficult to reduce the Ge / metal contact for the nMOSFET, which is a problem inherent to Ge-CMOS, is solved.

  As described above, the combination of the channel material, polarity, and electrode structure of this configuration comprehensively solves the problems of the background art, thereby improving the performance, power consumption, and cost of 3D CMOS. Can contribute.

1 is a cross-sectional view showing an element structure of a complementary semiconductor device according to a first embodiment. Sectional drawing which shows the manufacturing process of the complementary type semiconductor device concerning 1st Embodiment. Sectional drawing which shows the manufacturing process of the complementary type semiconductor device concerning 1st Embodiment. Sectional drawing which shows the element structure of the complementary semiconductor device concerning 2nd Embodiment. Sectional drawing which shows the manufacturing process of the complementary semiconductor device concerning 2nd Embodiment. Sectional drawing which shows the element structure of the complementary semiconductor device concerning 3rd Embodiment. Sectional drawing which shows the element structure of the complementary semiconductor device concerning 4th Embodiment. The figure which shows the threshold value characteristic of pMOSFET and nMOSFET for demonstrating the effect of 4th Embodiment. Sectional drawing which shows the element structure of the complementary semiconductor device concerning 5th Embodiment. Sectional drawing which shows the element structure of the complementary semiconductor device concerning 6th Embodiment. Sectional drawing which shows the element structure of the laminated type semiconductor device concerning 7th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing an element structure of a complementary semiconductor device according to the first embodiment.

A base insulating film 12 such as SiO ₂ or SiN and an n-type polyGe layer 21 (30 nm) serving as a channel are sequentially stacked on a Si support substrate 11. The Ge layer 21 is doped with P (phosphorus) at a high concentration and becomes n ⁺ type (concentration 1.0 × 10 ¹⁹ cm ⁻² ). Further, the Ge layer 21 is element-isolated in an nMOS region 100 and a pMOS region 200. The nMOS region 100 constitutes an nMOSFET channel, and the pMOS region 200 constitutes a pMOSFET channel. Yes. That is, both nMOSFET and pMOSFET use n-type Ge for the channel. Therefore, the nMOSFET operates as a depletion type and the pMOSFET operates as an inverting type.

In each of the nMOS region 100 and the pMOS region 200, a gate insulating film 22 made of Al ₂ O ₃ (4 nm) and a gate electrode 23 made of TaN (30 nm) are sequentially stacked on the Ge layer 21 to form a gate stack. ing. A gate sidewall insulating film 24 such as TaNO is formed on the side surface of the gate electrode 23. In the pMOS region 200, a source / drain region (metal S / D) 25 made of a NiGe alloy is formed with a gate stack interposed therebetween.

An interlayer insulating film 26 made of SiO ₂ or the like is formed on the substrate on which the gate stack and the metal S / D 25 are formed. Contact holes are formed in the interlayer insulating film 26, and W (tungsten) electrode plugs 27 are provided so as to fill the contact holes. In the pMOS region 200, the electrode plug 27 is connected to the metal S / D 25, and in the nMOS region 100, the electrode plug 27 is connected to the Ge layer 21. Here, a TiN barrier metal 28 is inserted between the electrode plug 27 and the metal S / D 25 or the Ge layer 21. A wiring 29 connected to the electrode plug 27 is provided on the interlayer insulating film 26.

  Next, the manufacturing method of this embodiment is demonstrated with reference to FIG.2 and FIG.3.

  First, as shown in FIG. 2A, a P-doped amorphous Ge film 13 is grown on the base insulating film 12 on the Si support substrate 11 by CVD or sputtering.

Next, by annealing at 350 ° C. to 500 ° C., an n-type polyGe layer 21 is formed as shown in FIG. An insulating film such as SiO ₂ may be deposited on the amorphous Ge film 13 as a protective film before annealing. Here, although the Ge layer 21 is polycrystalline, when the element is miniaturized and the channel length becomes close to the grain size, even if it is polycrystalline, it can be regarded as substantially the same as a single crystal. .

Next, as shown in FIG. 2C, after the Ge layer 21 is separated into an nMOS region 100 and a pMOS region 200 in an island shape, an Al ₂ O ₃ film (gate insulating film) 22 having a thickness of 4 nm is formed. A TaN film (gate electrode) 23 having a thickness of 30 nm is sequentially stacked.

  Next, as shown in FIG. 2D, a gate pattern is formed by lithography and RIE, the gate insulating film 22 and the gate electrode 23 are processed for pMOS and nMOS, respectively, and the source / drain portions are exposed. At this time, both sides of the gate electrode 23 are oxidized to form the sidewall insulating film 24.

Next, as shown in FIG. 3E, after depositing the SiO ₂ protective insulating film 31 by the CVD method, only the pMOS region 200 is exposed by lithography and wet etching, and the protective insulating film 31 is left in the nMOS region 100. Then, a Ni film 32 is deposited on the entire surface by sputtering or the like.

  Next, as shown in FIG. 3F, heat treatment is performed at 250 ° C. to 350 ° C. to form the NiGe alloy layer 25 in the source / drain portion of the pMOS region 200, and the unreacted Ni film 31 is diluted with dilute hydrochloric acid or the like. Remove. Here, the NiGe alloy layer 25 becomes the metal S / D for the pMOSFET. On the other hand, no NiGe alloy is formed in the nMOS region 100.

In the nMOSFET and the pMOSFET manufactured as described above, the channel is the n ⁺ type poly Ge layer 21 and is deposited on the base insulating film 12, and the nMOSFET is depleted and the pMOSFET is in an inverting operation. Further, the nMOSFET is a so-called junctionless transistor having no pn junction between the source / drain (S / D) and the channel, and the pMOSFET is a transistor having a metal S / D without using a p-type impurity.

Next, as shown in FIG. 3G, an interlayer insulating film 26 such as SiO ₂ is deposited by plasma CVD or the like, planarized by CMP, and contact holes are formed by lithography and RIE. That is, in the pMOS region 200, a contact hole is formed on the metal S / D 25, and in the nMOS region 100, a contact hole is formed on the Ge layer 21 with the gate stack interposed therebetween. Subsequently, a TiN barrier metal 28 is formed at the bottom of the contact hole, and the contact hole is further filled with a W plug 27.

  Thereafter, the W and TiN metals on the surface are again removed by CMP, and then the Al wiring 29 is formed to form the CMOS circuit, thereby completing the structure shown in FIG.

  As described above, according to this embodiment, since the n-type polyGe layer 21 which is the same material for both the pMOS and nMOS is used as a channel, the process becomes easier as compared with the case where different semiconductor materials are used. That is, only the process of forming the source / drain regions is different between the pMOS and the nMOS, and other processes are common, so that the entire process can be simplified.

  In addition, since Ge, which has higher mobility than Si, is used, a higher speed device can be manufactured. Further, since Ge can be formed at a lower temperature than Si, for example, when this structure is laminated three-dimensionally, the influence on the underlying device can be reduced.

  Further, by selecting an n-type Ge channel that is advantageous for reducing the resistance of the nMOSFET, the problem that it is difficult to reduce the resistance of the Ge / metal contact for nMOSFET, which is a problem inherent to Ge-CMOS, is solved.

  Further, in the pMOS, since the source / drain is made of NiGe alloy, the resistance of the source / drain can be reduced. Further, the connection resistance with the electrode plug 27 can be reduced. Further, since the contact between the source / drain and the electrode plug is only n-type Ge and metal, there is an advantage that the contact becomes easy.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing the element structure of the complementary semiconductor device according to the second embodiment. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  This embodiment is different from the first embodiment described above in that the source / drain of the nMOS region 100 is formed of a NiGe alloy, and a high concentration segregation region 40 of S (sulfur) is formed between the alloy and the Ge channel. Is formed. Other configurations are the same as those in the first embodiment.

  With the configuration of this embodiment, the parasitic resistance component of the nMOSFET can be further reduced as compared with the first embodiment.

  Next, the manufacturing method of this embodiment is demonstrated with reference to FIG.

  First, in the same manner as shown in FIGS. 2A to 2D, a gate stack pattern is formed on the element-isolated n-type polyGe layer 21.

  Next, as shown in FIG. 5A, the Ni film 32 is formed on both the nMOS region 100 and the pMOS region 200.

  Next, as shown in FIG. 5B, heat treatment is performed at 250 ° C. to 350 ° C. to form the NiGe alloy layer 25 in the source / drain portions of the nMOS region 100 and the pMOS region 200, and an unreacted Ni film is formed. Remove with dilute hydrochloric acid. Subsequently, a protective insulating film 31 is formed on the pMOS region 200, and S (sulfur) ion implantation is performed on the NiGe alloy layer 25 in the nMOS region 100.

  Next, as shown in FIG. 5C, heat treatment is again performed at 250 ° C. to 350 ° C. to segregate S ion-implanted into the nMOS region 100 between the NiGe layer 25 and the channel Ge layer 21. Due to the segregation of S, the Schottky barrier between the NiGe layer 25 and the n-type Ge layer 21 in the nMOS region 100 can be controlled to reduce the parasitic resistance and increase the drive current. Thereafter, the protective insulating film 31 is removed by wet etching.

  Thereafter, as in the first embodiment, the structure shown in FIG. 4 is completed through the process of forming the electrode plug 27, the wiring 29, and the like.

  As described above, according to the present embodiment, by using the n-type Ge layer 21 made of the same material for the channel in the pMOSFET and the nMOSFET, the same effect as that of the first embodiment can be obtained. Since the source / drain is made of NiGe alloy also in the region 100, the resistance of the source / drain of the nMOSFET can be reduced. Furthermore, by segregating S between the NiGe layer 25 and the channel Ge layer 21 in the nMOS region 100, an effect of reducing the parasitic resistance of the nMOSFET and increasing the drive current can be obtained.

(Third embodiment)
FIG. 6 is a sectional view showing an element structure of a complementary semiconductor device according to the third embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

The present embodiment is different from the first embodiment in that, in the nMOS region 100, S ions are implanted into the connection region between the source / drain and the electrode plug, and the S segregation region 50 is formed. . In order to form the S segregation region 50, after forming the contact hole, S ions are implanted into the contact hole of the nMOS region 100, heat treatment is performed at 250 ° C. to 350 ° C., and the S concentration becomes 1 × 10 ¹⁶ cm ^−3. May be formed.

  With such a configuration, the contact resistance of the electrode plug 27 in the nMOSFET is reduced as compared with the first embodiment. Therefore, the device characteristics can be further improved as well as the same effects as those of the first embodiment. Further, as compared with the second embodiment, since ion implantation is performed using a contact hole, there is an advantage that the process is simple without requiring a thick insulating film such as the protective film 31.

  In the first to third embodiments described above, as the channel layer, not only pure Ge but also GeSn that is a mixed crystal of Ge and Sn (tin), and SiGeSn that is further mixed with Si are used. It can also be used. That is, any semiconductor layer having Ge as a main component may be used. In this case, it becomes possible to further reduce the process temperature, Sn inactivates crystal defects at the polygrain interface, or crystal defects in the grains, thereby facilitating adjustment of the carrier concentration, or improving mobility. There are effects such as.

The gate insulating film such as HfO _2, or Al ₂ O ₃ / HfO ₂ laminated film, another insulating film may also be used. The channel impurity is not limited to P, and any of As (arsenic), Sb (antimony), or a mixture thereof may be used. Moreover, the film thickness of each layer, the values such as the impurity concentration are examples, and can be changed according to the purpose. In the second and third embodiments, other chalcogen elements, that is, Se or Te, may be used instead of S ions. The heat treatment after chalcogen injection can be omitted if the subsequent interlayer insulating film deposition temperature is 250 ° C. or higher.

(Fourth embodiment)
FIG. 7 is a cross-sectional view showing an element structure of a complementary semiconductor device according to the fourth embodiment. The same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

The present embodiment is different from the second embodiment in that a rare earth oxide such as Y ₂ O ₃ or La ₂ O ₃ is used as the base insulating film 60.

  In the structure of the present embodiment, a dipole is generated between the base insulating film 60 and the n-type Ge layer 21 as the channel, and the threshold values of the pMOSFET and nMOSFET are moved in the proper direction (positive side). The threshold adjustment of the FET can be facilitated. Thereby, the following effects are obtained.

FIG. 8 is a diagram showing transfer characteristics (drain current (Id) -gate voltage (Vg) characteristics) of the pMOSFET and the nMOSFET, and the dotted line in the figure indicates a case where a normal insulating film such as SiO ₂ is used (no control). ), The broken line shows the case where the base insulating film of this embodiment is used. Also, the solid line in the figure is an example when controlled by an independent back gate as will be described later.

When SiO ₂ or the like is used as the base insulating film and the gate insulating film, the pMOSFET has a deep threshold on the negative side and the nMOSFET also has a negative threshold (normally on) as shown by the dotted line in FIG. As it is, it is very difficult to use as a CMOS circuit. Therefore, in the first to third embodiments, an Al ₂ O ₃ gate insulating film or the like that has an effect of moving the threshold value to the positive side is used.

On the other hand, when the base insulating film 60 made of a rare earth oxide is used as in this embodiment, the threshold voltage shifts to the positive side in both channels as shown by the broken line in FIG. Therefore, the burden of threshold adjustment by the gate insulating film or the gate electrode is reduced, and the range of options for the gate insulating film and the electrode is widened. Specifically, in this embodiment, a ZrO ₂ gate insulating film and a TaN gate electrode that have a relatively high dielectric constant and can form a good interface with Ge can be used.

  As described above, according to the present embodiment, the threshold voltage can be shifted to the positive side in both the pMOSFET and the nMOSFET by using the threshold adjustment layer made of the rare earth oxide as the base insulating film 60. Therefore, there is an advantage that the range of material choices for the gate insulating film 22 and the gate electrode 23 is widened as well as the same effects as those of the fourth embodiment.

  The CMOS structure on the base insulating film 60 is not necessarily limited to the structure of the second embodiment, and can be applied to the structures of other embodiments.

(Fifth embodiment)
FIG. 9 is a cross-sectional view showing an element structure of a complementary semiconductor device according to the fifth embodiment. The same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The present embodiment is different from the second embodiment in that a back gate electrode 70 for adjusting a threshold voltage is provided between the Si support substrate 11 and the base insulating film 12. As the back gate electrode 70, a diffusion layer in which the surface of the Si support substrate 11 is doped with impurities (preferably P, As, Sb) is doped, a poly-Si deposited film doped with impurities, or Al, Cu, W, A metal film such as TaN or TiN can be used. Here, an insulating film may be formed between the back gate electrode 70 and the support substrate 11 except when the diffusion layer on the surface of the Si support substrate 11 is used.

  With such a configuration, the threshold voltages of the nMOSFET and the pMOSFET can be shifted to the positive side and optimized as in the fourth embodiment. In addition, since the back gate voltage can be adjusted, the threshold voltage can be set more precisely than in the fourth embodiment.

(Sixth embodiment)
FIG. 10 is a cross-sectional view showing an element structure of a complementary semiconductor device according to the sixth embodiment. The same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

  This embodiment is different from the second embodiment in that back gate electrodes 71 and 72 for adjusting a threshold voltage are provided between the support substrate 11 and the base insulating film 12. . In other words, the first back gate electrode 71 that controls the pMOSFET and the second back gate electrode 72 that controls the nMOSFET are formed, which are different from the fifth embodiment in that they can be controlled independently. In the drawing, reference numeral 73 denotes an insulating film for separating the back gate electrodes 71 and 72.

  Further, as the back gate electrodes 71 and 72, a poly-Si deposited film or a metal film such as Al, Cu, W, TaN, or TiN can be used. Furthermore, it is also possible to use a diffusion layer in which the surface of the Si support substrate 11 is doped with impurities (preferably P, As, Sb) at a high concentration. In this case, the insulating film 73 can be omitted.

  With such a configuration, it is possible to independently control the back gate voltage as well as to obtain the same effect as in the fourth embodiment. Therefore, as shown by the solid line in FIG. 8, the threshold voltage can be set more precisely.

(Seventh embodiment)
FIG. 11 is a cross-sectional view showing the element structure of the stacked semiconductor device according to the seventh embodiment. In addition, the same code | symbol is attached | subjected to the same part as FIG. 4, and the detailed description is abbreviate | omitted.

  In this embodiment, the base is a Si-CMOS circuit (first semiconductor device) 300, and a complementary semiconductor device (Ge-CMOS circuit: second semiconductor device) 400 according to the second embodiment is stacked thereon. Has been. That is, the Ge-CMOS circuit 400 made of pMOSFET and nMOSFET is formed on the Si-CMOS circuit 300 via the interlayer film, and is integrated as a CMOS circuit.

  In the underlying Si-CMOS circuit 300, 301 is a Si substrate, 311 is an element isolation insulating film, 321 is a gate electrode, 331 is a first electrode plug, 332 is a second electrode plug, 333 is a third electrode plug, 334 Denotes a fourth electrode plug, 335 denotes a fifth electrode plug, 341 denotes a first wiring, 342 denotes a second wiring, and 351 denotes an interlayer insulating film.

  The wiring 29 of the Ge-CMOS circuit 400 is electrically connected to the Si-CMOS circuit 300 through electrode plugs 27 and electrode plugs 331 to 335 embedded in contact holes formed by lithography.

  In manufacturing the Ge-CMOS circuit 400, the P-doped amorphous Ge film 13 is grown on the interlayer insulating film 351 by CVD or sputtering, and then annealed to form the n-type polyGe layer 21. Thereafter, it can be produced in the same manner as in the second embodiment.

  As described above, according to the present embodiment, the n-type poly-Ge layer 21 is formed in an island shape on the interlayer insulating film 351, and the p-MOSFET and the n-MOSFET are formed in each of them. A semiconductor device having a three-dimensional structure in which the CMOS circuit 400 is stacked can be realized. In this case, since the semiconductor formed on the interlayer insulating film 351 is a Ge layer, the annealing temperature can be lowered. This is extremely effective in that the influence on the underlying Si-CMOS circuit 300 can be reduced. Further, TSV is not required unlike the case where the substrates are bonded together, and can be realized at a low cost.

  In the present embodiment, the configuration shown as the second embodiment is used as the upper Ge-CMOS circuit 400, but the configurations of the first and third embodiments can also be used. Further, as in the fourth embodiment, it is also possible to sandwich the threshold adjustment insulating film 60 between the base Si-CMOS circuit 300. Furthermore, the back gate electrodes 70, 71, 72 as shown in the fifth and sixth embodiments may be inserted between the underlying Si-CMOS circuit 300.

(Modification)
The present invention is not limited to the above-described embodiments.

  In the embodiment, the source / drain is formed of NiGe as a pMOS structure, but the present invention is not limited to this, and other metals such as alloys of Co, Pd, Pt and Ge can be used. Further, the source / drain is not necessarily an alloy, and may be a diffusion layer by p-type impurity doping.

  Further, although S is used as an element segregated between the alloy layer and the channel, chalcogen elements such as Se and Te can also be used. Further, a combination of chalcogen elements (S, Se, Te) may be doped.

  In addition, the channel layer containing Ge as a main component may be formed not only by a CVD method or a sputtering method but also by a method of bonding onto an insulating film. In particular, when bonding, a single crystal can be used, and higher performance can be achieved.

  In addition, the first semiconductor device in the case of manufacturing the stacked semiconductor device is not necessarily limited to the one using the Si substrate, but may be one using another semiconductor material.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 11 ... Si support substrate 12 ... Base insulating film 13 ... Amorphous Ge film 21 ... N-type poly Ge layer 22 ... Gate insulating film 23 ... Gate electrode 24 ... Gate side wall insulating film 25 ... Metal source / drain 26 ... Interlayer insulating film 27 ... Metal plug 28 ... Barrier metal 29 ... Wiring 31 ... Protective insulating film 32 ... Ni film 40 ... High concentration segregation region 50 ... S segregation region 60 ... Base insulating film (threshold adjustment layer)
70, 71, 72 ... Back gate electrode 73 ... Insulating film 100 ... nMOS region 200 ... pMOS region 300 ... Si-CMOS circuit (first semiconductor device)
400... Ge-CMOS circuit (second semiconductor device)

Claims (8)

N-type first and second semiconductor layers mainly formed of Ge and formed on a base insulating film;
An nMOSFET in which a gate electrode is formed on the first semiconductor layer through a gate insulating film, and the channel and the source / drain are semiconductor layers having the same polarity;
A pMOSFET in which a gate electrode is formed on the second semiconductor layer via a gate insulating film, and a source / drain region is formed of an alloy layer of the second semiconductor layer and a metal;
A complementary semiconductor device comprising:   A contact electrode is connected to a source / drain region sandwiching the gate electrode of the first semiconductor layer, and any of S, Se, and Te is in a region where the contact electrode and the first semiconductor layer are in contact with each other. The complementary semiconductor device according to claim 1, wherein one or a combination thereof is doped. N-type first and second semiconductor layers mainly formed of Ge and formed on a base insulating film;
A gate electrode is formed on the first semiconductor layer through a gate insulating film, and a source / drain region is formed of an alloy layer of the first semiconductor layer and a metal, and between the alloy layer and the channel. NMOSFET doped with any one of S, Se, Te, or a combination thereof;
A pMOSFET in which a gate electrode is formed on the second semiconductor layer via a gate insulating film, and a source / drain region is formed of an alloy layer of the second semiconductor layer and a metal;
A complementary semiconductor device comprising:   The complementary semiconductor device according to claim 1, wherein the base insulating film contains a rare earth oxide.   5. The complementary semiconductor device according to claim 1, wherein an electrode for applying a back bias common to the nMOSFET and the pMOSFET is formed below the base insulating film.   The first back bias application electrode formed below the underlying insulating film so as to include at least a region immediately below the channel portion of the nMOSFET, and at least the region immediately below the channel portion of the pMOSFET. A second back bias application electrode formed under the base insulating film is formed, and the first and second back bias application electrodes are independently controlled. The complementary semiconductor device according to claim 1. A first complementary semiconductor device having a CMOS circuit formed on a semiconductor substrate;
The second complementary semiconductor device according to claim 1, wherein the second complementary semiconductor device is stacked on the first semiconductor device.
Comprising
A stacked semiconductor device, wherein the first complementary semiconductor device and the second complementary semiconductor device are electrically connected by a contact electrode. Forming an n-type semiconductor layer mainly composed of Ge on the base insulating film;
Isolating the n-type semiconductor layer into a first semiconductor region for nMOSFET and a second semiconductor region for pMOSFET;
Forming a gate electrode on the first semiconductor region via a gate insulating film, and forming an nMOSFET having a channel and a source / drain semiconductor layer of the same polarity;
Forming a gate electrode on the second semiconductor region via a gate insulating film and forming a pMOSFET in which source / drain regions are alloy layers of the second semiconductor region and metal;
A method of manufacturing a complementary semiconductor device, comprising:

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