JP2007287913A - Field effect transistor, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hetero junction MIS field effect transistor capable of obtaining excellent body contact and of preferably controlling the potential of a hetero junction layer. <P>SOLUTION: The field effect transistor comprises a substrate 1 with at least its upper portion constructed with semiconductor chiefly constituting Si; a first semiconductor layer 3 formed just above the substrate 1 and being a buffer layer chiefly consisting of Si; second semiconductor layers 4, 5 at least including a hetero junction layer 4 formed to make hetero junction with respect to the upper surface of the first semiconductor layer 3; a gate insulating film 9 formed on the second semiconductor layers 4, 5; a gate electrode 10 formed on the gate insulating film 9; a source region 7 and a drain region 8 located in at least the second semiconductor layers 4, 5 and formed to sandwich the gate electrode 10 as viewed in a plane; a contact hole 31 formed to penetrate at least the second semiconductor layer to reach the first semiconductor layer or the substrate; and a conductor contact 12 formed to make contact with at least any of the first semiconductor layer and the substrate exposed to a bottom surface of the contact hole. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof, and more particularly to a heterojunction MIS field effect transistor including a material heterojunction with silicon in a channel and a manufacturing method thereof.

  As a transistor in which a Si alloy material is introduced into a channel in order to realize high performance of a conventional MIS type field effect transistor (Metal Insulator Semiconductor Field Effect Transistor), there is a heterojunction MIS type field effect transistor. For example, when a Si alloy material made of strained SiGe is used for a channel, hole mobility increases, and improvement in electrical characteristics can be expected.

  FIG. 9 is a plan view showing a structure in plan view of an example of such a heterojunction MIS field effect transistor (hereinafter referred to as a first conventional example), and FIG. 10 is a heterojunction MIS field effect type of FIG. 9A and 9B are cross-sectional views of a transistor, in which FIG. 9A is a cross-sectional view showing a cross-section along the XA-XA line in FIG. 9 (a cross-section along the gate length direction), and FIG. It is sectional drawing which shows the cross section (cross section along a gate width direction) along a line.

  As shown in FIGS. 9 and 10, in the first conventional example, the Si buffer layer 3, the strained SiGe layer 4, and the Si cap layer 5 are formed in this order on the bulk Si semiconductor substrate 1 by using epitaxial growth. ing. The film thicknesses of the Si cap layer 5 and the strained SiGe layer 4 are, for example, 2 nm and 10 nm, respectively. If the Si cap layer 5 is formed thin, a large amount of current flows through the SiGe layer having high mobility. An element isolation region 2 is formed in the Si semiconductor substrate 1 on which each of these layers 3, 4, and 5 is formed. In a region surrounded by the element isolation region, impurities are doped using an ion implantation method. , An n-type body region 6, a p-type source region 7, and a p-type drain region 8 are formed. A gate electrode 10 is formed on the Si cap layer 5 with a gate insulating film 9 interposed therebetween. The gate electrode 10 is composed of a doped polysilicon layer 10a and a silicide layer 10b. A gate sidewall insulating film 15 is formed on the side surface of the gate electrode 10. A source electrode 13 and a drain electrode 14 made of silicide are formed on the source region 7 and the drain region 8, respectively. A contact hole 31 is formed so as to penetrate the gate insulating film 9, and a body electrode 12 made of silicide is formed at the bottom of the contact hole 31 so as to be in contact with the strained SiGe layer 4.

  In the first conventional example configured as described above, a channel is formed in the strained SiGe layer 4 and the Si cap layer 5, and carriers composed of holes move through the channel at a high speed, so that a high speed operation is possible. Further, since a threshold value of the gate voltage (hereinafter referred to as a threshold voltage) is changed by applying a voltage to the body electrode 12, the threshold voltage is lowered during operation and the threshold voltage during non-operation. By changing so as to increase the operating voltage, the operating voltage can be reduced and the leakage current can be reduced.

  FIG. 11 is a diagram showing a cross-sectional structure of another example of a conventional heterojunction MIS field effect transistor (hereinafter referred to as a second conventional example). FIG. 11A shows a cross-section along the gate length direction. FIG. 4B is a cross-sectional view showing a cross section along the gate width direction.

  As shown in FIG. 11, in the second conventional example, on the SOI substrate in which the buried oxide film 16 and the upper Si layer 17 are formed in this order on the Si semiconductor substrate 1, as in the first conventional example. A transistor is formed. This second conventional example has a smaller substrate capacity and can operate at a higher speed than the first conventional example in which transistors are formed on a bulk Si semiconductor substrate 1. On the other hand, as a drawback, carriers due to impact ionization or a tunnel current of the gate insulating film accumulate in the body region 6 and a substrate floating effect may occur.

  As a third conventional example, a dynamic threshold type transistor is known in which the gate and body of a heterojunction MIS field effect transistor are connected to operate in conjunction with the body bias and the gate bias (for example, Patent Documents). 1). The third conventional example includes a body contact for electrically connecting the gate electrode and the body region. This body contact is formed in contact with the Si channel region 25 (Si cap layer).

As a fourth conventional example, a heterojunction MIS field effect transistor is known in which a body electrode is formed so as to be electrically connected to a body region (see, for example, Patent Document 2).
Japanese Patent No. 3530521 (see particularly FIG. 1 (c)) WO 03/063254 A1 (especially see FIG. 1)

  However, in any of the first to third conventional examples described above, a good body contact cannot be obtained, and there is a problem of increasing the resistance. Further, in the fourth conventional example, it is not described where the body electrode is specifically formed, and this problem is not solved.

  Specifically, in the first and second conventional techniques, the body electrode 12 for obtaining the body contact is formed on the thin Si cap layer 5 on the strained SiGe layer 4 to constitute the body electrode 12. When heat treatment is performed to form a silicide film, Ge in the strained SiGe layer 4 is segregated to form grains, and it is difficult to obtain a good silicide film or ohmic contact. For example, when forming the aforementioned silicide film, for example, a Ni film or a Co film is formed on the Si cap layer 5 and then heat treatment is performed to form a nickel silicide film or a cobalt silicide film. Due to the difference in bond energy between metal and Si or Ge, problems such as segregation of Ge and loss of flatness of the silicide film occur. As a result, the resistance of the silicide film increases and the shape is poor. It becomes.

  Such a problem is a problem that may occur in common when a heterojunction composed of elements such as Si, Ge, and C is formed on the surface of the substrate, and Si, Ge, A grain is formed due to a difference in binding energy between each element such as C and a metal to be reacted such as Ni or Co. In other words, this is a common problem that occurs in field effect transistors in which a SiGe layer, a SiGeC layer, a SiC layer, a Ge layer, and the like (hereinafter sometimes collectively referred to as a heterojunction layer) are formed on the substrate surface.

  In such a case, the contact becomes insufficient, and the control of the substrate potential (exactly, the potential of the heterojunction layer) is deteriorated. In addition, when a transistor is formed on an SOI substrate as in the second conventional example, carriers accumulated in the body cannot be drawn out from the body electrode 12 and a substrate floating effect occurs.

  In the third conventional example, for the same reason as in the first and second conventional examples, the body contact has a high resistance or a defective shape. As a result, the body contact becomes insufficient, and a desired bias cannot be applied to the body, resulting in malfunction.

  The present invention has been made to solve the above-described conventional problems, and provides a heterojunction MIS field effect transistor capable of obtaining a favorable body contact and capable of suitably controlling the potential of the heterojunction layer, and the same. An object is to provide a manufacturing method.

  In order to solve the above-described problems, a method for manufacturing a field effect transistor according to the present invention includes a first buffer layer mainly made of Si and at least an upper part thereof directly above a substrate made of a semiconductor made mainly of Si. Forming a second semiconductor layer, forming a second semiconductor layer so as to have at least a heterojunction layer heterojunction with the upper surface of the first semiconductor layer, and forming the second semiconductor layer on the second semiconductor layer; A step C of forming a gate insulating film; a step D of forming a gate electrode on the gate insulating film; and a source region and a source region positioned at least in the second semiconductor layer and sandwiching the gate electrode in plan view Forming a drain region; forming a contact hole that penetrates at least the second semiconductor layer and reaches the first semiconductor layer or the substrate; and And a step G of forming a contact made of a conductive material so as to be in contact with at least one of said first semiconductor layer and the substrate exposed to the bottom surface of Kutohoru, the.

  With such a configuration, by forming a contact hole so as to penetrate the second semiconductor layer, Ge or the like contained in the heterojunction layer in the second semiconductor layer is surely removed, and then, Since the contact is formed at the bottom of the contact hole, it is possible to prevent the contact from increasing in resistance and deformation due to the formation of grains such as Ge. As a result, a good body contact can be obtained and the potential of the heterojunction layer can be suitably controlled.

  In the step F, the contact hole is formed so as to penetrate the second semiconductor layer and the first semiconductor layer and reach the substrate, and in the step G, the contact is formed so as to contact the substrate. May be.

  In the step F, the contact hole may be formed to reach the first semiconductor layer, and in the step G, the contact may be formed to be in contact with at least the first semiconductor layer.

  With such a configuration, since the contact is formed so as to contact the first semiconductor layer which is the buffer layer, the heterojunction is avoided by avoiding the interface between the contaminated substrate and the first semiconductor layer. Since a bias voltage can be applied to the layer, the potential of the heterojunction layer can be accurately controlled.

  The field effect transistor according to the present invention includes a first semiconductor layer that is a substrate made of a semiconductor mainly made of Si at least in the upper part and a buffer layer made mainly of Si formed immediately above the substrate. A second semiconductor layer having at least a heterojunction layer formed so as to be heterojunction with the upper surface of the first semiconductor layer, a gate insulating film formed on the second semiconductor layer, and the gate A gate electrode formed on an insulating film; a source region and a drain region which are located at least in the second semiconductor layer and sandwich the gate electrode in plan view; and at least the second semiconductor layer A contact hole formed so as to pass through the first semiconductor layer or the substrate, the first semiconductor layer exposed on the bottom surface of the contact hole, and Serial comprising a contact made of formed conductors such that at least contact with one of the substrate, the.

With such a configuration, Ge or the like contained in the heterojunction layer in the second semiconductor layer is surely removed when the contact hole is formed so as to penetrate the second semiconductor layer, and then the Since the contact is formed at the bottom of the contact hole, it is possible to prevent the contact from increasing in resistance and deformation due to the formation of grains such as Ge. As a result, a good body contact can be obtained and the potential of the heterojunction layer can be suitably controlled.
Can do.

  The contact may be formed in contact with the substrate.

  The contact may be formed to be in contact with at least the first semiconductor layer.

  With such a configuration, since the contact is formed so as to contact the first semiconductor layer which is the buffer layer, the heterojunction is avoided by avoiding the interface between the contaminated substrate and the first semiconductor layer. Since a bias voltage can be applied to the layer, the potential of the heterojunction layer can be accurately controlled.

  The heterojunction layer of the second semiconductor layer may be made of SiGe, SiGeC, SiC, or Ge.

  The second semiconductor layer may be composed of the heterojunction layer and a Si layer formed on the heterojunction layer.

  The substrate may be an SOI substrate, and the semiconductor constituting the upper portion of the substrate may be a Si upper layer formed on an insulating film of the SOI substrate.

  The substrate may be a bulk Si substrate.

  The contact may be a body contact that electrically connects the gate electrode to the first semiconductor layer.

  The present invention is configured as described above, and in the heterojunction MIS field effect transistor and the manufacturing method thereof, it is possible to obtain good body contact and to suitably control the potential of the heterojunction layer. There is an effect.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a plan view showing a structure of the field effect transistor according to the first embodiment of the present invention in plan view. 2 is a view showing a cross-sectional structure of the field effect transistor of FIG. 1, wherein (a) is a cross-sectional view showing a cross section taken along the line IIA-IIA of FIG. 1 (cross section along the gate length direction); FIG. 2B is a cross-sectional view showing a cross section taken along the line IIB-IIB in FIG. 1 (a cross section along the gate width direction).

  The field effect transistor according to the present embodiment is a heterojunction MIS field effect transistor.

  As shown in FIGS. 1 and 2, the field effect transistor includes a Si semiconductor substrate 1 made of bulk Si. Here, in order to simplify the description in this specification, in FIG. 2, reference numeral 1 indicating the Si semiconductor substrate is an unprocessed region (below the body region 6) of the Si semiconductor substrate. The area located at). However, the Si semiconductor substrate 1 is constituted by a region of the field effect transistor located below the Si buffer layer 3 described below.

  An Si buffer layer 3 made of Si, a strained SiGe layer 4 made of SiGe, and an Si cap layer 5 made of Si are formed in this order on the Si semiconductor substrate 1 by epitaxial growth. Therefore, the strained SiGe layer 4 is heterojunction with both the Si buffer layer 3 and the Si cap layer 5. The thickness of the Si buffer layer 3 is 5 nm, for example. The thickness of the strained SiGe layer 4 is, for example, about 8 nm. Here, the thickness of the Si cap layer 5 is 2 nm. The thickness of the Si cap layer 5 is preferably about 0.1 nm to 4 nm, and more preferably about 2 nm. With such a thickness, a large amount of carriers can be accumulated in the strained SiGe layer 4 with high hole mobility while suppressing surface scattering, and the electrical characteristics can be improved.

  An element isolation region 2 is formed in the Si semiconductor substrate 1 on which these layers (hereinafter referred to as epitaxial growth layers) 3, 4 and 5 are formed. A p-type source region 7 and a p-type drain region 8 to which conductivity is imparted by doping a region surrounded by the element isolation region 2 (hereinafter sometimes referred to as an active region) with a p-type impurity, The n-type body region 6 doped with n-type impurities and imparted with conductivity is formed. A source electrode 13 and a drain electrode 14 made of a silicide layer are formed on the source region 7 and the drain region 8, respectively. As shown in FIG. 1, the source region 7 and the drain region 8 are formed so as to be located on both sides of the gate electrode 10 (more precisely, on both sides in the gate length direction) in plan view. A source extension 41 is formed so as to extend from the source region 7 to a region below the gate sidewall insulating film 15, and a drain extension 42 is formed so as to extend from the drain region 8 to a region below the gate sidewall insulating film 15. In the case of simplification, the source extension 41 and the drain extension 42 may be omitted. As shown in FIG. 2, the source region 7 and the drain region 8 extend from directly below the source electrode 13 and the drain electrode 14 to the top of the Si semiconductor substrate 1 in the thickness direction of the Si semiconductor substrate 1. Is formed.

  The body region 6 is formed so as to occupy the portion excluding the source region 7 and the drain region 8 in the upper part of the Si semiconductor substrate 1 located in the active region.

  A gate insulating film 9 is formed on the Si cap layer 5 in a portion of the epitaxial growth layers 3 to 5 in the active region excluding the source region 7 and the drain region 8 (hereinafter referred to as channel region). A gate electrode 10 is formed on 9. The channel region is usually doped to a low concentration n-type with an n-type impurity diffused from the body region 6. The gate electrode 10 is composed of a doped polysilicon layer 10a and a silicide layer 10b made of polysilicon doped with a p-type impurity. As shown in FIGS. 1 and 2, a gate sidewall insulating film 15 is formed on the side surface of the gate electrode 10. A source electrode 13 and a drain electrode 14 made of silicide are formed on the source region 7 and the drain region 8, respectively.

  A contact hole 31 is formed so as to penetrate the Si buffer layer 3, the strained SiGe layer 4, the Si cap layer 5, and the gate insulating film 9. A body electrode 12 made of silicide is formed at the bottom of the contact hole 31. It is formed so as to be in contact with body layer 6. Since the body electrode 12 is formed by siliciding the surface layer portion of the body layer 6, the thickness is a design requirement.

  Next, a method for manufacturing the field effect transistor configured as described above will be described. However, since processes other than the process of forming the body electrode 12 are known, the process of forming the body electrode 12 will be mainly described, and the other processes will be described in a simplified manner.

  3 (a) to 3 (k) are cross-sectional views showing the manufacturing process of the field effect transistor of FIG. 1, and FIGS. 3 (a), (b), (d), (f) to (f) i) and (k) are sectional views showing a section along the gate length direction, and FIGS. 3C, 3E and 3J are sectional views showing a section along the gate width direction.

  First, in the step of FIG. 3A, an element isolation region 2 is formed in the Si semiconductor substrate 1, thereby forming an active region surrounded by the element isolation region 2.

  Next, in the step of FIG. 3B, n-type impurities such as As or P are ion-implanted into the Si semiconductor substrate 1 to form an n-well 6 'in the active region. At this time, p-type impurities made of B are also ion-implanted as appropriate in order to control the threshold voltage Vt. Thereafter, the Si semiconductor substrate 1 is annealed to activate the n-well 6 '.

Next, in the step of FIG. 3C, a mask layer 50 for selective growth is formed on the surface of the Si semiconductor substrate 1. The mask layer 50 is composed of a deposited layer made of SiO ₂ , a thermal oxide layer, or the like. The mask 50 has an opening in the active region and is formed so as to cover a region (referred to as a contact hole forming region) in which a body electrode contact hole is to be formed.

  Next, in the steps of FIGS. 3D and 3E, the Si buffer substrate 3, the strained SiGe layer 4, and the Si cap layer are formed on the Si semiconductor substrate 1 on which the mask is formed in this manner by the CVD method. 5 are sequentially epitaxially grown, and then the mask layer 50 is removed. Thereby, the Si buffer layer 3, the strained SiGe layer 4, and the Si cap layer 5 (epitaxial growth layers 3 to 5) are formed on the active region. On the other hand, the epitaxial growth layers 3 to 5 are not formed on the insulating layer in the contact hole forming region, but the contact hole 31 ′ is formed.

  Next, in the step of FIG. 3F, a gate insulating film 9a 'and a polysilicon film 10a' are sequentially deposited on the entire surface of the Si semiconductor substrate 1 by the CVD method.

Next, in the step of FIG. 3G, a TEOS layer (SiO ₂ layer made of TEOS) 51 is formed on the entire surface of the Si semiconductor substrate 1 by CVD, and this is patterned into a predetermined shape by lithography. As a result, the TEOS layer 51 is left on the region where the gate electrode is to be formed. Then, dry etching is performed using the TEOS layer 51 as a mask to remove the gate insulating film 9 ′ and the polysilicon film 10a ′ other than the portion where the TEOS layer 51 is left. Thereby, the gate insulating film 9 and the polysilicon layer 10a of the gate electrode 10 are formed.

  Next, in the step of FIG. 3H, a region where the source / drain region is not formed is masked with a resist, and p-type impurities made of B are ion-implanted into the Si semiconductor substrate 1. Although not shown, in order to suppress the short channel effect, an n-type impurity composed of As is pocket-implanted in an oblique direction aiming at a region under the gate. As a result, source extension regions 41 ′ and drain extension regions 42 ′ are formed over a predetermined depth on both sides of the polysilicon layer 10 a of the gate electrode 10 in the plan view of the epitaxial growth layers 3 to 5.

  Next, in the step of FIG. 3I, an insulating film is deposited on the surface of the Si semiconductor substrate 1 by the CVD method, and isotropically etched to thereby form the polysilicon layer 10a and the TEOS layer 51 of the gate electrode 10. A gate side wall insulating film 15 is formed on the side surface of the gate electrode. At this time, the gate sidewall insulating film 15 is also formed on the sidewall of the contact hole 31 '. Thereafter, a region where the source / drain region is not formed is masked with a resist, and p-type impurities made of B are ion-implanted into the Si semiconductor substrate 1. Thereafter, the Si semiconductor substrate 1 is annealed to activate the region implanted with ions. Thereby, the source region 7 and the drain region 8 are formed over a predetermined depth on both sides of the gate sidewall insulating film 15 in a plan view of the epitaxial growth layers 3 to 5. A source extension 41 and a drain extension 42 are formed immediately below the gate sidewall insulating film 15. In the n-well 6 ′, a region where the source region 7 and the drain region 8 are not formed becomes the body region 6. Of the epitaxial growth layers 3, 4, and 5, a region masked by the polysilicon layer 10 a of the gate electrode 10 becomes a channel region. In this channel region, n-type impurities are diffused from the body region 6 by annealing, and are doped to a low concentration n-type. Further, the polysilicon 10a of the gate electrode is doped p-type by the implanted p-type impurity.

  Next, in the steps of FIGS. 3J and 3K, the TEOS layer 51 on the gate electrode is removed by predetermined etching.

  Next, for example, nickel is deposited to a thickness of 15 nm on the surface of the Si semiconductor substrate 1 by a sputtering method, and then the Si semiconductor substrate 1 is heat-treated at 550 ° C. for 15 minutes. As a result, nickel and silicon are alloyed in the surface layer portions of the source region 7, the drain region 8, the doped polysilicon layer 10 a of the gate electrode, and the body region 6 exposed to the contact hole 31, thereby forming a nickel silicide film. It is formed. The silicide films form the source electrode 13, the drain electrode 14, the silicide layer 10b of the gate electrode 10, and the body electrode 12 (see FIG. 2B), respectively. Thereby, the gate electrode 10 is composed of the doped polysilicon layer 10a and the silicide layer 10b. In this silicidation process, a cobalt silicide film may be formed using, for example, cobalt other than nickel.

  Next, the operation of the field effect transistor constructed and manufactured as described above will be briefly described.

  In the field effect transistor of the present embodiment, a drain current flows (operates) when a voltage equal to or higher than the threshold voltage is applied between the gate electrode 10 and the body electrode 12. During this operation, a channel is formed in the strained SiGe layer 4 and the Si cap layer 5, and carriers consisting of holes move through the channel at a high speed. Therefore, high speed operation is possible. Further, by changing the voltage applied to the body electrode 12 so that the threshold voltage is lowered during operation and the threshold voltage is increased during non-operation, the operating voltage can be reduced and the leakage current can be reduced. Further, in the present embodiment, when the epitaxial growth layers 3 to 5 are formed, the contact hole 31 reaching the body region 6 is formed so as not to form the epitaxial growth layers 3 to 5 in the region where the body electrode 12 is to be formed. Then, the body electrode 12 is formed at the bottom of the contact hole 31. Therefore, when forming the body electrode 12, the formation of grains due to the segregation of Ge can be prevented, and a good silicide electrode with low resistance can be formed. Further, the flatness of the silicide film is good, and it is difficult to cause a shape defect. Therefore, the body potential control can be improved. Further, since the gate side wall insulating film is also formed on the side wall of the contact hole 31, there is no reaction with Ge of the SiGe layer on the side wall when the silicide electrode is formed, and the shape defect is unlikely to occur.

Next, a modification of the present embodiment will be described.
[Modification 1]
In this modification, the method for forming the contact hole 31 is modified in the method for manufacturing the field effect transistor of FIG.

Specifically, in the step of FIG. 3C, the epitaxial growth layers 3 to 5 are formed over the entire surface of the active region, and thereafter, the epitaxial growth layers 3 to 5 are removed by etching at an appropriate timing. A contact hole 31 reaching the surface of the region 6 is formed. For example, in the step of FIG. 3D, after epitaxial growth, a resist film having an opening in a portion where the body electrode 12 is to be formed is formed on the entire surface of the Si semiconductor substrate 1, and etching is performed using the resist film as a mask. A contact hole 31 is formed in the opening. That is, by this etching, the layers 9, 5, 4, 3 from the gate insulating film 9 to the Si buffer layer 3 are removed. When this is performed by wet etching, for example, an etching solution of HNO ₃ : H ₂ O: HF = 40: 20: 5 is used. According to this wet etching, since the etching rate of the strained SiGe layer 4 is about 10 times faster than that of the body region 6 (Si layer), it can be selectively removed. In addition, when this is performed by dry etching, the etching can be appropriately performed by controlling the etching amount according to time according to the total thickness of the layers to be removed.

  Further, the contact hole 31 may be formed by this etching after the formation of the gate electrode in the step of FIG. 3G or before the formation of the gate sidewall insulating film 15 in the step of FIG.

Also in such a modification, since the strained SiGe layer 4 containing Ge is removed by the above-described etching, the formation of grains due to the segregation of Ge can be prevented when the body electrode 12 is formed, A good silicide electrode with low resistance can be formed. Further, the flatness of the silicide film is good, and it is difficult to cause a shape defect. Further, by forming the gate sidewall insulating film after forming the contact hole, the cross section of the hetero contact layer is covered with the insulating film, and Ge is not mixed in the silicide process, so that it is difficult to cause a shape defect.
Therefore, the control of the body potential can be improved.
(Embodiment 2)
4A and 4B are views showing a cross-sectional structure of a field effect transistor according to Embodiment 2 of the present invention, in which FIG. 4A is a cross-sectional view showing a cross section along the gate length direction, and FIG. It is sectional drawing which shows the cross section along.

  In the field effect transistor of the present embodiment, the contact hole 31 is formed so as to reach the surface of the Si buffer layer 3. The surface layer portion of the Si buffer layer 3 is silicided to form a body electrode 12 made of the silicide film. Since the body electrode 12 is formed by silicidation, if the thickness of the Si buffer layer 3 is thin, it may reach not only the Si buffer layer 3 but also the body region, but that may be sufficient. The other points are the same as in the first embodiment.

  The manufacturing method of the field effect transistor according to the present embodiment is the same as that of the first modification of the first embodiment except that the contact hole 31 and the body electrode 12 are formed as described above. In the wet etching for forming the contact hole 31, the etching rate of the strained SiGe layer 4 is about 10 times faster than the etching rate of the Si buffer layer 3, so that it can be selectively removed. Also, the strained SiGe bath can be selectively removed accurately by controlling the etching time.

  By the way, in general, in the case of manufacturing a field effect transistor, since the Si buffer layer 3 or more layers are epitaxially grown on the upper surface of the Si semiconductor substrate 1 (the upper surface of the body region 6), the upper surface of the Si semiconductor substrate 1 The interface with the Si buffer layer 3 is contaminated. Therefore, when the body electrode 12 is formed directly on the body region 6, a bias voltage is applied to the strained SiGe layer 4 via the interface between the upper surface of the body region 6 and the Si buffer layer 3. The potential of the bonding layer) 4 cannot be accurately controlled. However, according to the present embodiment, a bias voltage can be applied to the strained SiGe layer 4 while avoiding the interface between the contaminated body region 6 and the Si buffer layer 3. For this reason, the potential of the strained SiGe layer 4 can be accurately controlled.

Next, a modification of the present embodiment will be described.
[Modification 2]
5A and 5B are diagrams showing a cross-sectional structure of a field effect transistor according to Modification 2 of the present embodiment, where FIG. 5A is a cross-sectional view showing a cross section along the gate length direction, and FIG. 5B is a gate width. It is sectional drawing which shows the cross section along a direction.

As shown in FIG. 5, the field effect transistor of this modification is obtained by omitting the Si cap layer 5 from the field effect transistor of FIG. Thus, by eliminating the Si cap layer, more carriers can be accumulated in the strained SiGe layer 4 and the current driving capability can be improved.
[Modification 3]
6A and 6B are diagrams showing a cross-sectional structure of a field effect transistor according to Modification 3 of the present embodiment, where FIG. 6A is a cross-sectional view showing a cross section along the gate length direction, and FIG. 6B is a gate width. It is sectional drawing which shows the cross section along a direction.

  As shown in FIG. 6, in the field effect transistor of this modification, in the field effect transistor of FIG. 4, two layers of the strained SiGe layer 4 are formed so as to sandwich the Si layer 19 therebetween. Here, the thickness of the Si layer 19 is 3 nm.

As described above, by forming the strained SiGe layer 4 into two layers, a double channel can be realized and the drain current can be increased.
(Embodiment 3)
7A and 7B are diagrams showing a cross-sectional structure of a field effect transistor according to Embodiment 3 of the present invention, where FIG. 7A is a cross-sectional view showing a cross section along the gate length direction, and FIG. 7B is a gate width direction. It is sectional drawing which shows the cross section along line. 7, the same reference numerals as those in FIG. 4 denote the same or corresponding parts.

  As shown in FIG. 7, in this embodiment, a Si semiconductor substrate 1 made of an SOI substrate is used instead of the Si semiconductor substrate 1 made of bulk Si in FIG. Other points are the same as in the second embodiment. In FIG. 7, reference numeral 1 indicating an SOI substrate (Si semiconductor substrate) indicates a region left unprocessed in the SOI substrate. However, the SOI substrate 1 is composed of a region located below the Si buffer layer 3 in the field effect transistor.

  Specifically, the Si semiconductor substrate 1 made of an SOI substrate is configured by forming a buried oxide film 16 and an upper Si layer 17 on a region left unprocessed.

  The Si buffer layer 3, the strained SiGe layer 4, and the Si cap layer 5 are formed on the upper Si layer 17 by epitaxial growth. The upper Si layer 17 of the Si semiconductor substrate 1 is doped with n-type impurities by being implanted with n-type impurities. That is, in the present embodiment, the upper Si layer 17 plays the same role as the n-well in the field effect transistor of the second embodiment. The element isolation region 2 is formed to a depth reaching the surface of the buried oxide film 16 of the Si semiconductor substrate 1. Other points are the same as in the second embodiment.

According to the field effect transistor of the present embodiment configured as described above, carriers accumulated in the body can be quickly drawn out to the body electrode 12, so that the substrate floating effect is suppressed and the element operates stably. It becomes possible to make it.
(Embodiment 4)
8A and 8B are diagrams showing a cross-sectional structure of a field effect transistor according to Embodiment 4 of the present invention, where FIG. 8A is a cross-sectional view showing a cross section along the gate length direction, and FIG. 8B is a gate width direction. It is sectional drawing which shows the cross section along line. 8, the same reference numerals as those in FIG. 7 denote the same or corresponding parts.

  The field effect transistor of this embodiment is a dynamic threshold type field effect transistor.

  The field effect transistor of the present embodiment is formed so that the contact hole 31 reaches the surface layer portion of the Si buffer layer 3 from the lower surface of the end portion of the gate electrode 10 in the field effect transistor of the third embodiment. Body contact 18 is formed to fill contact hole 31. Thereby, the gate electrode 10 and the Si buffer layer 3 are electrically connected by the body contact 18. The body contact 18 is made of a conductive material such as Al. The other points are the same as in the third embodiment.

  According to the field effect transistor of this embodiment configured as described above, the Ge (strained SiGe layer 4) in the region where the body contact 18 is formed is removed, so that grains are not generated without segregation of Ge. Therefore, a good body contact 18 can be formed with low resistance. Therefore, the control of the body potential can be improved. Therefore, it is possible to stably apply the body bias during the dynamic threshold operation. In addition, since carriers accumulated in the body can be quickly drawn out to the electrode (gate electrode), the effect of floating the substrate can be suppressed and the element can be operated stably.

  In the above description, the body contact 18 is made of a conductor filling the contact hole 31, but it may be made of a silicide film formed on the Si buffer layer 3 and a wiring material filling the contact hole 31.

  In the third and fourth embodiments, as in the first embodiment, the contact hole 31 is formed so as to reach the surface of the body region 6, and the body electrode 12 or body made of a silicide film is formed on the surface layer portion of the body region 6. A contact 18 may be formed.

  In the second to fourth embodiments, the impurity concentration of the Si buffer layer 3 on which the body electrode 12 or the body contact 18 is formed can be selected as appropriate.

  In the first to fourth embodiments, as the material of the gate electrode 10, TiN, W, Al, TaN, nickel silicide, or the like can be used in addition to the doped silicon described above.

  In the first to fourth embodiments, the heterojunction layer is formed of a SiGe layer. However, the heterojunction layer is heterojunction with the Si layer by combining elements such as Si, Ge, and C such as a SiGeC layer, a SiC layer, and a Ge layer. It may consist of layers. Even if comprised in this way, the effect similar to Embodiment 1 thru | or 4 is acquired.

  The field effect transistor of the present invention is useful as a heterojunction MIS field effect transistor or the like that can obtain a good body contact and can accurately control the potential of the heterojunction layer. It is useful as a rule integrated circuit transistor or a CMOS circuit transistor.

  The method for producing a field effect transistor of the present invention is useful as a method for producing a heterojunction MIS field effect transistor or the like that can obtain a good body contact and can accurately control the potential of the heterojunction layer. In particular, it is useful as a method for manufacturing an integrated circuit transistor or a CMOS circuit transistor having a fine design rule.

It is a top view which shows the structure in planar view of the field effect transistor which concerns on Embodiment 1 of this invention. 2A and 2B are diagrams showing a cross-sectional structure of the field effect transistor of FIG. 1, where FIG. 1A is a cross-sectional view showing a cross section taken along line IIA-IIA in FIG. 1, and FIG. FIG. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate width direction. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate width direction. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate width direction. FIG. 2 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1 and showing a cross section along the gate length direction. It is a figure which shows the cross-section of the field effect transistor which concerns on Embodiment 2 of this invention, Comprising: (a) is sectional drawing which shows the cross section along a gate length direction, (b) is the cross section along a gate width direction FIG. It is a figure which shows the cross-section of the field effect transistor which concerns on the modification 2 of Embodiment 2 of this invention, Comprising: (a) is sectional drawing which shows the cross section along a gate length direction, (b) is a gate width direction It is sectional drawing which shows the cross section along line. It is a figure which shows the cross-section of the field effect transistor which concerns on the modification 3 of Embodiment 2 of this invention, Comprising: (a) is sectional drawing which shows the cross section along a gate length direction, (b) is a gate width direction It is sectional drawing which shows the cross section along line. It is a figure which shows the cross-section of the field effect transistor which concerns on Embodiment 3 of this invention, Comprising: (a) is sectional drawing which shows the cross section along a gate length direction, (b) is the cross section along a gate width direction. FIG. It is a figure which shows the cross-section of the field effect transistor which concerns on Embodiment 4 of this invention, Comprising: (a) is sectional drawing which shows the cross section along a gate length direction, (b) is the cross section along a gate width direction FIG. It is a top view which shows the structure in the planar view of the heterojunction MIS type field effect transistor of the 1st prior art example. FIG. 10 is a diagram showing a cross-sectional structure of the heterojunction MIS field effect transistor of FIG. 9, wherein (a) is a cross-sectional view showing a cross-section along the XA-XA line of FIG. FIG. 10B is a cross-sectional view showing a cross section along the XB-X line in FIG. 9 (cross section along the gate width direction). It is a figure which shows the cross-section of the heterojunction MIS field effect transistor of the 2nd prior art example, Comprising: (a) is sectional drawing which shows the cross section along a gate length direction, (b) is along the gate width direction It is sectional drawing which shows a cross section.

Explanation of symbols

1 Si semiconductor substrate
2 Device isolation region
3 Si buffer layer
4 strained SiGe layer 5 Si cap layer
6 Body region 7 Source region 8 Drain region 9 Gate insulating film
10 Gate electrode 10a Doped polysilicon layer 10b Silicide layer
12 Body electrode
13 Source electrode
14 Drain electrode
15 Gate sidewall insulating film 16 Buried oxide film
17 Upper Si layer
18 Body contact
19 Si layer
31 Contact hole 41 Source extension 42 Drain extension 50 Mask layer 51 TEOS layer

Claims (11)

Forming a first semiconductor layer, which is a buffer layer mainly made of Si, at least directly above a substrate made of a semiconductor made mainly of Si;
Forming a second semiconductor layer so as to have at least a heterojunction layer heterojunction with the upper surface of the first semiconductor layer; and
Forming a gate insulating film on the second semiconductor layer; and
Forming a gate electrode on the gate insulating film; and
Forming a source region and a drain region at least in the second semiconductor layer and sandwiching the gate electrode in plan view; and
Forming a contact hole that penetrates at least the second semiconductor layer and reaches the first semiconductor layer or the substrate; and
Forming a contact made of a conductor so as to be in contact with at least one of the first semiconductor layer exposed on the bottom surface of the contact hole and the substrate. In the step F, the contact hole is formed to penetrate the second semiconductor layer and the first semiconductor layer to reach the substrate,
The method of manufacturing a field effect transistor according to claim 1, wherein in the step G, the contact is formed so as to contact the substrate. In the step F, the contact hole is formed to reach the first semiconductor layer,
The method of manufacturing a field effect transistor according to claim 1, wherein in the step G, the contact is formed so as to be in contact with at least the first semiconductor layer. A substrate composed of a semiconductor composed mainly of Si at least in the upper part;
A first semiconductor layer which is a buffer layer mainly made of Si and formed directly on the substrate;
A second semiconductor layer having at least a heterojunction layer formed so as to be heterojunction with the upper surface of the first semiconductor layer;
A gate insulating film formed on the second semiconductor layer;
A gate electrode formed on the gate insulating film;
A source region and a drain region which are located at least in the second semiconductor layer and are formed so as to sandwich the gate electrode in plan view;
A contact hole formed so as to penetrate at least the second semiconductor layer and reach the first semiconductor layer or the substrate;
A contact made of a conductor formed in contact with at least one of the first semiconductor layer and the substrate exposed at the bottom surface of the contact hole;
A field effect transistor comprising:   The field effect transistor according to claim 4, wherein the contact is formed so as to contact the substrate.   The field effect transistor according to claim 4, wherein the contact is formed to be in contact with at least the first semiconductor layer.   5. The field effect transistor according to claim 4, wherein the heterojunction layer of the second semiconductor layer is made of SiGe, SiGeC, SiC, or Ge.   The field effect transistor according to claim 4, wherein the second semiconductor layer includes the heterojunction layer and a Si layer formed on the heterojunction layer.   5. The field effect transistor according to claim 4, wherein the substrate is an SOI substrate, and the semiconductor constituting the upper portion of the substrate is an Si upper layer formed on an insulating film of the SOI substrate.   The field effect transistor according to claim 4, wherein the substrate is a bulk Si substrate.   The field effect transistor according to claim 4, wherein the contact is a body contact that electrically connects the gate electrode to the first semiconductor layer.

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