JP2018006412A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance CMOS inverter and CMOS circuit on a flexible substrate.SOLUTION: Provided is a CMOS inverter and CMOS circuit that consists of a TFT and that is provided on a flexible substrate. At least a p-channel TFT is a coupling type planar double gate structure poly-Ge TFT that has a gate electrode and a gate insulating film on an upper surface and a lower surface of the channel, or a four-terminal structure poly-Ge TFT whose upper and lower gate electrodes operate independently of each other.SELECTED DRAWING: Figure 12

Description

The present invention relates to the field of semiconductor technology for realizing flexible electronics and wearable electronics, and more particularly to technology for forming a high-performance complementary metal oxide semiconductor (CMOS) circuit on a deformable flexible substrate.

Recently, flexible electronics and wearable electronics are attracting attention as next-generation electronics.

Conventionally, thin film transistors (TFTs) made of organic semiconductors and TFTs made of oxide semiconductors have attracted attention as devices necessary for realizing these technologies. These devices are characterized by being capable of being formed at low temperatures, and thus can form TFTs on deformable plastics.

However, TFTs using these semiconductors are p-channel (p-ch) for organic TFTs and n-channel (n-ch) for oxide TFTs. Therefore, it is difficult to form a CMOS circuit with the same material. Therefore, a hybrid CMOS using different semiconductor materials is generally used.

A planar double-gate low-temperature polycrystalline germanium (poly-Ge) TFT having gate electrodes on the upper and lower surfaces of the channel and connected to the electrodes is a p-ch TFT. CMOS inverter and CMOS circuit.

Alternatively, a CMOS inverter on a flexible substrate, characterized in that a four-terminal planar double-gate low-temperature poly-Ge TFT that makes the upper and lower gate electrodes operate independently is a p-ch TFT, and CMOS circuit.

Recently, flexible electronics and wearable electronics are attracting attention as next-generation electronics. Conventionally, TFTs made of organic semiconductors and oxide semiconductors have attracted attention as devices necessary for realizing these technologies. These devices are characterized by being able to be formed at low temperatures, thus making it possible to form TFTs on deformable plastics. However, TFTs using these semiconductors can only drive p-ch organic TFTs and n-ch oxide TFTs. Therefore, it is impossible to form a CMOS circuit with the same material. Therefore, a hybrid CMOS using different semiconductor materials is generally used.

However, when forming a hybrid CMOS, it is difficult to align both n-ch and p-ch current drive capabilities. For example, an n-ch oxide TFT has a mobility of about 5 cm ² / Vs, while a p-ch organic TFT has a mobility of about 0.5 cm ² / Vs.

The present invention is characterized in that, in a CMOS inverter and a CMOS circuit made of TFTs formed on a flexible substrate, at least p-ch TFTs use planar double gate low-temperature poly-Ge TFTs.

It is known that a poly-Ge thin film having a crystal grain size of 50 nm or less exhibits a strong p-type. Moreover, the concentration of generated holes is very high, and when the TFT is operated, a large leakage current due to a large amount of holes is generated. For this reason, it is difficult to increase the on / off ratio during TFT operation. However, Ge is an attractive material in that it has a very high hole mobility and can be expected to have excellent p-ch TFT characteristics.

The present invention has been made in view of the above problems, and is a connected planar double gate structure having a gate electrode and a gate insulating film on the upper and lower surfaces of the channel, or a gate electrode and a gate insulating film on the upper and lower surfaces of the channel. The present invention relates to a CMOS inverter and a CMOS circuit on a flexible substrate, characterized in that a four-terminal planar double-gate low-temperature poly-Ge TFT having a gate electrode independently operating is used as at least a p-ch TFT.

As a result of intensive studies, the present inventor has conceived the following aspects of the invention.

At least the p-ch TFT is a low-temperature poly-Ge TFT having a planar double gate structure having a gate electrode and a gate insulating film on the upper and lower surfaces of the channel and a structure in which the electrodes are connected. CMOS inverter and CMOS circuit on flexible board.

Alternatively, at least the p-ch TFT is a planar double-gate low-temperature poly-Ge TFT having a gate electrode and a gate insulating film on the upper and lower surfaces of the channel and having a four-terminal structure in which the gate electrode operates independently. A CMOS inverter and a CMOS circuit on a flexible substrate.

The details will be described below.

Organic semiconductors have been studied as semiconductors that realize p-ch TFTs formed on flexible substrates, but their mobility is as low as about 0.5 cm ² / Vs, and stability and reliability are poor. However, a low temperature process is indispensable for forming a semiconductor device on a flexible substrate such as plastic. Organic semiconductors are the best candidates for TFTs on plastics because they can be formed at low temperatures.

On the other hand, the present invention is characterized in that a coupled planar double-gate low-temperature poly-Ge TFT or a four-terminal planar double-gate low-temperature poly-Ge TFT is used as a p-ch TFT. Since Ge has a higher mobility than Si and a melting point of 400 ° C., the process temperature, particularly the crystallization process temperature, can be lowered compared to Si while maintaining a high mobility.

Ge crystallized by a low temperature process has a small crystal grain size. In general, it is known that a poly-Ge thin film having crystal grains with a grain size of 50 nm or less exhibits a strong p-type. The concentration of generated holes is very high, and when a normal top or bottom TFT structure is operated, a large leakage current is generated due to a large amount of holes. For this reason, it is difficult to increase the on / off ratio during TFT operation, and it is difficult to form a good CMOS circuit.

To address this problem of poly-Ge TFTs, this patent describes a CMOS inverter on a flexible substrate and at least a p-ch TFT that constitutes a CMOS circuit, with a gate electrode and a gate insulating film on the upper and lower surfaces of the channel. It is a flat double-gate low-temperature poly-Ge TFT, or a four-terminal flat double-gate low-temperature poly-Ge TFT that has a gate electrode and a gate insulating film on the upper and lower surfaces of the channel and operates independently. Have

A poly-Ge TFT with this device structure can achieve a high on / off ratio of 2000 or more when the poly-Ge film thickness is set to 20 nm or less. In addition, even with a small crystal grain size of 50 nm or less, it is possible to achieve high performance with a mobility of 20 cm ² / Vs or more.

Since Ge has a melting point 400 ° C. lower than that of Si, the process temperature, particularly the crystallization process temperature, can be lowered compared to Si. Therefore, a CMOS circuit can be formed on a flexible substrate such as plastic.

According to the present invention, a low-temperature p-ch poly-Ge TFT having a high on-off ratio of 2000 or more and a mobility of 20 cm ² / Vs or more can be formed on a flexible substrate by a low-temperature process. A high-performance CMOS inverter and CMOS circuit can be realized on a flexible substrate.

As a first embodiment, the formation process and characteristics of a p-ch coupled planar double gate low-temperature poly-Ge TFT on glass in which gate electrodes on the upper and lower surfaces of the channel are coupled will be described in detail. FIG. 1 is a simplified cross-sectional schematic view of a device structure. The gate electrodes 2 and 6 are provided above and below the channel, and their positions coincide with each other.

First, as a first step, a bottom gate metal serving as a bottom gate electrode is formed on the glass substrate 1 by sputtering. Mo was adopted here. Next, the shape of the bottom metal gate 2 is processed by photolithography and wet etching.

Next, the gate insulating film 3 is formed by plasma CVD. Here, SiO ₂ having a thickness of 30 nm is used.

Subsequently, an amorphous Ge thin film is formed to a thickness of 15 nm by sputtering. Subsequently, after an amorphous Ge transistor island 4 is formed by photolithography and wet etching, copper (Cu) is attached to the surface. In this step, Cu was deposited on the surface of the amorphous Ge transistor island by immersing the substrate in a solution containing Cu.

Subsequently, a SiO ₂ film is applied using spin-on glass (SOG) and then dried.

Next, heat treatment is performed in vacuum at 350 ° C. for 10 hours. As a result, metal-induced solid phase growth of amorphous Ge transistor islands using Cu as a catalyst is performed, and the amorphous Ge transistor islands are changed to poly-Ge transistor islands 44.

Subsequently, the SOG oxide film is removed by HF, and the top gate insulating film 5 is formed by plasma CVD. Here, a 30 nm gate oxide film was formed.

Thereafter, a gate contact hole for connecting the top metal gate and the bottom metal gate is formed by reactive ion etching.

Subsequently, a top gate metal is formed by sputtering. Mo was used here. Next, a positive resist is applied to the upper layer.

Subsequently, using the back exposure, the resist on the top metal gate is exposed in a self-aligned manner with respect to the bottom gate using the bottom metal gate as a mask. Thereafter, unnecessary portions of Mo are etched, and the top gate metal 6 is formed in a self-aligned manner with the bottom gate.

Subsequently, an interlayer insulating film is formed, contact holes are formed, electrodes are formed, and the TFT is completed. The maximum temperature of the process is 350 ° C.

FIG. 3 shows a cross-sectional TEM photograph of the created connection plane type double gate low temperature poly-Ge TFT. The crystal grain size of Poly-Ge is about 30 nm, and the film thickness of poly-Ge is about 15 nm. FIG. 1 shows a schematic cross-sectional view of the completed TFT.

The transfer characteristics are shown in FIG. The output characteristics are shown in FIG.

As a result of analyzing the TFT characteristics, it was found that the on / off ratio exceeded 2000 and the mobility was 20 cm ² / Vs. This characteristic is superior to the p-ch TFT of low-temperature polycrystalline silicon TFT crystallized using a laser.

As a second embodiment, a process of forming a connecting planar double gate oxide TFT and a connecting planar double gate low-temperature poly-Ge TFT on a plastic substrate will be described. FIG. 6 shows a completed cross-sectional schematic view of the device. Here, the coupled planar double gate oxide TFT is used as an n-ch TFT. The coupled planar double gate low-temperature poly-Ge TFT is used as a p-ch.

First, polyimide 7 is applied on a glass substrate, and after drying and heat treatment, a buffer layer SiO ₂ 9 is formed thereon by plasma CVD. Here, the buffer layer SiO ₂ was grown to 300 nm.

Subsequently, a bottom gate metal to be a bottom gate electrode of both TFTs is formed by sputtering. Here, Mo was deposited. Next, a bottom gate metal electrode 2 of poly-Ge TFT and oxide TFT is formed by a photolithography process and wet etching.

Subsequently, the bottom gate insulating film 3 is formed using plasma CVD. Here, a 30 nm thick SiO ₂ film was formed by plasma CVD. A schematic diagram of the steps so far is shown in FIG.

Subsequently, after forming a resist mask in the formation region of the poly-Ge TFT, an oxide semiconductor is deposited to a thickness of 20 nm by sputtering. Subsequently, an oxide TFT transistor island 8 is formed by photolithography and wet etching. A schematic diagram of the steps so far is shown in FIG. Note that here, IGZO (In-Ga-Zn-O) was used as the oxide semiconductor.

Subsequently, after removing the resist in the poly-Ge TFT region, the oxide TFT transistor island 8
A protective film made of resist is formed in the region.

Subsequently, an amorphous Ge thin film is formed by sputtering. Here, a 15 nm amorphous Ge thin film was grown. Subsequently, an amorphous Ge transistor island 4 is formed by photolithography and wet etching. A schematic diagram of the steps so far is shown in FIG.

After removing the resist in the oxide semiconductor region, copper (Cu) is deposited on the amorphous Ge transistor island 4 and the IGZO transistor island 8. In this step, Cu was deposited by immersing the substrate in a solution containing Cu. A schematic diagram of the steps so far is shown in FIG.

Next, a SiO ₂ film is applied on the amorphous Ge transistor island 4 and the IGZO transistor island 8 by spin coating using a spin-on-glass solution and dried.

Subsequently, the amorphous Ge transistor island 4 is crystallized into a poly-Ge transistor island 44 by heat treatment at 350 ° C. for 10 hours in a vacuum. A schematic diagram of the steps so far is shown in FIG.

Next, after removing the SOG oxide film with HF, the top gate insulating film 5 is formed by plasma CVD. Here, 30 nm of SiO ₂ was formed by plasma CVD.

Subsequently, after forming a gate contact hole for connecting the top metal and the bottom metal to both TFTs, the top metal is formed. Here, Mo was formed by sputtering. Subsequently, a positive resist is applied.

Next, using back exposure, the resist on the top metal gate of poly-Ge TFT and IGZO TFT is exposed to the bottom gate in a self-aligned manner using the bottom metal gate as a mask. Thereafter, unnecessary portions of Mo are etched to form the top gate metal 6 in a self-aligned manner with the bottom gate metal.

Following the formation of the interlayer insulating film, contact holes are formed, metal electrodes for CMOS are formed, and CMOS is completed. FIG. 12 shows a cross-sectional view of the completed CMOS.

As described above, it is possible to form a CMOS on a flexible substrate using a low-temperature poly-Ge TFT having a gate-electrode and gate insulating film on the upper and lower surfaces of a channel and a low-temperature poly-Ge TFT having a p-ch as a p-ch. .

As a result, the TFT is a CMOS inverter and a CMOS circuit, and at least the p-ch TFT is a low-temperature poly-Ge TFT having a planar double gate structure having a gate electrode and a gate insulating film on the upper and lower surfaces of the channel. It is possible to form a CMOS inverter and a CMOS circuit on a flexible substrate.

The p-ch TFT is not limited to the coupled planar double gate low-temperature poly-Ge TFT shown in this embodiment, but a four-terminal planar double-gate low-temperature poly-Ge TFT in which the upper and lower gates operate independently. It may be.

Note that the n-ch TFT is not limited to an oxide, but may be Si or another semiconductor material.

The n-ch TFT is not limited to a coupled double gate structure, but may be a top gate structure, a bottom gate structure, or a four-terminal structure in which upper and lower gate electrodes operate independently.

The flexible substrate is not limited to plastic polyimide.

Further, the metal used for crystallization of Ge is not limited to Cu, but may be any metal such as Au, Al, Co that has an effect of promoting the crystallization of Ge at a low temperature.

Schematic drawing of completed cross section of connected planar double gate low temperature poly-Ge TFT. Schematic cross-section of a coupled planar double gate low temperature poly-Ge TFT. Sectional drawing after amorphous Ge formation. A cross-sectional TEM photograph of the channel portion of the fabricated coupled planar double gate low temperature poly-Ge TFT. Transfer characteristics of the fabricated coupled planar double gate low temperature poly-Ge TFT. Output characteristics of the fabricated coupled planar double gate low temperature poly-Ge TFT. Hybrid CMOS on plastic substrate with connected planar double gate oxide n-ch TFT with connected planar double gate low temperature poly-Ge TFT as P-ch TFT. Hybrid CMOS on plastic substrate with connected planar double gate oxide n-ch TFT after bottom gate oxide formation. Hybrid CMOS on plastic substrate with connected planar double gate oxide n-ch TFT after oxide semiconductor formation. Hybrid CMOS with connected planar double gate oxide n-ch TFT after amorphous Ge formation. Adsorb Cu on semiconductor surface Hybrid CMOS on plastic substrate with coupled planar double gate oxide n-ch TFT after amorphous Ge changed to poly-Ge After top gate oxide film is formed, top gate metal is formed by sputtering. Hybrid CMOS on plastic substrate with connected planar double gate oxide n-ch TFT with top gate electrode formed in self-alignment with bottom metal gate by back exposure after applying positive resist.

1. 1. Glass substrate 2. Bottom metal gate 3. Bottom gate oxide film Amorphous Ge thin film 44. 4. Poly-Ge thin film 5. Top gate oxide film 6. Top metal gate Polyimide 8. 8. Oxide semiconductor Buffer layer

Claims (8)

A CMOS inverter and a CMOS circuit comprising a thin film transistor (TFT), at least a p-channel TFT having a planar double gate structure having a gate electrode and a gate insulating film formed in a self-aligned manner on the upper and lower surfaces of the channel. A CMOS inverter and a CMOS circuit on a flexible substrate, characterized by being polycrystalline germanium (poly-Ge) TFT. 2. The planar double-gate low-temperature poly-Ge TFT in which upper and lower gate electrodes are connected to each other. 2. The planar double-gate low-temperature poly-Ge TFT having a four-terminal structure in which the upper and lower gate electrodes are independently operated. The crystal grain size of the Poly-Ge thin film is 50 nm or less. The film thickness of the Poly-Ge thin film is 20 nm or less. Poly-Ge thin films must be formed from amorphous Ge through a crystallization process using solid-phase growth, metal-induced solid-phase growth, laser crystallization, high-temperature gas injection technology, lamp heating, flash lamp annealing, etc. The claim 1-5 characterized by these. 7. The n-channel TFT and the p-channel planar double gate low-temperature poly-Ge TFT constituting the CMOS are laid out in the same plane on the same substrate. The n-channel TFT and the p-channel planar double-gate low-temperature poly-Ge TFT constituting the CMOS have a hierarchical structure and are three-dimensionally stacked.

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