JP2013222927A - Complementary semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a complementary semiconductor device and a method for manufacturing the same, capable of further reducing power consumption by achieving a dual channel CMOS structure which employs different channel materials for nMOSFET and pMOSFET.SOLUTION: A complementary semiconductor device comprises: a first semiconductor layer 12 formed on a part of a first insulator layer 11; a MOSFET of a first conductivity type formed on the first semiconductor layer 12; a first back gate electrode 13 formed in a position corresponding to the MOSFET of the first conductivity type under the first insulator layer 11; a second back gate electrode 16 formed on another part of the first insulator layer 11; a second insulator layer 17 formed on the second back gate electrode 16 and a second semiconductor layer 18 which is formed on the second insulator layer 17 and whose material differs from a material of the first semiconductor layer 12; and a MOSFET of a second conductivity type formed on the second semiconductor layer 18.

Description

  Embodiments described herein relate generally to a complementary semiconductor device and a method for manufacturing the same.

  As a CMOS structure for realizing a low power consumption LSI, an SOI-CMOS structure having a back gate electrode through a thin film non-doped body and a thin film embedded insulating film is promising. In such a structure, in addition to realizing a low power supply voltage by reducing threshold variation by channel non-doping, power consumption of the entire circuit is achieved by appropriately adjusting the threshold by applying a back gate voltage. be able to.

  In the threshold adjustment by the back gate, the most energy efficient circuit operation can be performed by independently controlling the nMOSFET and the pMOSFET. For this reason, a structure in which the back gate electrodes of the nMOSFET and the pMOSFET are provided electrically independently is desirable (for example, see Non-Patent Document 1).

  On the other hand, adopting a material having higher mobility than conventional Si as the channel material is also effective in reducing the power consumption of the CMOS. This is because the same drive current can be obtained with a small power supply voltage by using a channel material with high mobility (see, for example, Non-Patent Document 2).

However, in the conventionally proposed CMOS structure in which the back gate electrode is independently provided for the nMOSFET and the pMOSET, a so-called dual channel CMOS structure in which different channel materials are employed for the nMOSFET and the pMOSFET cannot be realized. That is, in order to form different channel materials in desired regions on the insulating film, a substrate bonding technique capable of highly precise position control, or materials having different lattice constants are selectively selected at desired positions on the Si substrate. A technique for epitaxial growth is required. However, a substrate bonding technique having an alignment accuracy of 0.1 μm or less required for CMOS-LSI and an epitaxial technique for suppressing the defect density to 10 ⁴ cm ⁻² or less have not been developed yet.

2010 Symposium on VLSI Technology Digest of Technical Papers, pp.43 IEEE Transaction on Electron Devices, vol 55, pp.21

  The problem to be solved by the invention is to provide a complementary semiconductor device capable of realizing a dual channel CMOS structure employing different channel materials for nMOSFET and pMOSFET, and capable of further reducing power consumption, and a method for manufacturing the same. It is to be.

  The semiconductor device of the embodiment is a complementary semiconductor device, and includes a first semiconductor layer formed in a part on a first insulator layer, and a first conductivity type formed in the first semiconductor layer. MOSFET, a first back gate electrode formed at a position corresponding to the first conductivity type MOSFET under the first insulator layer, and another part on the first insulator layer. The second back gate electrode, the second insulator layer formed on the second back gate electrode, and the first semiconductor layer formed on the second insulator layer are made of materials. And a second conductivity type MOSFET formed in the second semiconductor layer.

  According to an embodiment of the present invention, the nMOSFET and the pMOSFET are formed in different semiconductor layers, and the back gate electrode of the other MOSFET is formed in one semiconductor layer or an alloy thereof, thereby providing separate channels for the nMOSFET and the pMOSFET. A dual channel CMOS structure using materials and having electrically independent back gates can be realized, thereby further reducing power consumption.

Sectional drawing which shows the element structure of the Ge / InGaAs-CMOS type semiconductor device concerning 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. Sectional drawing which shows the element structure of the Ge / InGaAs-CMOS type semiconductor device concerning 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing an element structure of a complementary semiconductor device according to the first embodiment.

  This embodiment has a Ge / InGaAs-CMOS structure having an independent back gate, and the nMOSFET region is in the upper stage.

A buried insulating film (first insulator layer) 11 such as SiO ₂ , SiN, Al ₂ O ₃ , or HfO ₂ is formed on the p-type Si substrate 10. In the pMOS region 100, a Ge layer 12 is formed on the insulating film 11, and a first back gate electrode 13 made of an n ⁺ -type Si region is formed under the insulating film 11. In the nMOS region 200, a second back gate electrode 16 made of a Ge alloy on the insulating film 11, a buried insulating film (second insulator layer) 17 such as SiO _2, SiN, Al ₂ O ₃ , and HfO ₂ , and An In _x Ga _1-x As (0 <x <1) layer (second semiconductor layer) 18 is formed.

  A gate electrode 22 is formed on the Ge layer 12 via a gate insulating film 21, and a metal S / D region 23 is further formed to form a pMOSFET. A sidewall insulating film 24 is formed on the side surface of the gate portion. A gate electrode 32 is formed on the InGaAs layer 18 via a gate insulating film 31, and a metal S / D region 33 is further formed to constitute an nMOSFET. A sidewall insulating film 34 is formed on the side surface of the gate portion.

  Thus, the nMOSFET channel is InGaAs and the pMOSFET channel is Ge, and the back gate electrodes 13 and 16 are provided under the respective channels via the insulating film. The back gate electrode 16 of the nMOSFET is made of p-type or n-type doped Ge, or an alloy of a metal such as Ni, Co, Pt, or Ta and Ge, and the back gate electrode 13 of the pMOSFET has an n-type Si substrate. It is composed of a p-type doped region.

  Here, the buried insulating film 17 is also present under the back gate electrode 16 of the nMOSFET and is electrically insulated from the Si substrate 10. That is, the nMOS region 200 has a structure in which double insulator layers 11 and 17 exist. Since the back gate electrodes 13 and 16 of the pMOSFET and the nMOSFET are electrically cut off, the back gate voltage can be applied independently.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

  First, as shown in FIG. 2A, a so-called GOI (Ge on Insulator) substrate in which a Ge layer 12 is formed on a p-type Si substrate (support substrate) 10 via a buried insulating film 11 is used as a base substrate. use. There is no limitation on the method of manufacturing the GOI substrate, and an oxidation concentration method that utilizes the phenomenon that Ge is concentrated when oxidizing SiGe epitaxially grown on SOI, or a bonding method in which the Ge layer is bonded to the Si substrate via an insulating layer. It can be manufactured using a combination method.

The thickness of the Ge layer 12 is desirably about 100 nm or less in order to obtain a fully depleted device. More desirably, the thickness is 50 nm or less from the viewpoint of suppressing the short channel effect. For the insulating film 11 under the Ge layer 12, SiO ₂ , SiN, Al ₂ O ₃ , HfO _2, or a mixture thereof can be used. The film thickness of the insulating film 11 is desirably reduced within a range where leakage current does not cause a problem so that a large threshold modulation can be obtained with a constant power supply voltage. Typically, it is desirable to be about 50 nm or less.

Next, as shown in FIG. 2B, a mask material 14 such as SiO ₂ or SiN is deposited on both the pMOS region 100 and the nMOS region 200 by vapor deposition or the like, and then photolithography and etching are performed. The mask material 14 in the nMOS region 200 is removed. Thereafter, a metal film 15 is deposited on the entire surface by sputtering or vacuum evaporation. For example, Ni, Co, Pt, Ta or the like can be used as the metal material.

  Next, by performing heat treatment at 200 ° C. or higher, as shown in FIG. 2C, Ge and metal are reacted to form an alloy (germanide) 16 containing Ge. This alloy 16 is used as a second back gate electrode of the nMOSFET.

  Next, as shown in FIG. 2D, the unreacted metal remaining on the germanide 16 and the metal film 15 deposited on the mask material 14 are removed by etching using hydrochloric acid, for example. Further, the mask material 14 is also removed. At this time, it is desirable to select an etching solution having a high selectivity between metal and germanide. In the figure, all of the GOI not covered with the mask material 14 is shown to be germanide, but unreacted Ge may remain. Further, alloying is not performed for the formation of the back gate electrode, and only p-type or n-type doping may be performed.

  Through the above process, an alloy layer of metal and Ge is formed only in the nMOS region 200 with respect to the GOI substrate, whereby the back gate electrode 16 for nMOS is formed.

  Next, as illustrated in FIG. 3E, the InGaAs layer 18 is bonded onto the GOI substrate in which germanide is formed in the nMOS region 200. Prior to bonding, the GOI substrate may be subjected to surface planarization treatment using chemical mechanical polishing (CMP) or the like as appropriate. As the InGaAs layer 18, a layer epitaxially grown on a support substrate 19 such as InP is used. Here, the InGaAs layer 18 does not necessarily have a single composition, and the composition may be modulated in the film thickness direction.

At the time of bonding, an insulating film 17 is deposited on the InGaAs layer 18, the Ge layer 12 and the germanide 16, or both, and then a bonding process is performed. As the insulating film type, an insulating film such as SiO ₂ , SiN, Al ₂ O ₃ , HfO _2, or a mixture thereof can be used similarly to the GOI substrate, and the film thickness is desirably about 50 nm or less.

  Next, as shown in FIG. 3F, the InGaAs layer 18 is exposed on the surface by removing the support substrate 19 of the InGaAs layer 18 such as InP using mechanical polishing, CMP, or other various etching techniques. At this time, the thickness of the InGaAs layer 18 may be adjusted. Similar to the thickness of the GOI layer, the thickness of the InGaAs layer 18 is preferably about 100 nm or less, more preferably 50 nm or less.

  Next, as shown in FIG. 3G, in a state where only the pMOS region 100 is exposed by photolithography, the InGaAs layer 18 and the insulating film 17 therebelow are removed, and the Ge layer 12 is exposed on the surface of the pMOS region 100. Let For the etching of the InGaAs layer 18, for example, a mixed solution of phosphoric acid and hydrogen peroxide water can be used, and for the etching of the insulating film 17, for example, hydrogen fluoride can be used. Of course, it is also possible to use dry etching instead of wet etching.

Next, as shown in FIG. 3H, element isolation between the pMOS region 100 and the nMOS region 200 is performed. That is, the Ge layer 12, the alloy 16, the insulating film 17, and the InGaAs layer 18 are removed by etching at the boundary between the pMOS region 100 and the nMOS region 200. Further, n-type impurities are ion-implanted into the surface of the Si substrate 10 through the Ge layer 12 and the insulating film 11 to form an n ⁺ -type Si region (first back gate electrode) 13 for pMOS.

  Thereafter, by performing a conventionally proposed SOI-CMOS with back gate, the nMOSFET channel is InGaAs, the pMOSFET channel is Ge, and each has an independent back gate, as shown in FIG. A simple CMOS can be realized.

Specifically, the gate electrodes 22 and 32 such as TaN are formed on the Ge layer 12 and the InGaAs layer 18 via the gate insulating films 21 and 31 such as Al ₂ O ₃ and HfO ₂ , respectively. Side wall insulating films 24 and 34 are formed. Then, by forming the metal S / D regions 23 and 33, a pMOSFET and an nMOSFET are formed. Here, the gate insulating films 21 and 31, the gate electrodes 22 and 32, and the side wall insulating films 24 and 34, which are the same elements in the pMOSFET and the nMOSFET, can be formed of the same material at the same time.

  As described above, according to the present embodiment, a dual channel CMOS structure using channel materials suitable for the nMOSFET and the pMOSFET can be realized in the CMOS structure in which the back gate electrode is independently provided for the nMOSFET and the pMOSFET. For this reason, it is possible to further reduce the power consumption of the CMOS-LSI.

  In addition, since the pMOS and nMOS semiconductor layers 11 and 18 are not provided on the same surface, but the pMOS and nMOS semiconductor layers 11 and 18 are separate layers, it is necessary to perform high-precision alignment when bonding the substrates. Absent. Further, since the back gate electrodes 13 and 16 for pMOS and nMOS have steps, there is an advantage that the insulation between the back gate electrodes 13 and 16 is facilitated.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing the element structure of the complementary semiconductor device according to the second embodiment. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  This embodiment has a Ge / InGaAs-CMOS structure having an independent back gate, and the pMOSFET region is in the upper stage.

  In the first embodiment, it is assumed that the GOI substrate is a base substrate, but in this embodiment, an InGaAs-OI substrate is used as the base substrate.

The buried insulating film 11 is formed on the n-type Si substrate 40, the InGaAs layer (first semiconductor layer) 42 is formed on the insulating film 11 in the nMOS region 200, and the p ⁺ -type Si region is formed below the insulating film 11. A first back gate electrode 43 is formed. In the pMOS region 100, a second back gate electrode 46 made of an InGaAs alloy, a buried insulating film 17, and a Ge layer (second semiconductor layer) 48 are formed on the insulating film 11.

  Then, the gate electrode 22 is formed on the Ge layer 48 via the gate insulating film 21, and the metal S / D region 23 is further formed, whereby the pMOSFET is configured. A gate electrode 32 is formed on the InGaAs layer 42 via the gate insulating film 31, and a metal S / D region 33 is further formed, whereby an nMOSFET is configured.

  In this embodiment, the vertical relationship between the nMOSFET and the pMOSFET is opposite to that of the first embodiment, but the manufacturing process is substantially the same as that of the first embodiment.

  As described above, according to the present embodiment, a dual channel CMOS structure using channel materials suitable for the nMOSFET and the pMOSFET can be realized in the CMOS structure in which the back gate electrode is independently provided for the nMOSFET and the pMOSFET. Therefore, the same effect as in the first embodiment can be obtained.

(Modification)
The present invention is not limited to the above-described embodiments.

  In the embodiment, InGaAs and Ge are used as channel materials. However, the present invention is not limited to these, and InSb, GaSb, SiGe, GeSn, and compounds thereof can also be employed. For example, it is desirable to use GaAs, InGaAs, InAs, InSb or the like having high electron mobility for the nMOSFET region, and Ge, SiGe, GeSn or the like having high hole mobility is desirably used for the pMOSFET region. Furthermore, conditions such as the material, composition, and film thickness of each part other than the channel can be appropriately changed according to the specifications.

  In addition, the back gate electrodes of the pMOS and nMOS may be selected from impurities doped or alloys with metals. Furthermore, the S / D region is not necessarily made of metal, and can be formed by impurity doping.

  Further, the first back gate electrode may be formed in advance at the time of the GOI substrate, not after the formation of the elements in the pMOS region and the nMOS region. Further, in order to prevent damage to Ge due to impurity ions, it may be selectively formed on the surface portion of the support substrate before the Ge layer is formed.

  In addition, the manufacturing method is not necessarily limited to the steps described in FIGS. 2 and 3, and the first semiconductor layer and the second semiconductor layer are formed in separate layers, and the first semiconductor layer or Any method can be used as long as the back gate of the second semiconductor layer can be formed using the alloy.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

10 ... p-type Si substrate 11 ... buried insulating film (first insulator layer)
12 ... Ge layer (first semiconductor layer)
13... N ⁺ type Si region (first back gate electrode)
14 ... Mask material 15 ... Metal film 16 ... Ge alloy (second back gate electrode)
17 ... Embedded insulating film (second insulator layer)
18 ... InGaAs layer (second semiconductor layer)
DESCRIPTION OF SYMBOLS 19 ... InP substrate 21, 31 ... Gate insulating film 22, 32 ... Gate electrode 23, 33 ... S / D area | region 24, 34 ... Side wall insulating film 40 ... N-type Si substrate 42 ... InGaAs layer (1st semiconductor layer)
43... P ⁺ type Si region (first back gate electrode)
46. InGaAs alloy layer (second back gate electrode)
48 ... Ge layer (second semiconductor layer)
100 ... pMOS region 200 ... nMOS region

Claims (11)

A first semiconductor layer formed in part on the first insulator layer;
A first conductivity type MOSFET formed in the first semiconductor layer;
A first back gate electrode formed at a position corresponding to the first conductivity type MOSFET under the first insulator layer;
A second back gate electrode formed on another portion of the first insulator layer;
A second insulator layer formed on the second back gate electrode; a second semiconductor layer formed on the second insulator layer and made of a different material from the first semiconductor layer;
A second conductivity type MOSFET formed in the second semiconductor layer;
A complementary semiconductor device comprising: The first conductivity type is p-type, the second conductivity type is n-type,
The complementary type according to claim 1, wherein the first semiconductor layer is made of Ge, and the second semiconductor layer is made of In _x Ga _1-x As (0 <x <1). Semiconductor device.   3. The complementary semiconductor device according to claim 2, wherein the second back gate electrode is made of an alloy containing Ge.   The base of the first insulator layer is a p-type Si substrate, and the first back gate electrode is formed by doping a surface portion of the Si substrate with an n-type impurity. Item 3. A complementary semiconductor device according to Item 2. The first conductivity type is n-type, the second conductivity type is p-type,
2. The complementary type according to claim 1, wherein the first semiconductor layer is made of In _x Ga _1-x As (0 <x <1), and the second semiconductor layer is made of Ge. Semiconductor device. 6. The complementary semiconductor device according to claim 5, wherein the second back gate electrode is made of an alloy containing In _x Ga _1-x As (0 <x <1).   The foundation of the first insulator layer is an n-type Si substrate, and the first back gate electrode is formed by doping a surface portion of the Si substrate with a p-type impurity. Item 6. A complementary semiconductor device according to Item 5. A first region where a pMOSFET is to be formed is covered with a mask material for the first semiconductor layer formed on the first insulator layer, and the first region is formed in a second region where an nMOSFET is to be formed. Forming an nMOS back gate electrode made of an alloy obtained by reacting a semiconductor layer and a metal;
Forming a second insulator layer on the first semiconductor layer and the nMOS back gate electrode;
Forming a second semiconductor layer made of a material different from that of the first semiconductor layer on the second insulator layer using a substrate bonding technique;
Removing the second semiconductor layer and the second insulator layer in the first region;
Forming a back gate electrode for pMOS under the first region of the first insulator layer;
Forming a pMOSFET in the first semiconductor layer exposed by removing the second semiconductor layer and the second insulator layer, and forming an nMOSFET in the second semiconductor layer;
A method of manufacturing a complementary semiconductor device, comprising:   9. The method of manufacturing a complementary semiconductor device according to claim 8, wherein Ge is used as the first semiconductor layer, and InGaAs is used as the second semiconductor layer. A first semiconductor layer formed on the first insulator layer is covered with a mask material in a first region where an nMOSFET is to be formed, and the first region is formed in a second region where a pMOSFET is to be formed. Forming a back gate electrode for pMOS made of an alloy obtained by reacting a semiconductor layer and a metal;
Forming a second insulator layer on the first semiconductor layer and the pMOS back gate electrode;
Forming a second semiconductor layer made of a material different from that of the first semiconductor layer on the second insulator layer using a substrate bonding technique;
Removing the second semiconductor layer and the second insulator layer in the first region;
Forming an nMOS back gate electrode under the first region of the first insulator layer;
Forming an nMOSFET in the first semiconductor layer exposed by removing the second semiconductor layer and the second insulator layer, and forming a pMOSFET in the second semiconductor layer;
A method of manufacturing a complementary semiconductor device, comprising:   11. The method of manufacturing a complementary semiconductor device according to claim 10, wherein InGaAs is used as the first semiconductor layer, and Ge is used as the second semiconductor layer.

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