CN111293085A - Three-dimensional CMOS (complementary metal oxide semiconductor) based on two-dimensional transition metal chalcogenide and tellurium and preparation method thereof - Google Patents
Three-dimensional CMOS (complementary metal oxide semiconductor) based on two-dimensional transition metal chalcogenide and tellurium and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 28
- 229910052714 tellurium Inorganic materials 0.000 title claims abstract description 15
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 title claims abstract description 15
- 230000000295 complement effect Effects 0.000 title claims abstract description 14
- 229910052723 transition metal Inorganic materials 0.000 title claims abstract description 11
- -1 transition metal chalcogenide Chemical class 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 13
- 150000004706 metal oxides Chemical class 0.000 title abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000000126 substance Substances 0.000 claims abstract description 24
- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical compound C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000001259 photo etching Methods 0.000 claims abstract description 21
- 230000005669 field effect Effects 0.000 claims abstract description 12
- 239000011241 protective layer Substances 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims description 33
- 239000010409 thin film Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 238000005566 electron beam evaporation Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 238000001704 evaporation Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000000231 atomic layer deposition Methods 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000002207 thermal evaporation Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 7
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000010894 electron beam technology Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000009616 inductively coupled plasma Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052961 molybdenite Inorganic materials 0.000 claims description 4
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 239000003513 alkali Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000000428 dust Substances 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 210000000003 hoof Anatomy 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 2
- 239000003960 organic solvent Substances 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 239000004033 plastic Substances 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 150000004770 chalcogenides Chemical class 0.000 claims 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 1
- 238000003860 storage Methods 0.000 claims 1
- 150000003624 transition metals Chemical class 0.000 claims 1
- 238000004506 ultrasonic cleaning Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 7
- 230000006872 improvement Effects 0.000 abstract description 3
- 230000009467 reduction Effects 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract description 2
- 239000010931 gold Substances 0.000 description 12
- 238000012546 transfer Methods 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 239000002041 carbon nanotube Substances 0.000 description 3
- 229910021393 carbon nanotube Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a three-dimensional CMOS (complementary metal oxide semiconductor) based on a two-dimensional transition metal chalcogenide and tellurium and a preparation method thereof. The three-dimensional CMOS is formed by connecting an N-channel field effect transistor with TMDs as an active layer and a P-channel field effect transistor with a simple substance tellurium (Te) as an active layer; the CMOS with the three-dimensional structure can realize digital logics such as inverters, NAND gates, NOR gates and the like, and functions of other analog circuits and radio frequency analog circuits. The preparation method comprises the following steps: preparing a device substrate; preparing TMDS or simple substance Te, and preparing a bottom layer field effect transistor by maskless photoetching; preparation of simple substance Te or TMDS and field effect transistor (through hole and oxide protective layer) thereof. The invention prepares the three-dimensional CMOS through maskless photoetching, and the device has the advantages of multifunctional integration, interconnection shortening, integration level improvement, power consumption reduction and the like.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a monolithic three-dimensional CMOS (complementary metal oxide semiconductor) based on two-dimensional transition metal chalcogenide (TMDs) and tellurium and a preparation method thereof.
Background
Integrated Circuits (ICs) have been widely used in modern life due to their advantages of small size, light weight, long life, high reliability, and good performance, and are indispensable members of electronic products for processing, transmitting, and storing information. In ICs, N-channel field effect transistors (N-MOSFETs) and P-channel MOSFETs (P-MOSFETs) are necessary devices for Complementary Metal Oxide Semiconductors (CMOS), and therefore, the integration of ICs needs to be improved by reducing the CMOS, i.e., reducing the size of the MOSFETs, and in order to effectively turn on and off the MOSFET devices, the channel film needs to be reduced to a nanometer level.
Two-dimensional transition metal chalcogenides (TMDs, e.g. MoS)2、WS2Etc.) in which a single layer of MoS is mechanically exfoliated2Thin film FET mobility in excess of 200 cm2V-1s-1On-off ratio of more than 107And the operability of TMDs in a single layer thickness has been applied to the fabrication of monolithic three-dimensional Complementary Metal Oxide Semiconductor (CMOS) logic devices, however, the application of TMDs thin films in integrated circuits has been limited due to the small area of the mechanical release material and the transfer technique of CVD thin films. Recently, with the improvement of the high temperature CVD for the production of TMDS thin films and the transfer technique, TMDS thin films are used for the production of CMOS, such as layered WSe for Huzhengming et al2And MoS2Nanostructured elemental P-type semiconductor materials, such as amorphous silicon (α -Si), poly-germanium (P-Ge), and Carbon Nanotubes (CNT) due to low hole mobility (α -Si mobility less than 1 cm)2V-1s-1) Impurity residue (gold for p-Ge annealing)Belongs to the field of catalyst; CNT is a metal catalyst in CVD fabrication), etc., limiting its use in CMOS. Single crystal tellurium (Te) having energy band Eg=0.31eV has a high hole mobility of 700cm2V-1s-1The mobility of the heat evaporation elementary substance Te film in the experiment can reach hundreds of cm2V-1s-1The method becomes a research hotspot of future simple substance P-type semiconductor materials; the Ali Javey utilizes a substrate with the low temperature of-80 ℃ to prepare a simple substance Te film and realizes a three-dimensional CMOS multifunctional logic circuit based on the Te film.
Compared with other nano-scale thickness materials, the N-type TMDs and the P-type simple substance Te have higher mobility, but the preparation of a CMOS (complementary metal oxide semiconductor) based on the TMDs and the P-type simple substance tellurium (Te) thin film is not researched at present; and the circuit integration of preparing the simple substance Te film and preparing the CMOS by other two-dimensional materials under the low-temperature (-80 ℃) substrate is not carried out.
Disclosure of Invention
Aiming at the defects of the existing TMDs, P-type simple substance Te film CMOS and the circuit integration technology thereof, the invention aims to provide a novel TMDs and P-type simple substance Te complementary metal oxide semiconductor device and a preparation method thereof. The semiconductor device can realize various logic gate controls, has simple preparation process and low cost, and can further promote the application of TMDs in CIs.
The invention provides a monolithic three-dimensional CMOS (complementary metal oxide semiconductor) device based on two-dimensional transition metal chalcogenide (TMDS) and tellurium (Te), which is formed by connecting an N-channel field effect transistor (marked as N-FET) with a layer of TMDS as an active layer and a P-channel field effect transistor (marked as P-FET) with a layer of simple substance Te as an active layer; the CMOS with the three-dimensional structure can realize digital logics such as inverters, NAND gates, NOR gates and the like, and functions of other analog circuits and radio frequency analog circuits.
The invention provides a preparation method of a monolithic three-dimensional CMOS device based on two-dimensional transition metal chalcogenide and tellurium.
(1) Preparing substrate of device, including selecting material, cleaning, pretreating, and aligning
The device substrate can be a silicon wafer (containing a thin silicon oxide layer), sapphire, quartz, glass, polymer or plastic and the like; the material can be selected according to the type of the transistor in the CMOS structure to be prepared, for example, a bottom layer transistor is a back gate and a buried gate transistor, and a silicon wafer containing a silicon oxide thin layer, sapphire and quartz are used as a substrate; the bottom layer transistor is a top gate transistor, and any material can be used as a substrate;
the cleaning of the substrate aims to remove impurities and dust remained on the surface of the substrate in the processes of processing, transporting, storing and using, and the substrate can be cleaned by adopting ultrasonic waves such as an organic solvent, diluted acid alkali liquor, deionized water and the like;
the pretreatment of the substrate mainly comprises the steps of enhancing the adhesion between the substrate and a device and reducing the roughness of the surface of the substrate, and the substrate can be pretreated in the modes of baking or heating by using an oven or a constant-temperature heating table, plasma treatment or spin coating of photoresist, coating and the like; the alignment marks are used to facilitate precise alignment between processes during device fabrication.
(2) Preparing N-type TMDS (or P-type simple substance Te) on a device substrate as an active layer film of a bottom layer transistor; based on the bottom active film, preparing a bottom transistor by using the technologies of maskless photoetching, etching, film deposition and the like;
the N-type TMDs film can be prepared into a two-dimensional atomic crystal film material with a small area by a mechanical stripping mode, or a two-dimensional atomic crystal film material with a large area by a Chemical Vapor Deposition (CVD) method or a physical vapor deposition method; the transfer can be realized by transferring the TMDS film onto a target substrate by adopting a dry method and a wet method according to the substrate and the film;
here, the TMDS thin film material may be MoS2、WS2、Bi2S3ZnS or CdS, etc.;
the P-type simple substance hoof is a simple substance Te film with the thickness of below 100nm formed by conventional photoetching at the temperature of minus 80 ℃ or a hard mask plate through thermal evaporation;
an N-type TMDS film or a simple substance Te film is used as an active layer of a bottom transistor and a top transistor to be prepared;
the hard mask (which can be prepared by photoetching, wet etching, deep silicon etching and other methods) is used for aligning the substrate and the silicon-based mask by adopting a high-precision alignment platform device. The manufacturing method can refer to a high-precision silicon-based through hole mask split graphic structure (CN 109188858A) and a preparation method of an ultra-high precision silicon-based through hole graphic structure (CN 105261588A), and can refer to a micro device for precision mask alignment (CN 203932033U) and a device for assisting the precision alignment of a hard through hole mask and a sample (CN 109065493A);
the maskless photoetching adopts equipment such as electron beam photoetching, laser direct writing and the like;
the etching is mainly used for etching two-dimensional transition metal chalcogenide (TMDS) and connecting through holes among devices, the etching of the TMDS can be carried out by dry etching of reactive plasma (RIE) containing F + gas, Plasma Etching (PE) or inductively coupled plasma etching (ICP) equipment, and the through hole etching can be carried out by dry etching and wet etching;
the thin film deposition is to deposit a thin film by using modes of Thermal Evaporation (TE), Electron Beam Evaporation (EBE), Atomic Layer Deposition (ALD), magnetron sputtering, Physical Vapor Deposition (PVD) and the like, so as to prepare a metal electrode, a connecting through hole and an insulating layer (a gate dielectric seed layer and a gate dielectric layer) of a bottom transistor.
(3) Preparation of spacers for bottom layer transistors and top layer transistors
The interlayer of the bottom layer transistor and the top layer transistor is made of silicon oxide (SiO)2) Zirconium oxide (ZrO)2) Hafnium oxide (HfO)2) Alumina (Al)2O3）、SixCyOzOr SixByCzNkThe insulator thin film is mainly prepared by methods such as Thermal Evaporation (TE), Electron Beam Evaporation (EBE), Atomic Layer Deposition (ALD) and the like. The spacer layer may also serve as a gate dielectric layer for the transistor.
(4) Preparing a P-type Te thin film (or an N-type TMDS thin film) on the bottom transistor to be used as an active layer thin film of the top transistor; and preparing a top transistor (including etching a through hole and preparing a protective layer) based on the active layer film of the top transistor.
In the invention, in the step (2), when the active layer thin film of the bottom transistor is N-type TMDS, corresponding to the step (4), the active layer thin film of the top transistor is P-type Te; in the step (2), when the active layer thin film of the bottom transistor is P-type Te, corresponding to the step (4), the active layer thin film of the top transistor is N-type TMDs; thereby forming TMDs and elemental Te of P-type complementary metal oxide semiconductor devices (i.e., three-dimensional CMOS devices).
In the invention, the top transistor can be prepared according to the type and the structure of the bottom transistor and the preparation method; the preparation method of the oxide protective layer is consistent with that of the oxide interlayer, namely the insulating layer.
The protective layer is mainly used for preventing the exposed outermost layer of the N-type TMDS or P-type simple substance Te thin film from contacting with air, water and the like to shorten the service life of the device, and in order to ensure the service life of the CMOS, a protective layer can be prepared on the top FET of the whole three-dimensional CMOS; the protective layer may be an oxide or a stable metal layer.
In the invention, the bottom layer transistor and the top layer transistor can be top and bottom gate transistors, buried gate transistors or surrounding gate transistors.
In the invention, the bottom transistor and the top transistor can be gated by the same gate, namely the gate is shared.
The invention provides a novel TMDs and P-type simple substance Te complementary metal oxide semiconductor device, a single-chip three-dimensional CMOS is prepared by maskless photoetching, the preparation process is simple, the cost is low, and the device has the advantages of multifunctional integration, interconnection shortening, integration level improvement, power consumption reduction and the like.
Drawings
Fig. 1 is a schematic diagram of a single three-dimensional common-gate CMOS structure in embodiment 1 of the present invention. Wherein the substrate is Polyimide (PI), the top layer transistor is P-type channel bottom gate field effect crystal of simple substance Te, and the bottom layer transistor is WS2The N-type channel top gate field effect transistor of (1).
Fig. 2 is a schematic diagram of a single three-dimensional buried gate-bottom gate CMOS structure in embodiment 2 of the present invention. Wherein the substrate is 300nmSiO2The top transistor is MoS2The bottom layer transistor is a buried gate bottom gate field effect crystal of a P-type channel of a simple substance Te.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The invention is illustrated in the accompanying drawings by way of example and with reference to the accompanying figures, which are intended to explain the method of fabricating a thin film transistor device using an all silicon-based reticle of the invention. The specific embodiments described herein are merely illustrative of the present invention and do not limit the scope of the invention.
EXAMPLE 1 preparation of monolithic three-dimensional common-gate CMOS
(1) Preparing a substrate, respectively ultrasonically cleaning a Polyimide (PI) substrate with acetone, isopropanol and deionized water in sequence, and evaporating 20nm of silicon oxide (SiO) on the PI by using an electron beam evaporation device2) Making the PI substrate smoother, and depositing SiO by laser direct writing, electron beam evaporation of Au, liftofoff, etc2Making an alignment mark on the PI;
(2) and preparing a bottom active layer and a transistor. Preparation of WS on silicon wafers by mechanical lift-off2Film, WS prepared by mechanically peeling silicon wafer by dry transfer2Film transfer to SiO2And a marked PI substrate; preparing a bottom layer transistor: laser direct writing photoetching Source and Drain (SD) electrode patterns of bottom layer transistor, evaporating Ti of 5nm and Au of 35nm on the source and drain electrode patterns by using electron beam evaporation equipment, preparing SD electrode after liftoff, and taking the source electrode as V of CMOSssA terminal; preparation of 2nm SiO by electron beam evaporation2And alumina (Al)2O3) A seed layer as a gate dielectric; preparation of 20nm hafnium oxide (HfO) by ALD2) As the gate dielectric layer of the bottom transistor; laser direct writing photoetching to form common gate electrode pattern of bottom transistor and top transistor, and electron beam evaporating equipment to form common gate35nm Au is evaporated on the pattern of the electrode, a common gate electrode is prepared after liftoff, and the common gate electrode is a signal input end Vin of the CMOS;
(3) top layer transistor fabrication, fabrication of 20nm HfO by ALD2As the gate dielectric layer of the top transistor, making via hole pattern by laser direct writing photoetching, and making ICP at SF6Etching the through hole under the atmosphere of (1), wherein the etching depth of the through hole is 80nm, and evaporating and plating 80nm Au and liftoff on an electron beam evaporation device; the prepared hard mask is aligned with the alignment mark on the substrate by using a high-precision alignment platform, and the manufacturing and alignment methods of the hard mask can be found in the patent of a high-precision silicon-based through hole mask split graphic structure (CN 109188858A) and the preparation method of an ultra-high precision silicon-based through hole graphic structure (CN 105261588A), the utility model discloses a micro device for aligning the precision mask (CN 203932033U) and a device for assisting the precision alignment of the hard through hole mask and a sample (CN 109065493A). Putting the aligned high-precision alignment platform, the hard mask plate and the substrate into a thermal evaporation device, reducing the temperature of the substrate to-80 ℃ by using liquid nitrogen, evaporating 10nm of elemental tellurium, directly writing and photoetching a pattern of a Source Drain (SD) electrode of a top transistor by using laser based on elemental Te, evaporating 35nm of Au on the pattern of the source drain electrode by using an electron beam evaporation device, preparing the SD electrode of the top transistor after liftoff, wherein a source electrode D is a power supply end V of a CMOS (complementary metal oxide semiconductor)DDThe drain electrode is connected with the bottom layer transistor to serve as a signal output end V of the CMOSout. Preparation of 20nm Al by ALD2O3As a protective layer.
EXAMPLE 2 preparation of a monolithic three-dimensional buried-bottom-gate CMOS
(1) Preparation of the substrate. Sequentially and respectively ultrasonically cleaning Si/300nmSiO by using acetone, isopropanol and deionized water2A substrate;
(2) and preparing a bottom layer buried gate transistor. Laser is used for directly writing and photoetching a buried gate electrode of a bottom layer transistor and a pattern of an alignment mark, and BOE etching liquid is used for etching Si/300nmSiO2SiO on substrate2Etching depth of 35nm, and forming buried gate electrode and gate electrodeEtching a groove on the pattern of the cross-shaped alignment mark, removing photoresist, photoetching the etched pattern by aligning a laser direct writing device, evaporating and evaporating 35nm Au by using an electron beam, and preparing a buried gate electrode of a bottom layer transistor after liftoff; preparation of 20nm Al by ALD2O3As the gate dielectric layer of the bottom transistor; the method comprises the following steps of (1) directly writing and photoetching an active layer pattern of a bottom transistor by using laser, placing a substrate with the active layer pattern in thermal evaporation equipment, reducing the temperature of the substrate with the active layer pattern to-80 ℃ by using liquid nitrogen, evaporating 8nm of elemental tellurium, preparing an elemental tellurium active layer after liftoff, directly writing and photoetching a source-drain (SD) electrode pattern of the bottom transistor by using laser based on elemental Te, evaporating 35nm of Au on the source-drain electrode pattern by using electron beam evaporation equipment, preparing an SD electrode of the bottom transistor after liftoff, and using an S electrode of the SD electrode as a power supply end Vss of an inverter;
preparation of 20nm SiO by electron beam evaporation2Using laser to directly write the pattern of the gate electrode of the bottom transistor and the connecting via hole of the gate electrode of the top transistor as the oxide spacers of the bottom transistor and the top transistor, placing the wafer with the gate-gate electrode connecting via hole pattern in Plasma Equipment (PE), and using SF6Gas etching the through hole, wherein the etching depth is 45nm, 45nm Au is plated through magnetron sputtering, and after liftoff, a connecting through hole between gate electrodes is prepared and can be used as a signal input end Vin of a CMOS (complementary metal oxide semiconductor);
(3) and preparing a top-layer bottom-gate transistor. Directly writing a pattern of a top gate electrode of the top layer transistor by using laser, evaporating 35nm Au on the pattern of the gate electrode by using electron beam evaporation equipment, and preparing the top gate electrode of the bottom layer transistor after liftoff; preparation of 20nm Al by ALD2O3As the gate dielectric layer of the top transistor; MoS prepared by CVD on silicon wafer by adopting large-area dry transfer equipment2Top Al with thin film transfer to top layer transistor2O3On the gate dielectric layer, the specific transfer method and equipment can refer to a patent of a transfer platform for transferring large-area two-dimensional materials in a vacuum environment (CN 201820102682); using photoresist as mask, RIE equipment in CHF3Etching CVDMoS under atmosphere2The film being a roofThe channel of the layer transistor. Laser direct writing photoetching the patterns of the drain electrode of the bottom transistor and the connecting through hole of the source electrode of the top transistor, etching the through hole by reactive plasma equipment (RIE), and using CF4And etching a 25nm through hole by gas, evaporating 25nm Au by magnetron sputtering, and connecting the bottom and top drain electrodes with the through hole after liftoff. Laser is directly written on the etched CVD film to etch the patterns of a Source Drain (SD) electrode of a top layer transistor, the source electrode pattern is connected with a bottom top layer drain connecting through hole, an electron beam evaporation device evaporates 5nm Ti and 35nm Au on the source drain electrode pattern, the SD electrode is prepared after liftoff, and the S electrode is a signal output end V of a phase inverteroutD electrode is V of inverterDD。
Claims (9)
1. A monolithic three-dimensional CMOS based on two-dimensional transition metal chalcogenide and tellurium is characterized by being formed by connecting a layer of N-channel field effect transistor taking TMDS as an active layer and a layer of P-channel field effect transistor taking elemental tellurium as an active layer; the CMOS with the three-dimensional structure can realize digital logics such as inverters, NAND gates, NOR gates and the like, and functions of other analog circuits and radio frequency analog circuits.
2. The method for preparing the two-dimensional transition metal chalcogenide and tellurium-based monolithic three-dimensional CMOS as claimed in claim 1, comprising the specific steps of:
(1) preparing a device substrate, including material selection, cleaning, pretreatment and alignment mark of the substrate;
(2) preparing an N-type TMDS or a P-type simple substance Te on a device substrate as an active layer film of a bottom layer transistor; based on the bottom active film, preparing a bottom transistor by using the technologies of maskless photoetching, etching, film deposition and the like;
(3) preparation of spacers for bottom layer transistors and top layer transistors
The interlayer is made of silicon oxide, zirconium oxide, hafnium oxide, aluminum oxide and SixCyOzOr SixByCzNkThin film of insulator, mainly by thermal evaporationElectron beam evaporation or atomic layer deposition; the interlayer can also be used as a gate dielectric layer of the transistor;
(4) preparing a P-type Te thin film or an N-type TMDS thin film on the bottom transistor to be used as an active layer thin film of the top transistor; preparing a top transistor based on the active layer film of the top transistor, wherein the steps of etching a through hole and preparing an oxide protective layer are included;
in the step (2), when the active layer thin film of the bottom transistor is N-type TMDS, corresponding to the step (4), the active layer thin film of the top transistor is P-type Te; in the step (2), when the active layer thin film of the bottom transistor is P-type Te, corresponding to the step (4), the active layer thin film of the top transistor is N-type TMDs; thereby forming TMDS and P-type simple substance Te complementary type three-dimensional CMOS devices.
3. The manufacturing method according to claim 2, wherein in the step (1), the device substrate is a silicon wafer of a thin silicon oxide layer, sapphire, quartz, glass, polymer or plastic; selecting according to the type of a transistor in a CMOS structure to be prepared, and when a bottom transistor is a back gate or a buried gate transistor, adopting a silicon wafer containing a silicon oxide thin layer, sapphire or quartz as a substrate; when the bottom layer transistor is a top gate transistor, any of the materials described above is used as the substrate.
4. The method according to claim 3, wherein in the step (1), the substrate cleaning is to remove impurities and dust remaining on the surface of the substrate during processing, transportation, storage and use; cleaning the substrate by ultrasonic cleaning of an organic solvent, dilute acid alkali liquor and deionized water;
the pretreatment of the substrate is to treat the substrate in the modes of baking or heating by an oven or a constant-temperature heating table, plasma treatment or spin-coating of photoresist, coating and the like so as to enhance the adhesion between the substrate and a device and reduce the roughness of the surface of the substrate; the alignment mark is used for facilitating accurate alignment among various processes in the device manufacturing process.
5. The method according to claim 2, wherein in the step (2), the N-type TMDs film is mechanically peeled to obtain the two-dimensional atomic crystal thin film material with a smaller area, or is prepared by a chemical vapor deposition method or a physical vapor deposition method to obtain the two-dimensional atomic crystal thin film material with a larger area; or transferring the TMDS film to a target substrate by adopting a dry method and a wet method according to the substrate and the film;
the TMDS film material is MoS2、WS2、Bi2S3ZnS or CdS;
the P-type simple substance hoof is a simple substance Te film with the thickness of less than 100nm formed by conventional photoetching at the temperature of minus 80 ℃ or a hard mask plate through thermal evaporation.
6. The production method according to claim 5, wherein in the step (2):
the maskless photoetching adopts equipment such as electron beam photoetching, laser direct writing and the like;
the etching is mainly used for etching the two-dimensional transition metal chalcogenide TMDS and the connecting through hole between the devices; etching TMDs by using a reactive plasma containing F + gas, plasma etching or dry etching of an inductively coupled plasma etching device, wherein the through hole etching adopts dry etching and wet etching;
the film deposition is to deposit a film by using a thermal evaporation mode, an electron beam evaporation mode, an atomic layer deposition mode, a magnetron sputtering mode or a physical vapor deposition mode, so that a metal electrode, a connecting through hole and an insulating layer of a bottom layer transistor are prepared.
7. The method of claim 2, wherein the oxide protective layer in step (4) is in accordance with the oxide spacer preparation method.
8. The method of one of claims 1-7, wherein the bottom layer transistor and the top layer transistor are top and bottom gate transistors, buried gate transistors, and wrap gate transistors.
9. The manufacturing method according to one of claims 1 to 7, wherein the transistors of the bottom layer transistor and the top layer transistor are gated by the same gate, i.e. common gate.
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