CN111446288B - NS (non-volatile) stacked transistor based on two-dimensional material and preparation method thereof - Google Patents
NS (non-volatile) stacked transistor based on two-dimensional material and preparation method thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to an NS (non-volatile storage) stacked transistor based on a two-dimensional material and a preparation method thereof. The NS stacked transistor consists of two or more two-dimensional active layers, three or more graphene or metal grid stacked common gates. The preparation method comprises the steps of preparing a silicon/silicon dioxide buried gate; preparing a two-dimensional material on a silicon/silicon dioxide substrate; preparing a graphene or metal electrode which is not connected with the two-dimensional material; oxidizing or selectively etching the two-dimensional material and selectively etching the metal electrode; preparing a metal electrode in contact with the edge of the two-dimensional material and a connecting electrode in contact with the metal electrode. The invention provides a novel transistor structure of a two-dimensional material, which not only solves the problem of short channel effect of a silicon-based transistor under a very small scale, but also can adapt to an advanced process technology below 5nm, and provides a foundation for the application of the two-dimensional material in the advanced process of an integrated circuit.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a Nanoshiet (NS) laminated transistor based on a two-dimensional material and a preparation method thereof.
Background
The continuation of moore's law and the rise of the electronics industry such as cell phones not only bring great improvements to the Integrated Circuit (ICs) industry, but also bring more challenges, especially when the MOSFET size is reduced below 10nm, the short channel effect and the consequent increase of off-state current become one of the biggest challenges. Many researches have been made on the field effect transistor (FINFET), junction-FET, and Gate-all-around (gaa) FET, which are characterized by enhanced Gate control and can suppress short channel effect to some extent. In the 2020 integrated circuit process blueprint predicted by the world authority IMEC, processes of 3nm and below recommend NS stacked devices using GAA structures and CFET devices with differently doped NS stacks, demonstrating that NS stacked devices can be efficiently adapted to advanced integrated circuit node processes.
Representative examples thereof since graphene discovery include transition metal disulfides (TMDs, such as MoS)2，WSe2Etc.), Black Phosphorus (BP), etc., have been widely studied and are receiving increasing attention. Due to the inherent interlayer structure without dangling bonds and high theoretical mobility of the two-dimensional material, and the transistor prepared based on the two-dimensional material has extremely high on-off ratio, the two-dimensional material replaces the traditional germanium-silicon material to form one of hot gate materials for effectively solving the short channel effect. In MoS2For example, a detached monolayer MoS2Thin film FET mobility in excess of 200 cm2V-1s-1On-off ratio of more than 107(ii) a In the Sub-5nm level device, the theoretical characteristics better than Si are presented; experimentally (1 nm-MoS)2-FET) also demonstrated MoS compared to Si2There is better gate leakage and lower intralevel dielectric constant at ultra-small dimensions. The above properties result in two-dimensional materials (e.g., MoS) with superior performance2、WS2、WSe2Etc.) become a strong candidate for Sub-5nm channel materials.
Currently for MoS2The multi-gate and gate-all-around transistors have been prepared from these two-dimensional materials, but there has been no research on the transistors of the NS stack, nor transistor protodevices that can be integrated in advanced integrated circuit processes. The multi-channel common-gate surrounding gate type transistor prepared by the invention not only effectively increases the on-state current of the transistor and inhibits off-state electric leakage, but also has mature and repeatable preparation process, can realize large-scale circuit integration of two-dimensional materials, and can become one of the selection schemes of the next generation integrated circuit process.
Disclosure of Invention
The invention aims to provide a NS (negative-positive-negative) stacked transistor based on a two-dimensional material and a preparation method thereof, so as to solve the problems of short channel effect of the traditional silicon process under a very small scale and the adaptation of the two-dimensional material in an advanced process.
The NS (nanosheet) laminated transistor based on the two-dimensional material is formed by stacking and sharing gates by taking two or more layers of two-dimensional materials as active layers and three or more layers of graphene or metal as gates. The NS laminated transistor based on the two-dimensional material can be used for preparing an inverter with a CMOS basic structure, so that a complex large-scale digital logic circuit and functions of other analog circuits and radio frequency analog circuits are realized.
The two-dimensional material is 1-15 atomic layers of material, including but not limited to MoS2Black Phosphorus (BP), MoSe2、MoTe2、WS2And WSe2And the like.
The invention relates to a preparation method of an NS (non-volatile semiconductor) stacked transistor based on a two-dimensional material, which comprises the steps of preparing a buried gate on an insulating substrate; two-dimensional material growth or transfer on an insulating substrate; deposition of graphene or metal gate electrodes; oxidizing or selectively etching the semiconductor two-dimensional material; selectively etching the gate electrode; preparing a metal electrode in contact with the edge of the semiconductor two-dimensional material, and preparing a metal electrode in contact with the edge of the gate electrode. The method comprises the following specific steps.
(1) Determining the position of a buried gate on a silicon/silicon dioxide substrate by a photoetching or masking method, depositing to form a buried gate electrode (the material is two-dimensional graphene or conductive materials such as metal), and etching the reserved thickness of the electrode by using a dry etching method if the buried gate electrode is a metal electrode, so as to ensure the surface flatness after the electrode is formed.
(2) Depositing a medium (the material is oxide or two-dimensional boron nitride and other insulating materials) interlayer on the buried gate;
in the invention, the buried gate, the two-dimensional material and the dielectric spacer between the gate electrodes include but are not limited to silicon oxide (SiO)2) Two-dimensional Boron Nitride (BN), zirconium oxide (ZrO)2) Hafnium oxide (HfO)2) Alumina (Al)2O3）、SixCyOz、SixByCzNkThe dielectric material can also be other high-K dielectric materials or BN-like two-dimensional insulating materials and is prepared by adopting a Thermal Evaporation (TE), Electron Beam Evaporation (EBE), Atomic Layer Deposition (ALD) or Molecular Beam Epitaxy (MBE) method.
(3) Preparing a layer of semiconductor two-dimensional material on the buried gate interlayer, and depositing a layer of medium (oxide or two-dimensional boron nitride and other insulating materials) interlayer;
the semiconductor two-dimensional material is formed by physical vapor deposition, chemical vapor deposition, metal organic compound chemical vapor deposition, molecular beam epitaxy or atomic layer deposition; or stripping the grown two-dimensional material wafer from the metal or insulator substrate and transferring the two-dimensional material wafer to a target substrate by a dry method or a wet method; or mechanically stripping the two-dimensional material block to obtain a two-dimensional atomic crystal thin film material, and transferring the two-dimensional atomic crystal thin film material to a target substrate by a dry method; the method and the equipment for transferring the large-area thin-film material can refer to a patent of a transfer platform for transferring the large-area two-dimensional material under a vacuum environment (CN 201820102682).
(4) Preparing a layer of gate electrode (made of two-dimensional graphene electrode or metal and other conductive materials) on the two-dimensional material interlayer, and then depositing a layer of medium interlayer on the gate electrode;
the gate electrode material includes, but is not limited to, two-dimensional graphene, Au, Ag, Pt, Al, Ti, or Cr;
if the gate electrode is a graphene gate electrode, the forming method is chemical vapor deposition, metal organic compound chemical vapor deposition, molecular beam epitaxy or atomic layer deposition; or stripping the grown graphene wafer from the metal or insulator substrate of the graphene wafer and transferring the graphene wafer to a target substrate by a dry method or a wet method; if the gate electrode is a metal gate electrode, the gate electrode is formed by adopting a method of ultraviolet, electron beam lithography or hard mask, and the method comprises the following steps: making a mask of a required pattern on the metal precursor layer; and depositing the metal electrode by physical vapor deposition, electron beam evaporation or magnetron sputtering and other equipment.
(5) And (5) repeating the step (3) and the step (4), and preparing the two-dimensional material-gate dielectric-gate electrode-gate dielectric laminated structure, wherein the repetition frequency is more than two times (determined according to actual needs).
(6) Etching the shape of the channel on the basis of the film material with the periodic structure; firstly, etching two parallel edges of a channel of the NS stacked transistor in the direction parallel to the electrode by using dry etching, and stopping etching until a substrate is etched; etching the exposed gate electrode by using selective wet etching; then depositing a contact electrode in edge contact with the multilayer semiconductor two-dimensional material, thereby connecting the multilayer channels of the NS stacked transistor;
the etching is used for etching two-dimensional materials, oxide interlayers and graphene or metal electrodes, and F is adopted+Dry etching such as reactive plasma etching (RIE), Plasma Etching (PE) or inductively coupled plasma etching (ICP); the selective etching of the graphene uses H+、He+、Ar+、O2Carrying out plasma dry etching or carrying out wet etching by adding a hydrochloric acid solution into ferrocene; the selective etching of the metal electrode uses H3PO4、HNO3、HF、NH4F, carrying out wet etching on one or more solutions;
the two-dimensional material contact electrode is made of metal materials including but not limited to Au, Ag, Pt, Ni, Ti or Cr, and can be other low work function metals.
(7) Etching the other two parallel edges of the channel of the NS laminated transistor in the direction vertical to the electrode by using dry etching, and etching the exposed edge of the semiconductor two-dimensional material by using a selective wet etching method; or oxidizing the exposed edges of the semiconductor two-dimensional material to insulate the semiconductor two-dimensional material; metal electrodes are then deposited in contact with the edges of the multi-layer gate electrodes to connect the multi-layer gate electrodes of the NS stack transistor.
In the invention, the two-dimensional material edge oxidation can use O2Or O3Natural oxidation or annealing treatment is carried out in an annealing furnace under the oxygen environment; the selective wet etching of the two-dimensional material is suitable according to specific materialsAnd etching agent.
In the invention, the grids of the transistors in several layers are connected through the same metal connecting layer, namely the common-grid type surrounding grid transistor; the buried gate electrode and the metal connecting layer are made of metal materials including, but not limited to, Au, Ag, Pt, Al, Ti or Cr.
The invention provides a novel nanoshiet laminated transistor device based on a two-dimensional material, a multi-channel common-gate surrounding gate type transistor can be prepared through photoetching, the preparation process is easy to copy, and the nanoshiet laminated transistor device has the advantages of solving the short-channel effect, improving the integration level, reducing the power consumption and adapting to an advanced process.
Drawings
Fig. 1 is a schematic illustration of forming a buried gate electrode.
Fig. 2 is a schematic diagram of forming a first layer of transistors.
Fig. 3 is a schematic diagram of forming a second layer of transistors.
Fig. 4 is a schematic diagram after etching along the gate parallel direction.
Fig. 5 is a schematic view after growing a channel contact electrode.
Fig. 6 is a schematic diagram after etching along the vertical direction of the gate.
Fig. 7 is a schematic view of the completed device after the gate connection layer metal is grown.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The invention is illustrated in the accompanying drawings by way of example and with reference to the accompanying figures, which illustrate the method of fabricating a thin film transistor device by photolithographic etching in accordance with the present invention. Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar materials throughout, or methods of having the same or similar functions. The specific embodiments described herein are merely illustrative of the present invention and do not limit the scope of the invention. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the applicability of other processes and/or the use of other materials.
Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings.
Examples
MoS2NS stacked gate-all transistor fabrication
(1) Preparing a buried gate, and respectively ultrasonically cleaning Si/SiO by sequentially using acetone, isopropanol and deionized water2Substrate, laser direct-writing photoetching to form buried gate electrode and pattern as alignment mark, and SF6Etching a 35nm groove in ICP equipment by using gas, plating Au with the same thickness and liftoff by using electron beam evaporation equipment, and finally depositing a layer of hafnium oxide (20 nm) on a substrate by using Atomic Layer Deposition (ALD) equipment to be used as a gate dielectric layer of a transistor;
(2) preparation of transistor channel and gate, wherein prepared MoS is prepared by single-layer Chemical Vapor Deposition (CVD) with metal Au as gate electrode2A double-layer channel three-layer grid laminated transistor with a film as a channel; firstly, adopting large-area dry transfer equipment to prepare MoS on silicon wafer by CVD2Accurate transfer of thin film to HfO with well-prepared buried gate2On the gate dielectric layer, the specific transfer method and equipment can refer to a patent of a transfer platform for transferring large-area two-dimensional materials in a vacuum environment (CN 201820102682); respectively preparing 2nm SiO by using electron beam evaporation equipment2And Al2O3As a seed layer of a gate dielectric, prepare 20nm HfO using ALD2The grid dielectric layer is used as a first layer of transistor; evaporation of 5nmAu using an electron beam evaporation device, preparation of a layer of 20nm HfO using ALD2The protective layer is used as a protective layer of the grid electrode of the first layer of transistor, and simultaneously can also be used as a back gate dielectric layer for regulating and controlling the second layer of transistor; accurate transfer of a second layer of MoS using the large area dry transfer apparatus described above2Applying a thin film on the first transistor protective layer, and respectively preparing SiO 2nm by using an electron beam evaporation device2And Al2O3As a seed layer of the gate dielectric, prepare HfO of 20nm using ALD2The grid medium layer is used as a second layer of transistor; evaporating 5nmAu by using an electron beam evaporation device;
(3) transistor bulk lithographyEtching, connection of a contact electrode, and connection of a gate electrode; exposing the etched region parallel to the electrode direction by laser direct writing, using a solution containing SF6Etching two parallel sides of a channel of the NS stacked transistor in a direction parallel to the electrode by using gas ICP (inductively coupled plasma) until the substrate stops, selectively etching the exposed gate electrode by using an HF (hydrogen fluoride) solution in a wet method, and performing laser direct writing exposure and MoS (Mos) after liftoff2Edge-contacted electrode shape, growing 40nmAu as contact electrode using electron beam evaporation equipment and liftoff; exposing the etched region in the direction perpendicular to the electrode by laser direct writing, using a solution containing SF6Etching the channel width of the NS stacked transistor in the direction vertical to the electrode by ICP of gas to the depth of the channel width until contacting the buried gate electrode, and using O-containing material2Annealing furnace heated to 100 ℃ oxidizes exposed MoS2Exposing the shape of the grid connecting layer by using laser direct writing after liftoff, and depositing 40nm Au as the connecting layer of the grid by using electron beam evaporation equipment; finally, ALD can be used to grow a layer of 20nm HfO2As a protective layer.
Claims (8)
1. The preparation method of the NS stacked transistor based on the two-dimensional material is characterized in that the NS stacked transistor is formed by taking two or more layers of two-dimensional materials as active layers and taking three or more layers of graphene or metal as grid electrode stacking common grid; the two-dimensional material is 1-15 atomic layers of material; the two-dimensional material is MoS2Black phosphorus, MoSe2、MoTe2、WS2Or WSe2(ii) a The preparation method comprises the following steps: preparing a buried gate on an insulating substrate; two-dimensional material growth or transfer on an insulating substrate; deposition of graphene or metal gate electrodes; oxidizing or selectively etching the semiconductor two-dimensional material; selectively etching the gate electrode; the preparation of the metal electrode in contact with the edge of the semiconductor two-dimensional material and the preparation of the metal electrode in contact with the edge of the gate electrode comprise the following steps:
(1) determining the position of a buried gate on a silicon or silicon dioxide substrate by a photoetching or masking method, depositing to form a buried gate electrode, wherein a gate electrode material is two-dimensional graphene or a metal conductive material, and for the metal electrode, firstly, etching by a dry method to obtain the reserved thickness of the electrode, so as to ensure the surface flatness after the electrode is formed;
(2) depositing a dielectric interlayer on the buried gate electrode;
(3) preparing a layer of semiconductor two-dimensional material on the buried gate interlayer, and depositing a layer of medium interlayer on the semiconductor two-dimensional material;
(4) preparing a layer of gate electrode on the two-dimensional material interlayer, wherein the gate electrode is made of two-dimensional graphene or metal conductive material, and then depositing a layer of medium interlayer on the gate electrode;
(5) repeating the preparation of the two-dimensional material-gate dielectric-gate electrode-gate dielectric laminated structure in the step (3) and the step (4) for more than two times;
(6) etching the shape of the channel on the basis of the film material with the periodic structure; firstly, etching two parallel edges of a channel of the NS stacked transistor in the direction parallel to the electrode by using dry etching, and stopping etching until a substrate is etched; then, etching the exposed gate electrode by utilizing selective wet etching; then depositing a metal electrode in contact with the edges of the multilayer semiconductor two-dimensional material, thereby connecting the multilayer channels of the NS stacked transistor;
(7) etching the other two parallel edges of the channel of the NS stacked transistor in the direction vertical to the electrode by dry etching, and oxidizing the exposed edge of the two-dimensional semiconductor material to insulate the two-dimensional semiconductor material, or etching the exposed edge of the two-dimensional semiconductor material by a selective wet etching method; metal electrodes are then deposited in contact with the edges of the multi-layer gate electrodes to connect the multi-layer gate electrodes of the NS stack transistor.
2. The method of claim 1, wherein the dielectric spacer material used for the semiconductor two-dimensional material and the gate electrode in steps (2) - (4) is selected from two-dimensional boron nitride, silicon oxide, zirconium oxide, hafnium oxide, aluminum oxide, Si, and mixtures thereofxCyOz、SixByCzNkOr other high K dielectric material or BN-like two-dimensional insulating material.
3. The method of claim 1, wherein the metal gate electrode material of steps (1) and (4) is selected from Au, Ag, Pt, Ni, Ti, and Cr.
4. The method of claim 1, wherein the gate electrode is formed by chemical vapor deposition, metal organic chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition; or stripping the grown graphene wafer from the metal or insulator substrate of the graphene wafer and transferring the graphene wafer to a target substrate by a dry method or a wet method; in the case of using metal for the gate electrode, the gate electrode is prepared by using methods such as ultraviolet, electron beam lithography or hard mask, and the like, and the method comprises the steps of making a mask with a required pattern on the metal precursor layer, and depositing the metal electrode by physical vapor deposition, electron beam evaporation or magnetron sputtering equipment.
5. The method of claim 1, wherein the dry etching in steps (1), (6) and (7) is F-containing+Reactive plasma etching, plasma etching or inductively coupled plasma etching; the selective etching of the graphene is performed by using H+、He+、Ar+Or O2Carrying out plasma dry etching or carrying out wet etching by adding a hydrochloric acid solution into ferrocene; the selective etching of the metal electrode is performed by using H3PO4、HNO3、HF、NH4F, carrying out wet etching on one or more solutions; the two-dimensional material contact electrode is made of metal materials selected from Au, Ag, Pt, Ni, Ti or Cr.
6. The method of claim 1, wherein the step (7) of edge oxidation of the exposed two-dimensional semiconductor material is performed by using O2Or O3Naturally oxidized, or in annealing furnacesAnd annealing treatment is carried out in an oxygen environment.
7. The method of claim 1, wherein the stacked transistor gates are connected by a single metal interconnect layer, i.e., a common gate pass-gate transistor; the buried gate electrode and the metal connecting layer are made of metal materials selected from Au, Ag, Pt, Al, Ti or Cr.
8. A NS stacked transistor based on two-dimensional material obtained by the manufacturing method according to any one of claims 1 to 7.
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