CN114242780A - Indium tin oxide vertical ring grid field effect transistor and preparation method thereof - Google Patents
Indium tin oxide vertical ring grid field effect transistor and preparation method thereof Download PDFInfo
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 238000002360 preparation method Methods 0.000 title abstract description 12
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 32
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
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- 125000006850 spacer group Chemical group 0.000 claims description 4
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- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 3
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- 229910000167 hafnon Inorganic materials 0.000 claims description 2
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- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The invention discloses an indium tin oxide vertical ring gate field effect transistor and a preparation method thereof. The field effect transistor is of a vertical ring-grid structure and comprises an insulating substrate, wherein a drain electrode, an indium tin oxide channel layer with a large height-width ratio and a source electrode are sequentially stacked on the insulating substrate from bottom to top, and the indium tin oxide channel layer is surrounded and coated by a high-kappa grid dielectric layer and a grid electrode to form a ring-grid structure. The indium tin oxide channel is surrounded by the ring gate, the gate control capability is enhanced, the short channel effect can be better inhibited, the process node is further promoted, the limitation on the gate length and the source-drain contact area is smaller compared with a planar ring gate, the whole process thermal budget is within 300 ℃, and three-dimensional stacking can be carried out, so the integration density is effectively improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an indium tin oxide vertical ring gate field effect transistor and a preparation method thereof.
Background
As transistor sizes become smaller, short channel effects of MOSFETs become more severe, preventing further device feature size scaling. In order to suppress the short channel effect, the moore' S law is continued, and researchers propose various solutions, such as finfets and multi-gate structure devices like double-gate, triple-gate, pi-gate, S-gate, omega-gate, and gate-all-around. With the advance of new process nodes to the nanometer level, the aspect ratio of the Fin structure needs to be increased to improve the performance of the device, and the Fin is difficult to maintain in an upright state due to the internal stress of the material, so that new challenges are brought to the micro-nano processing process. In multi-gate devices, gate-all-around field effect transistors (GAAFETs) have become the most competitive alternative to Fin FET structures due to their superior gate control capabilities and compatibility with Fin FET fabrication process technologies. The channel materials of the gate-all-around field effect transistor comprise nanowires, nanotubes, nanosheets and the like, and all face the difficult problems of material preparation and device manufacturing process difficulty. Recent studies have shown that ITO transistors can better overcome short channel effects. Moreover, the preparation process of the ITO material is completely compatible with the existing mainstream thin film growth process, and the preparation process of the ITO GAA FET device is also completely compatible with the CMOS process, so that the ITO can be the most potential semiconductor channel material for large-scale production of GAAFET. GAA FETs can be classified into planar and vertical structures depending on the orientation of the channel. The former can increase the drive current per active area by stacking channels in multiple layers in the vertical direction. The latter has a smaller occupied area of a single device due to the adoption of a channel material with a large height-width ratio, and has a larger potential in improving the integration density.
Disclosure of Invention
The invention aims to provide an indium tin oxide vertical type ring gate field effect transistor and a preparation method thereof, wherein a channel material is indium tin oxide, a channel is completely surrounded by a gate, a gate medium is made of a high-k material, and the indium tin oxide vertical type ring gate field effect transistor has excellent gate control capability and can better inhibit a short channel effect.
Specifically, the technical scheme of the invention is as follows: a field effect transistor is a vertical ring gate structure and comprises an insulating substrate, wherein a drain electrode, an indium tin oxide channel layer with a large height-width ratio and a source electrode are sequentially stacked on the insulating substrate from bottom to top, and the indium tin oxide channel layer is surrounded and coated by a high-kappa gate dielectric layer and a gate electrode to form a ring gate structure.
Furthermore, the field effect transistor is provided with an isolating layer between the gate electrode and the source electrode to prevent the short circuit between the gate electrode and the source electrode. The isolation layer is preferably a low-k dielectric material, and SiO can be adopted2Or SiNxAn insulating material.
In the field effect transistor, the insulating substrate may be a high-resistance silicon substrate whose surface is a silicon dioxide layer, or may be another insulating substrate such as a high-resistance silicon, silicon carbide, diamond, or sapphire substrate.
In the field effect transistor, the aspect ratio of the indium tin oxide channel layer is preferably 3:1 to 8:1, and the thickness (i.e. height) is preferably 5 to 50 nm.
In the above field effect transistor, the drain electrode and the source electrode are preferably Ni/Au metal composite layer electrodes, and Au, Ni/Pt.
In the field effect transistor, the high-k gate dielectric layer is a high-k dielectric material, such as HfO2、HfSiO4、Si3N4、La2O5、ZrO2And the like. The thickness of the gate dielectric layer surrounding the indium tin oxide channel layer (i.e., the channel to gate electrode spacing) is preferably 2-10 nm.
In the field effect transistor, the gate electrode is preferably made of W, Au, Pt, TiN, or Ni.
The invention also provides a preparation method of the field effect transistor, which comprises the following steps:
1) cleaning the insulating substrate;
2) preparing a drain electrode on an insulating substrate;
3) preparing an indium tin oxide channel layer with a large height-width ratio on the drain electrode;
4) depositing a high-k dielectric material to form a gate dielectric layer coating the indium tin oxide channel layer;
5) growing a gate electrode layer on the gate dielectric layer;
6) depositing a low-k dielectric material on the gate electrode layer to form an isolation layer;
7) defining an etching area by adopting electron beam lithography, removing the isolation layer and the gate electrode layer on the top by adopting dry etching to expose the top of the channel layer and form a ring gate electrode, and then removing the photoresist mask;
8) depositing a low-k dielectric material as an insulating isolation layer of the top source electrode and the gate all around electrode;
9) defining an etching area by adopting electron beam lithography, removing part of the isolation layer by adopting dry etching, and exposing the top of the channel layer and the test areas of the drain electrode and the gate electrode;
10) and preparing a source electrode on the top of the indium tin oxide channel layer.
In all the above steps, the lithographic definition of the image is preferably performed by an electron beam lithography process.
In the step 3), the indium tin oxide channel layer is preferably prepared by magnetron sputtering.
In the step 4), the high- κ dielectric material is preferably deposited by atomic layer deposition.
In the step 5), the TiN gate electrode layer is preferably grown on the whole surface by atomic layer deposition.
In step 6) and step 8) above, the low- κ insulating material is preferably deposited by plasma-enhanced chemical vapor deposition.
In the step 7) and the step 9), the dry etching is preferably dry etching using inductively coupled plasma.
And in the step 2) and the step 10), the drain electrode and the source electrode are respectively prepared by evaporating metal by adopting an electron beam.
Compared with the prior art, the invention has the following beneficial effects:
1. the growth of indium tin oxide and the device preparation process are completely compatible with the existing silicon-based CMOS process, and the volume production potential is huge;
2. the indium tin oxide channel material has low price and simple acquisition mode, can be subjected to large-scale uniform deposition, and meets the requirements of large-area integrated circuits;
3. the indium tin oxide channel is surrounded by the ring gate, the gate control capability is enhanced, the short channel effect can be better inhibited, the process node is further promoted, the limitation on the gate length and the source-drain contact area is smaller compared with a planar ring gate, the whole process thermal budget is within 300 ℃, and three-dimensional stacking can be carried out, so the integration density is effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of an ito vertical-type mosfet, wherein: 1 is a high-resistance silicon substrate, 2 is a silicon dioxide layer, 3 is a drain electrode, 4 is an indium tin oxide channel layer, 5 is a high-kappa gate dielectric layer, 6 is a gate electrode, 7 is a first isolation layer, 8 is a second isolation layer, 9 is a source electrode, and the indium tin oxide channel layer 4 is surrounded and coated by the high-kappa gate dielectric layer 5 and the gate electrode 6 to form a ring gate structure.
FIG. 2 is a schematic diagram of the process steps for fabricating an ITO vertical gate all-around FET in an embodiment, wherein: step1, cleaning the high-resistance silicon substrate with silicon dioxide on the surface; step 2, preparing a drain electrode by adopting processes of electron beam exposure, development, electron beam metal evaporation, stripping and the like; step 3, defining an indium tin oxide channel region by adopting processes such as electron beam exposure, development and the like, growing an indium tin oxide layer by adopting a magnetron sputtering process, and stripping; step 4, growing a high-temperature grid dielectric layer by adopting an atomic layer deposition process, and surrounding an indium tin oxide channel; step 5, growing a gate electrode layer by adopting an atomic layer deposition process; step 6, depositing a low-k dielectric isolation layer by plasma enhanced chemical vapor deposition; step 7, defining an etching area through electron beam exposure and development, removing the isolation layer and the gate electrode layer on the top of the channel by adopting dry etching, and removing the photoresist mask; step 8, depositing a low-k dielectric isolation layer again through plasma enhanced chemical vapor deposition to prevent the gate electrode and the source electrode from being connected and shorted; step 9, defining a window area by using electron beam exposure, and removing an isolation layer on a channel by adopting plasma dry etching; and Step 10, preparing the source electrode by adopting processes of electron beam exposure, development, electron beam metal evaporation, stripping and the like.
Detailed Description
In order to make the content of the present invention more comprehensible, the technical solutions of the present invention are further described below by referring to the accompanying drawings, but the following embodiments are only an example of the present invention and do not represent the scope of the present invention defined by the claims, and the scope of the present invention is subject to the claims.
The structure of the ito vertical ring-gate fet of this embodiment is shown in fig. 1, and includes a high-resistance silicon substrate 1 and a silicon dioxide layer 2 thereon, a drain electrode 3, an ito channel layer 4 with a large aspect ratio, and a source electrode 9 are sequentially stacked on the silicon dioxide layer 2, and the ito channel layer 4 is surrounded and coated by a high- κ gate dielectric layer 5 and a gate electrode 6 to form a ring-gate structure; between the gate electrode 6 and the source electrode is a first spacer 7 and a second spacer 8 to prevent short circuits. The preparation steps of the transistor are shown in fig. 2, and comprise:
step 1: selecting a high-resistance Si (110) substrate with SiO 90nm thick on the surface2A standard RCA1 cleaning process is used to remove particles, organics, etc. from the substrate. And after cleaning, blowing the high-purity nitrogen for later use.
Step 2: the preparation of the drain electrode comprises the process steps of glue homogenizing, baking, exposure, development, metal evaporation, stripping and the like. (1) Firstly, spin-coating PMMA electron beam glue on the basis of the step1, wherein the spin-coating parameters are 3000rpm/60s, and baking the glue for 90s at 180 ℃ after spin-coating; (2) defining a drain electrode area by adopting a Raith 150 electron beam exposure system, namely, modifying electron beam glue in the exposed area; (3) and (3) developing: developing liquid is MIBK, IPA is 1:3, the developing time is 50s, IPA is fixed for 50s, nitrogen is dried, the denatured glue in an exposure area is dissolved in the developing liquid and the glue in a non-exposure area is reserved, and a layout graph is transferred to a sample wafer; (4) oxygen plasma cleaning: the ratio of argon to oxygen is 4:1, the power is 30W, the processing time is 2min, and the electron beam glue remained after the exposure and development process is removed; (5) and (3) evaporating a metal electrode: evaporating and evaporating 5nm Ni and 25nm Au by adopting an electron beam as drain electrodes; (6) stripping metal: soaking in acetone at 55 deg.C for 30min, dissolving the glue in acetone to remove the metal from the sample surface, washing off the excess metal, cleaning in IPA for 1min to remove acetone, and blowing with nitrogen gas.
And 3, step 3: preparing the indium tin oxide channel, including the process steps of glue homogenizing, baking, exposure, development, magnetron sputtering, stripping and the like. (1) Firstly, spin-coating PMMA electron beam glue on the basis of the step 2, wherein the spin-coating parameters are 3000rpm/60s, and baking the glue for 90s at 180 ℃ after spin-coating; (2) defining a channel region by adopting a Raith 150 electron beam exposure system, namely modifying electron beam glue in the exposure region; (3) and (3) developing: developing liquid is MIBK, IPA is 1:3, the developing time is 50s, IPA is fixed for 50s, nitrogen is dried, the denatured glue in an exposure area is dissolved in the developing liquid and the glue in a non-exposure area is reserved, and a layout graph is transferred to a sample wafer; (4) oxygen plasma cleaning: the ratio of argon to oxygen is 4:1, the power is 30W, the processing time is 2min, and the electron beam glue remained after the exposure and development process is removed; (5) magnetron sputtering: preparing an indium tin oxide layer with the thickness of 5-50 nm by adopting radio frequency magnetron sputtering; (6) stripping: soaking in NMP at 80 deg.C for 2h, dissolving the glue in acetone to remove indium tin oxide from the sample surface, washing off the excess part, washing with IPA for 1min to remove acetone, and blowing with nitrogen gas. At this time, the indium tin oxide channel layer is completed.
And 4, step 4: preparing a gate dielectric, and growing a high-k dielectric HfO with the thickness of 5nm on the surface of the sample by using an atomic layer deposition system on the basis of the step 32As a gate dielectric layer. TEMAHf and O are adopted during the growth of the gate dielectric layer3As a precursor, the growth temperature was 250 ℃.
And 5, step 5: and (4) depositing a gate electrode layer, and using 30nm TiN deposited by an atomic layer as the gate electrode layer on the basis of the step (4), wherein the sidewall coverage of the atomic layer deposition is superior to that of electron beam evaporation and magnetron sputtering, so that the gate electrode is more suitable for preparing a gate-all-around electrode.
And 6, step 6: preparing a first isolation layer, and depositing SiO with a thickness of 100nm by plasma enhanced chemical vapor deposition based on the step 52Or SiNxThe insulating material acts as an isolation layer.
And 7, step 7: and windowing the top of the channel, wherein the windowing comprises the process steps of glue homogenizing, baking, exposing, etching, mask removing and the like. (1) Spin-coating a mask ARP electron beam glue on the basis of the step 6, wherein the spin-coating parameter is 4000rpm/60s, and baking the glue for 60s at 150 ℃; (2) defining an etching area by adopting a Raith 150 electron beam exposure system, namely modifying electron beam glue in the exposure area; (3) and (3) developing: the developing solution is MIBK, the developing time is 60s, IPA fixing is carried out for 30s, nitrogen is blown dry, at the moment, denatured glue in an exposure area is dissolved in the developing solution, glue in a non-exposure area is reserved, and a layout graph is transferred to a sample; (4) oxygen plasma cleaning: the ratio of argon to oxygen is 4:1, the power is 30W, the processing time is 2min, and the electron beam glue remained after the exposure and development process is removed; (5) etching and removing the isolation layer and the gate electrode layer at the top of the channel by using an inductively coupled plasma etching machine to form a ring gate electrode; (6) and (3) carrying out hot bath in a photoresist removing liquid NMP at 80 ℃ for 1 hour to remove the ARP photoresist, finally cleaning in IPA for 2min, and drying by nitrogen.
And 8, step 8: preparing a second isolation layer, and depositing SiO with a thickness of 100nm by plasma enhanced chemical vapor deposition on the basis of the step 72Or SiNxThe insulating material is used as an isolation layer to avoid direct contact short circuit between the gate-all-around electrode and the top source electrode.
Step 9: and windowing the top of the channel and the test electrode, wherein the windowing comprises the process steps of glue homogenizing, baking, exposing, etching, mask removing and the like. (1) Spin-coating a mask ARP electron beam glue on the basis of the step 8, wherein the spin-coating parameter is 4000rpm/60s, and baking the glue for 60s at 150 ℃; (2) defining an etching area by adopting a Raith 150 electron beam exposure system, namely modifying electron beam glue in the exposure area; (3) and (3) developing: the developing solution is MIBK, the developing time is 60s, IPA fixing is carried out for 30s, nitrogen is blown dry, at the moment, denatured glue in an exposure area is dissolved in the developing solution, glue in a non-exposure area is reserved, and a layout graph is transferred to a sample; (4) oxygen plasma cleaning: the ratio of argon to oxygen is 4:1, the power is 30W, the processing time is 2min, and the electron beam glue remained after the exposure and development process is removed; (5) etching and removing the isolation layers on the top of the channel, the gate electrode and the drain electrode test area by using an inductively coupled plasma etching machine; (6) and (3) carrying out hot bath in a photoresist removing liquid NMP at 80 ℃ for 1 hour to remove the ARP photoresist, finally cleaning in IPA for 2min, and drying by nitrogen.
Step 10: preparing a source electrode, and comprises the process steps of glue homogenizing, baking, exposure, development, metal evaporation, stripping and the like. (1) Spin-coating PMMA electron beam glue with the spin-coating parameter of 3000rpm/60s, and baking for 90s at 180 ℃ after spin-coating; (2) defining a source electrode area by adopting a Raith 150 electron beam exposure system, namely electron beam gel modification of the exposure area; (3) and (3) developing: developing liquid is MIBK, IPA is 1:3, the developing time is 50s, IPA is fixed for 50s, nitrogen is dried, the denatured glue in an exposure area is dissolved in the developing liquid and the glue in a non-exposure area is reserved, and a layout graph is transferred to a sample wafer; (4) oxygen plasma cleaning: the ratio of argon to oxygen is 4:1, the power is 30W, the processing time is 2min, and the electron beam glue remained after the exposure and development process is removed; (5) and (3) evaporating a metal electrode: evaporating and evaporating 20nm Ni and 40nm Au by adopting an electron beam as source electrodes; (6) stripping metal: soaking in acetone at 55 deg.C for 30min, dissolving the glue in acetone, removing the excess metal, washing in IPA for 1min to remove acetone, and blowing with nitrogen gas.
Claims (10)
1. A field effect transistor is a vertical ring gate structure and comprises an insulating substrate, wherein a drain electrode, an indium tin oxide channel layer with a large height-width ratio and a source electrode are sequentially stacked on the insulating substrate from bottom to top, and the indium tin oxide channel layer is surrounded and coated by a high-kappa gate dielectric layer and a gate electrode to form a ring gate structure.
2. The field effect transistor of claim 1 wherein a spacer layer is disposed between the gate electrode and the source electrode, the spacer layer being a low- κ dielectric material.
3. The field effect transistor according to claim 1, wherein the insulating substrate is a high-resistance silicon substrate having a surface formed with a silicon dioxide layer, or a high-resistance silicon, silicon carbide, diamond, or sapphire substrate.
4. The field effect transistor of claim 1, wherein the indium tin oxide channel layer has an aspect ratio of 3:1 to 8:1 and a height of 5 to 50 nm.
5. The field effect transistor of claim 1, wherein said high- κ gate dielectric layer is a high- κ dielectric material selected from HfO2、HfSiO4、Si3N4、La2O5、ZrO2(ii) a The thickness of the gate dielectric layer surrounding the indium tin oxide channel layer, i.e. the distance between the channel and the gate electrode, is 2-10 nm.
6. A method for producing a field effect crystal according to any one of claims 1 to 5, comprising the steps of:
1) cleaning the insulating substrate;
2) preparing a drain electrode on an insulating substrate;
3) preparing an indium tin oxide channel layer with a large height-width ratio on the drain electrode;
4) depositing a high-k dielectric material to form a gate dielectric layer coating the indium tin oxide channel layer;
5) growing a gate electrode layer on the gate dielectric layer;
6) depositing a low-k dielectric material on the gate electrode layer to form an isolation layer;
7) defining an etching area by adopting electron beam lithography, removing the isolation layer and the gate electrode layer on the top by adopting dry etching to expose the top of the channel layer and form a ring gate electrode, and then removing the photoresist mask;
8) depositing a low-k dielectric material as an insulating isolation layer of the top source electrode and the gate all around electrode;
9) defining an etching area by adopting electron beam lithography, removing part of the isolation layer by adopting dry etching, and exposing the top of the channel layer and the test areas of the drain electrode and the gate electrode;
10) and preparing a source electrode on the top of the indium tin oxide channel layer.
7. The method of manufacturing according to claim 6, wherein the indium tin oxide channel layer is manufactured by magnetron sputtering in step 3).
8. The method of claim 6, wherein step 4) is performed by depositing the high- κ dielectric material by atomic layer deposition; and 6) depositing the low-k dielectric material by adopting plasma enhanced chemical vapor deposition in the step 8).
9. The method according to claim 6, wherein the dry etching in step 7) and step 9) is inductively coupled plasma dry etching.
10. The method of claim 6, wherein the drain electrode and the source electrode are separately prepared by evaporating metal in step 2) and step 10) by electron beam evaporation.
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| CN202111571065.8A CN114242780A (en) | 2021-12-21 | 2021-12-21 | Indium tin oxide vertical ring grid field effect transistor and preparation method thereof |
| PCT/CN2022/070644 WO2023115654A1 (en) | 2021-12-21 | 2022-01-07 | Indium tin oxide vertical gate-all-around field effect transistor and preparation method therefor |
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| CN116230737A (en) * | 2022-06-30 | 2023-06-06 | 北京超弦存储器研究院 | Semiconductor device, method of manufacturing the same, and electronic apparatus |
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| WO2023184927A1 (en) * | 2022-03-30 | 2023-10-05 | 北京超弦存储器研究院 | Field-effect transistor, memory and preparation method therefor, semiconductor array, and transistor |
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| CN102263201A (en) * | 2010-05-25 | 2011-11-30 | 中国科学院微电子研究所 | Organic field effect transistor and preparation method thereof |
| US9368619B2 (en) * | 2013-02-08 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for inducing strain in vertical semiconductor columns |
| CN108878425B (en) * | 2017-05-09 | 2021-09-03 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
| DE102021108598A1 (en) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | HETEROSTRUCTURAL OXIDE SEMICONDUCTOR TRANSISTOR WITH VERTICAL GATE-ALL-AROUND (VGAA) AND PROCESS FOR THE PRODUCTION OF IT |
| CN113078208A (en) * | 2021-03-09 | 2021-07-06 | 深圳大学 | Surrounding grid field effect transistor and preparation method thereof |
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| CN116230765A (en) * | 2022-03-30 | 2023-06-06 | 北京超弦存储器研究院 | MOS tube, memory and preparation method thereof |
| WO2023184927A1 (en) * | 2022-03-30 | 2023-10-05 | 北京超弦存储器研究院 | Field-effect transistor, memory and preparation method therefor, semiconductor array, and transistor |
| WO2023184914A1 (en) * | 2022-03-30 | 2023-10-05 | 北京超弦存储器研究院 | Mos transistor, memory and manufacturing method therefor |
| CN116230765B (en) * | 2022-03-30 | 2024-03-15 | 北京超弦存储器研究院 | MOS tube, memory and preparation method thereof |
| CN116230737A (en) * | 2022-06-30 | 2023-06-06 | 北京超弦存储器研究院 | Semiconductor device, method of manufacturing the same, and electronic apparatus |
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| CN115932015A (en) * | 2023-01-09 | 2023-04-07 | 福州大学 | T-shaped gate FET biosensor based on atomic layer deposition semiconductor channel |
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