CN111640800B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN111640800B CN111640800B CN202010366057.9A CN202010366057A CN111640800B CN 111640800 B CN111640800 B CN 111640800B CN 202010366057 A CN202010366057 A CN 202010366057A CN 111640800 B CN111640800 B CN 111640800B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 59
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims abstract description 41
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 5
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 2
- 239000010409 thin film Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000005294 ferromagnetic effect Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000005291 magnetic effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 229910021389 graphene Inorganic materials 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor device and a preparation method thereof, wherein the device comprises: an insulating substrate; the grid electrode, the grid dielectric layer, the active layer and the source drain electrode are arranged on the insulating substrate from bottom to top in sequence; the active layer is made of a heterostructure material formed by pseudobrookite and titanium oxide. The device and the method provided by the invention are used for solving the technical problem that the performance of the semiconductor device in the prior art needs to be improved. A semiconductor device having superior performance is provided.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
With the continuous progress of the technology, particularly the development and wide application of the graphene two-dimensional material, the development of the novel two-dimensional material is greatly promoted. The most important characteristic of the novel two-dimensional material is that the mobility of electrons transmitted on the novel two-dimensional material is high; in addition, compared to conventional bulk materials, new two-dimensional materials are widely used in semiconductor devices due to their superior optical, electrical, and thermal properties. Based on these characteristics, a large number of novel two-dimensional materials are prepared into thin film transistors such as graphene Thin Film Transistor (TFT) and MoS 2 Thin film transistors, black phosphorus thin film transistors, and the like. However, the device is not limited to the specific type of the deviceHowever, these transistors have various problems, such as large negative threshold voltage, large sub-threshold swing, etc. These problems will greatly affect the performance of the thin film transistor.
Disclosure of Invention
It is an object of the present disclosure, at least in part, to provide a semiconductor device with stable and superior performance and a method of manufacturing the same.
In a first aspect, a semiconductor device is provided, including:
an insulating substrate;
the grid electrode, the grid dielectric layer, the active layer and the source drain electrode are arranged on the insulating substrate from bottom to top in sequence;
the active layer is made of a heterostructure material formed by pseudobrookite and titanium oxide.
Optionally, the pseudobrookite is Fe 2 TiO 5 The titanium oxide is TiO 2 。
Optionally, the active layer is sequentially formed by the pseudobrookite material layer and the titanium oxide material layer from bottom to top.
Optionally, the thickness of the active layer is 100nm to 1000nm.
Optionally, the thickness of the pseudobrookite material layer is equal to the thickness of the titanium oxide material layer.
Optionally, the gate is a metal gate, and the thickness of the gate is 30nm-100nm; the gate dielectric layer is SiO or Al 2 O 3 Or HfO 2 The thickness is 500nm-1000nm; the source and drain electrodes are Mo or Ti/Au, and the thickness is 100nm-1 μm.
In a second aspect, a method for manufacturing a semiconductor device is provided, including:
preparing a grid electrode on an insulating substrate, and preparing a grid dielectric layer on the grid electrode;
forming a heterostructure material of pseudobrookite and titanium oxide on the gate dielectric layer to serve as an active layer;
and forming a source drain electrode on the active layer.
Optionally, the preparing a gate on an insulating substrate includes: and etching a grid pattern groove on the insulating substrate, and filling grid materials in the groove to form the grid.
Optionally, the forming of the heterostructure material of pseudobrookite and titanium oxide on the gate dielectric layer as an active layer includes: and forming a heterostructure material of pseudobrookite and titanium oxide on the gate dielectric layer as the active layer by adopting a magnetron sputtering or pulse laser deposition process.
Optionally, forming a heterostructure material of pseudobrookite and titanium oxide on the gate dielectric layer as an active layer includes: preparing a pseudobrookite material layer on the grid dielectric layer; preparing a titanium oxide material layer on the pseudobrookite material layer, wherein the pseudobrookite material layer and a heterostructure material formed by the titanium oxide material layer are used as the active layer.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the semiconductor device and the preparation method thereof, the heterostructure material formed by the pseudobrookite and the titanium oxide is used as the active layer of the semiconductor device, so that the semiconductor device not only has the electron transport property of a semiconductor, but also can generate ferromagnetic property. The device has low off-state current and high mobility, and the process can be well compatible with the traditional CMOS structure process, so that a novel semiconductor device with high performance and compatibility with the existing process and a preparation method are provided.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only examples of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of a semiconductor device according to one or more embodiments of the present disclosure;
fig. 2 is a flow diagram of a method of fabricating a semiconductor device according to one or more embodiments of the present disclosure;
FIG. 3 is a first process flow diagram of a semiconductor device according to one or more embodiments of the present disclosure;
FIG. 4 is a second process flow diagram of a semiconductor device according to one or more embodiments of the present disclosure;
fig. 5 is a third process flow diagram of a semiconductor device in accordance with one or more embodiments of the present disclosure;
fig. 6 is a fourth process flow diagram of a semiconductor device in accordance with one or more embodiments of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In the context of the present disclosure, similar or identical components may be denoted by the same or similar reference numerals.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to specific embodiments, and it should be understood that the specific features in the examples and examples of the present disclosure are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application, and the technical features in the examples and examples of the present application may be combined with each other without conflict.
According to an aspect of the present disclosure, there is provided a semiconductor device, as shown in fig. 1, including:
an insulating substrate 1;
the grid electrode 2, the grid dielectric layer 3, the active layer 4 and the source-drain electrode 5 are arranged on the insulating substrate 1 from bottom to top in sequence;
wherein the material of the active layer 4 is a heterostructure material formed by pseudobrookite 41 and titanium oxide 42.
Based on the same inventive concept, there is also provided a method for manufacturing a semiconductor device, specifically, the method for manufacturing a semiconductor device shown in fig. 1, as shown in fig. 2, the method includes:
step S101, preparing a grid electrode 2 on an insulating substrate 1, and preparing a grid dielectric layer 3 on the grid electrode 2;
step S102, forming a heterostructure material of pseudobrookite and titanium oxide on the gate dielectric layer 3 as an active layer 4;
in step S103, source/drain electrodes 5 are formed on the active layer 4.
The structure of the semiconductor device and the fabrication process thereof provided by the present disclosure are described in detail below with reference to fig. 1-6:
first, an insulating substrate 1 as shown in fig. 3 is provided, and the insulating substrate 1 may be a glass substrate, a silicon oxide substrate, or the like, without limitation. Preferably, the thickness of the insulating substrate 1 may be 100 μm to 500 μm for both support and reliability.
Then, step S101 is performed to prepare a gate 2 on the insulating substrate 1 as shown in fig. 4, and prepare a gate dielectric layer 3 on the gate 2 as shown in fig. 5.
Specifically, the gate 2 may be a metal gate or a polysilicon gate. Preferably, the gate 2 is a metal gate, which may be a metal such as Mo or Au, and the gate 2 has a thickness of 30nm to 100nm.
Preferably, a gate pattern groove may be etched on the insulating substrate 1, and the groove may be filled with a gate material to form the gate 2. Specifically, photoresist can be coated and developed to prepare a metal grid pattern, grid pattern grooves are etched through etching machines such as ICP (inductively coupled plasma), the grid pattern grooves are filled in a mode of evaporating Mo or Au through electron beams, and then the metal grid is prepared by stripping redundant metal on the photoresist through stripping liquid.
Specifically, the gate dielectric layer 3 may be SiO or Al 2 O 3 Or HfO 2 And the thickness of the medium is 100nm-1000nm, preferably 500nm-1000nm. The preparation process can be deposition or magnetron sputtering growth, and specifically can be a chemical vapor deposition method or a physical deposition method and the like.
Then, step S102 is performed, as shown in fig. 6, a heterostructure material of pseudobrookite and titanium oxide is formed as the active layer 4 on the gate dielectric layer 3.
In the embodiment of the present application, the pseudobrookite may be Fe 2-X Ti 1+Y O 5 The titanium oxide may be Ti 1+N O 2-M Wherein X, Y, N and M are integers. Preferably, the pseudobrookite is Fe 2 TiO 5 The titanium oxide being TiO 2 So as to ensure the stability of the formed heterostructure material.
In the specific implementation process, the upper and lower positions of the pseudobrookite 41 layer and the titanium oxide 42 layer are not limited, and the pseudobrookite 41 layer may be first prepared on the gate dielectric layer 3, and then the titanium oxide 42 layer may be prepared on the pseudobrookite 41 layer, or the titanium oxide 42 layer may be first prepared on the gate dielectric layer 3, and then the pseudobrookite 41 layer may be prepared on the titanium oxide 42 layer. Preferably, the active layer 4 is a material layer of pseudobrookite 41 and a material layer of titanium oxide 42 from bottom to top in sequence, so as to ensure stability.
Optionally, the thickness of the active layer 4 is 100nm to 1000nm, wherein the thicknesses of the pseudobrookite 41 layer and the titanium oxide 42 layer are not limited, and preferably, the thickness of the pseudobrookite 41 material layer is equal to the thickness of the titanium oxide 42 material layer, so as to ensure the optimal magnetic performance and semiconductor performance. Preferably, a heterostructure material of pseudobrookite 41 and titanium oxide 42 films can be prepared on the gate dielectric layer 3 by using a magnetron sputtering technology or a pulse laser deposition technology, so as to reduce defects and ensure the reliability and performance of an active layer.
Pseudobrookite is a two-dimensional non-van der Waals material existing in nature, and is a semiconductor material with n-type characteristics, and the band gap of the pseudobrookite is about 2eV. Pseudobrookite not only has the characteristics of semiconductors, but also has unique ferromagnetic characteristics. The heterostructure material formed by pseudobrookite 41 and titanium oxide 42 thin-film materials is used as the active layer 4 of the device, so that the stable electronic device with low off-state current and high mobility can be realized, and the prepared electronic device contains transistor characteristics and magnetic characteristics and can be used in environments needing the magnetic characteristics.
Next, step S103 is performed, as shown in fig. 1, to form the source-drain electrode 5 on the active layer 4
Specifically, source/drain electrode material is deposited or grown (e.g. electron beam evaporation), and the source/drain electrode 5 may be made of conductive material such as Mo or Ti/Au, and has a thickness of 100nm to 1 μm. And performing patterning treatment, namely exposing and developing by using ultraviolet rays to leave photoresist with a specific pattern, bombarding and etching by using oxygen plasma, and washing away the photoresist to finish patterning of the source and drain electrodes to prepare the source and drain electrodes.
The following is a specific example to help understand the method and device structure provided by the present embodiment.
Firstly, etching a grid pattern groove with the depth of 30nm-50nm on an insulating substrate 1, and then filling Mo or Au in the groove by using electron beam evaporation growth to serve as grid metal 2. Then, growing SiO with the thickness of 500nm-1000nm by magnetron sputtering 2 As a gate dielectric layer 3, fe with the thickness of 200nm is grown on the gate dielectric layer by magnetron sputtering 2 TiO 5 And TiO 2 2 Heterostructure material formed by thin film material as active layer 4, finally growing with thickness of 50nm by electron beam evaporationMo or Ti/Au with the thickness of-100 nm is used as the source and drain electrode 5.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
according to the semiconductor device and the preparation method thereof, the heterostructure material formed by the pseudobrookite and the titanium oxide is used as the active layer of the semiconductor device, so that the semiconductor device not only has the electron transport property of a semiconductor, but also can generate ferromagnetic property. The device has low off-state current and high mobility, and the process can be well compatible with the traditional CMOS structure process, so that a novel semiconductor device with high performance and compatibility with the existing process and a preparation method are provided.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. Further, although the embodiments are described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination.
It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.
Claims (10)
1. A semiconductor device, comprising:
an insulating substrate;
the grid electrode, the grid dielectric layer, the active layer and the source drain electrode are arranged on the insulating substrate from bottom to top in sequence;
the active layer is made of a laminated heterostructure material formed by a pseudobrookite film and a titanium oxide film.
2. The semiconductor device according to claim 1, wherein the pseudobrookite is Fe 2 TiO 5 The titanium oxide is TiO 2 。
3. The semiconductor device according to claim 1, wherein the active layer is the pseudobrookite material layer and the titanium oxide material layer in this order from bottom to top.
4. The semiconductor device of claim 1, wherein the active layer has a thickness of 100nm to 1000nm.
5. The semiconductor device according to claim 1, wherein a thickness of the material layer of pseudobrookite is equal to a thickness of the material layer of titanium oxide.
6. The semiconductor device according to claim 1, wherein:
the gate is a metal gate, and the thickness of the gate is 30nm-100nm;
the gate dielectric layer is made of SiO and Al 2 O 3 Or HfO 2 The thickness is 500nm-1000nm;
the source and drain electrodes are Mo or Ti/Au, and the thickness is 100nm-1 μm.
7. A method of manufacturing a semiconductor device, comprising:
preparing a grid electrode on an insulating substrate, and preparing a grid dielectric layer on the grid electrode;
forming a laminated heterostructure material of a pseudobrookite film and a titanium oxide film on the gate dielectric layer to serve as an active layer;
and forming a source drain electrode on the active layer.
8. The method of manufacturing according to claim 7, wherein the manufacturing of the gate electrode on the insulating substrate includes:
and etching a grid pattern groove on the insulating substrate, and filling grid materials in the groove to form the grid.
9. The method according to claim 7, wherein the forming of the heterostructure material of pseudobrookite and titanium oxide as an active layer on the gate dielectric layer comprises:
and forming a heterostructure material of pseudobrookite and titanium oxide on the grid dielectric layer by adopting a magnetron sputtering or pulse laser deposition process to serve as the active layer.
10. The method of claim 7, wherein forming a heterostructure material of pseudobrookite and titanium oxide as an active layer on the gate dielectric layer comprises:
preparing a pseudobrookite material layer on the grid dielectric layer;
preparing a titanium oxide material layer on the pseudobrookite material layer, wherein the pseudobrookite material layer and a heterostructure material formed by the titanium oxide material layer are used as the active layer.
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