CN110112073B - Preparation method of field effect transistor and field effect transistor - Google Patents
Preparation method of field effect transistor and field effect transistor Download PDFInfo
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention provides a field effect transistor preparation method and a field effect transistor, and belongs to the technical field of field effect transistor manufacturing. The preparation method of the field effect transistor comprises the following steps: preparing a gate electrode on a substrate; preparing gate dielectric layers on the surfaces of the substrate and the gate electrode; transferring the two-dimensional semiconductor channel layer to the surface of the gate dielectric layer; preparing a source electrode and a drain electrode on two sides of the two-dimensional semiconductor channel layer; and adjusting the growth sequence of elements of the passivation layer on the surface of the two-dimensional semiconductor channel layer according to different channel types, and growing the passivation layer in a circulating and reciprocating manner. The field effect transistor preparation method provided by the invention can prepare a field effect transistor with lower sub-threshold swing amplitude, adjust the threshold voltage of the transistor, improve the switching speed and stability of the transistor, and reduce the signal noise and power consumption of the transistor.
Description
Technical Field
The invention relates to the technical field of field effect transistor manufacturing, in particular to a field effect transistor and a preparation method thereof.
Background
In the post-molar age, the application of two-dimensional semiconductors in this field is beginning to be focused on the traditional silicon-based three-dimensional field effect transistor in the path of size reduction due to the physical limits of short channel effect and the like, and the increasingly high research and development and manufacturing costs. MoS2，MoSe2The two-dimensional materials, such as these, have no dangling bond, and have no short channel effect in the case of a single layer or a few layers, and therefore, the cost reduction and the like have been the main points of research. However, there are some critical problems that are not solved in this field, such as: due to defects in the material itself and at the interface between the material and the insulating layerThe channel region has a plurality of shallow defect states, the shallow defect states can increase the subthreshold swing, so that the transistor device has low light-on speed and large power consumption, the threshold voltage is a large negative voltage, the power consumption of the transistor device is increased, and the transistor device is unstable.
Disclosure of Invention
Technical problem to be solved
The invention provides a field effect transistor preparation method and a field effect transistor, which at least partially solve the technical problems.
(II) technical scheme
According to an aspect of the present invention, there is provided a method for manufacturing a field effect transistor, including:
preparing a gate electrode on a substrate;
preparing gate dielectric layers on the surfaces of the substrate and the gate electrode;
transferring the two-dimensional semiconductor channel layer to the gate dielectric layer;
preparing a source electrode and a drain electrode on two sides of the two-dimensional semiconductor channel layer;
and growing a passivation layer on the surface of the two-dimensional semiconductor channel layer according to the growth sequence of the elements of the passivation layer adjusted according to different channel types.
In some embodiments, adjusting the growth sequence of the passivation layer elements according to different channel types includes:
for an n-type channel, first growing a first element and then growing a second element;
for a p-type channel, firstly growing the second element, and then growing the first element; wherein the electronegativity of the first element is weaker than that of the second element.
In some embodiments, preparing a gate electrode on a substrate comprises:
coating photoresist on the surface of a substrate, and exposing and developing the photoresist;
growing metal or metal compound on the surfaces of the substrate and the photoresist to be used as a gate electrode;
and washing off the photoresist to obtain the patterned gate electrode.
In some embodiments, a magnetron sputtering method or an ion beam sputtering method or an electron beam evaporation method is used to grow a metal or a metal compound as a gate electrode; the thickness of the gate electrode is 10nm-50 nm; the metal material is Pt, Ti, Cu or Au, and the metal compound material is metal nitride.
In some embodiments, transferring a two-dimensional semiconductor channel layer onto a gate dielectric layer comprises:
spin-coating polymethyl methacrylate on the surface of the two-dimensional semiconductor channel layer, and drying;
transferring the two-dimensional semiconductor channel layer to a gate dielectric layer by taking polymethyl methacrylate as a carrier;
and removing the polymethyl methacrylate on the surface of the two-dimensional semiconductor channel layer.
In some embodiments, after the step of transferring the two-dimensional semiconductor channel layer onto the gate dielectric layer, the method further comprises:
and coating photoresist on the surface of the two-dimensional semiconductor channel layer, and patterning the two-dimensional semiconductor channel layer to obtain the patterned two-dimensional semiconductor channel layer.
In some embodiments, preparing a source electrode and a drain electrode on both sides of the two-dimensional semiconductor channel layer includes:
coating photoresist on the two-dimensional semiconductor channel layer, and carrying out development and exposure operations;
growing metal or metal compound on the surface of the photoresist as a source electrode and a drain electrode;
and washing the photoresist to obtain the patterned source electrode and drain electrode.
In some embodiments, an electron beam evaporation method is used to grow metals as source and drain electrodes; the thickness of the source electrode and the drain electrode is 10nm-50 nm; the metal is made of Pt, Ti, Cu or Au.
In some embodiments, the gate dielectric layer is prepared by atomic layer deposition, magnetron sputtering or ion beam sputtering, and the gate dielectric layer is made of binary oxideThe thickness of the gate dielectric layer is 5nm-200 nm; the two-dimensional semiconductor channel layer is made of graphene and MoS2、MoSe2Or WSe2(ii) a The passivation layer is made of TiO2、HfO2Or Al2O3。
According to another aspect of the present invention, there is provided a field effect crystal light prepared by the above provided method, comprising:
the semiconductor device comprises a substrate, a gate electrode, a gate dielectric layer, a two-dimensional semiconductor channel layer, a source electrode, a drain electrode and a passivation layer; the gate electrode is positioned above the substrate, the gate dielectric layer covers the gate electrode and the surface of the substrate, the two-dimensional semiconductor channel layer is positioned above the gate dielectric layer, the source electrode and the drain electrode are positioned on two sides of the two-dimensional semiconductor channel layer, and the passivation layer is positioned on the surface of the two-dimensional semiconductor channel layer.
(III) advantageous effects
According to the technical scheme, the field effect transistor and the preparation method thereof have at least one or part of the following beneficial effects:
(1) according to the field effect transistor preparation method provided by the invention, a compound with polarity is used as a passivation layer on the surface of a channel layer, the growth sequence of elements of the passivation layer is adjusted according to different channel types, and an electric dipole moment is formed on the surface of the channel layer by cyclically and repeatedly growing the passivation layer, and the electric dipole moment can reduce the energy level height of a shallow defect state in a channel region to enable the energy level height to be a deep defect energy level, so that the field effect transistor with lower sub-threshold swing amplitude is prepared, the threshold voltage of the transistor is adjusted, the switching speed and stability of the transistor are improved, and the signal noise and the power consumption of the transistor are reduced;
(2) the field effect transistor provided by the invention has the advantages of simple structure, low cost and high reliability, can be compatible with the traditional CMOS process, and is beneficial to wide popularization and application.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
In the above figures, the reference numerals have the following meanings:
1-substrate, 2-gate electrode, 3-gate dielectric layer, 4-two-dimensional semiconductor channel layer, 5-drain electrode, 6-source electrode and 7-passivation layer.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
According to an aspect of the present invention, there is provided a method for manufacturing a field effect transistor, as shown in fig. 1, the method comprising the steps of:
step S1, preparing a gate electrode on the substrate;
step S2, preparing gate dielectric layers on the surfaces of the substrate and the gate electrode;
step S3, transferring the two-dimensional semiconductor channel layer to a gate dielectric layer;
step S4, preparing a source electrode and a drain electrode on both sides of the two-dimensional semiconductor channel layer;
and step S5, growing a passivation layer on the surface of the two-dimensional semiconductor channel layer according to the growth sequence of the elements of the passivation layer adjusted by different channel types.
According to the field effect transistor and the preparation method thereof, provided by the invention, a compound with polarity is used as a passivation layer on the surface of a channel layer, the growth sequence of elements of the passivation layer is adjusted according to different channel types, and an electric dipole moment is formed on the surface of the channel layer by cyclically and repeatedly growing the passivation layer, so that the electric dipole moment can reduce the energy level height of a shallow defect state in a channel region to enable the energy level height to become a deep defect energy level, the field effect transistor with lower sub-threshold swing amplitude is prepared, the threshold voltage of the transistor is adjusted, the switching speed and stability of the transistor are improved, and the signal noise and the power consumption of the transistor are reduced.
Wherein, in S1, the preparing the gate electrode on the substrate includes the following substeps:
s11, coating photoresist on the surface of the substrate, and exposing and developing the photoresist: coating photoresist on the surface of a substrate, and exposing and developing the photoresist by using ultraviolet rays;
s12, growing metal or metal compound on the surface of the substrate and the photoresist to be used as a gate electrode: placing a substrate and photoresist in an evaporation table chamber, and growing metal or a metal compound as a gate electrode by adopting a magnetron sputtering method, an ion beam sputtering method or an electron beam evaporation method; wherein the thickness of the gate electrode is 10nm-50 nm; the metal material can be Pt, Ti, Cu or Au, and the metal compound material is metal nitride such as TiN;
s13, washing away the photoresist to obtain a patterned gate electrode: putting the substrate with the manufactured gate electrode into an acetone solution to be soaked for about 15 minutes, and washing away the photoresist; soaking the substrate with the gate electrode in absolute ethyl alcohol for about 5 minutes, and washing off acetone; and drying the substrate with the gate electrode by using nitrogen to obtain the patterned gate electrode.
In step S2, in preparing the gate dielectric layer on the surface of the substrate and the gate electrode, the gate dielectric layer may be prepared by atomic layer deposition, magnetron sputtering, ion beam sputtering, or the like, and the material for preparing the gate dielectric layer is a binary oxide, such as SiO2、HfO2And Al2O3The thickness of the gate dielectric layer is 5nm-200 nm.
The step S3 of transferring the two-dimensional semiconductor channel layer to the gate dielectric layer includes the following substeps:
s31, spin-coating polymethyl methacrylate on the surface of the two-dimensional semiconductor channel layer, and drying;
s32, transferring the two-dimensional semiconductor channel layer to the gate dielectric layer by taking polymethyl methacrylate as a carrier;
and S33, removing the polymethyl methacrylate on the surface of the two-dimensional semiconductor channel layer.
Wherein, the material of the two-dimensional semiconductor channel layer can be graphene or MoS2，MoSe2，MoTe2，WS2，WSe2，WTe2，ReS2Or black phosphorus, etc.
In this embodiment, after S3 and before S4, the method further includes:
and coating photoresist on the surface of the two-dimensional semiconductor channel layer, and patterning the two-dimensional semiconductor channel layer to obtain the two-dimensional semiconductor channel layer with a specific pattern. Specifically, photoresist is coated on the surface of the two-dimensional semiconductor channel layer, the photoresist is exposed and developed by utilizing ultraviolet rays, and then, redundant semiconductor materials are bombarded by utilizing oxygen plasmas to obtain the graphical two-dimensional semiconductor channel layer.
The S4, preparing a source electrode and a drain electrode on both sides of the two-dimensional semiconductor channel layer, includes the following substeps:
s4l, coating photoresist on the surface of the two-dimensional semiconductor channel layer, and carrying out exposure and development operations;
s42, growing metal or metal compound on the surface of the photoresist as a source electrode and a drain electrode: growing metal on the surface of the photoresist by methods such as electron beam evaporation and the like to be used as a source electrode and a drain electrode; the positions of the source electrode and the drain electrode can be interchanged, the thickness of the source electrode and the thickness of the drain electrode are 10nm-50nm, and the material of the source electrode and the drain electrode can be simple substance metal such as Pt, Ti, Cu or Au;
s43, washing the photoresist to obtain a source electrode and a drain electrode with specific patterns: placing the substrate with the manufactured source electrode and drain electrode into an acetone solution to be soaked for about 15 minutes, and washing away the photoresist; placing the substrate of the active electrode and the drain electrode into absolute ethyl alcohol to be soaked for about 5 minutes, and washing off acetone; and drying the substrate of the active electrode and the drain electrode by using nitrogen to obtain the patterned source electrode and the patterned drain electrode.
S5, growing a passivation layer on the surface of the two-dimensional semiconductor channel layer according to the growth sequence of elements of the passivation layer adjusted by different channel types, specifically, adjusting the growth sequence of elements of the passivation layer on the surface of the two-dimensional material according to different channel types by adopting an atomic layer deposition technology: for an n-type channel, an element with weak electronegativity needs to be grown first, and an element with strong electronegativity needs to be grown again; for a p-type channel, an element with strong electronegativity needs to be grown first, and then an element with weak electronegativity needs to be grown; wherein, the thickness of the passivation layer is generally 2nm-20 nm; temperature of atomic layer depositionIs 100-400 ℃; the compound species having polarity of the passivation layer includes TiO2、HfO2、Al2O3. For example, for an n-type channel, if the passivation layer is made of Al2O3When growing the passivation layer, it is necessary to grow a layer of the element Al with weak electronegativity first and then grow the element O with strong electronegativity to form Al2O3Then respectively growing a layer of Al element and O element to form Al2O3And growing to the required thickness in a cyclic and reciprocating way.
According to the field effect transistor preparation method provided by the invention, a compound with polarity is used as a passivation layer on the surface of a channel layer, for an n-type channel, an element with low electronegativity is grown on the surface of the channel layer firstly by adopting an atomic layer deposition technology, and then an element with high electronegativity is grown on the surface of the channel layer firstly by adopting an atomic layer deposition technology, and then an element with low electronegativity is grown, and the element with low electronegativity is repeatedly circulated, so that an electric dipole moment with a positive/negative electricity center facing downwards is formed on the surface of the channel, the electric dipole moment can reduce the energy level height of a shallow defect state in the channel region to enable the energy level to become a deep defect energy level, a field effect transistor with lower sub-threshold value is prepared, the threshold voltage is regulated, the switching speed and stability of the transistor are improved, and the signal noise and the power consumption of the transistor are reduced.
According to another aspect of the present invention, there is provided a field effect transistor manufactured by the method provided in the above embodiment, as shown in fig. 2, the field effect transistor comprising:
the structure comprises a substrate 1, a gate electrode 2, a gate dielectric layer 3, a two-dimensional semiconductor channel layer 4, a source electrode 5, a drain electrode 6 and a passivation layer 7; the gate electrode 2 is located above the substrate 1, the gate dielectric layer 3 covers the gate electrode 2 and the surface of the substrate 1, the two-dimensional semiconductor channel layer 4 is located above the gate dielectric layer 3, the source electrode 5 and the drain electrode 6 are located above the two-dimensional semiconductor channel layer 4, and the passivation layer 7 is located on the surface of the two-dimensional semiconductor channel layer 4.
In the present embodiment, the substrate 1 is an insulating material such as glass; the thickness of the gate electrode 2 may be between 10nm and 50nm, and the material used may be a single layerA metalloid such as Pt, Ti, Cu, Au or a metal nitride such as TiN; the thickness of the gate dielectric layer 3 is generally 5nm-200nm, and the adopted material is binary oxide, such as SiO2、HfO2、Al2O3(ii) a The material of the two-dimensional semiconductor channel layer 4 may be graphene, MoS2，MoSe2，MoTe2，WS2，WSe2，WTe2，ReS2Or black phosphorus; the thicknesses of the source electrode 5 and the drain electrode 6 can be 10nm-50nm, and the adopted material can be simple substance metal such as Pt, Ti, Cu or Au; the compound species with polarity used for the passivation layer 7 having a thickness of typically 2nm to 20nm is TiO2、HfO2Or Al2O3。
The field effect transistor provided by the invention has the advantages of simple structure, low cost and high reliability, can be compatible with the traditional CMOS process, and is beneficial to wide popularization and application.
Up to this point, the present embodiment has been described in detail with reference to the accompanying drawings. From the above description, those skilled in the art should clearly recognize the present invention.
It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail.
It is also noted that the illustrations herein may provide examples of parameters that include particular values, but that these parameters need not be exactly equal to the corresponding values, but may be approximated to the corresponding values within acceptable error tolerances or design constraints. The directional terms used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present invention. In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
It should be noted that throughout the drawings, like elements are represented by like or similar reference numerals. In the above description, some specific embodiments are only used for descriptive purposes and should not be construed as limiting the invention in any way, but merely as exemplifications of embodiments of the invention. Conventional structures or constructions will be omitted when they may obscure the understanding of the present invention. It should be noted that the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present invention.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A method of fabricating a field effect transistor, the method comprising:
preparing a gate electrode on a substrate;
preparing gate dielectric layers on the surfaces of the substrate and the gate electrode;
transferring the two-dimensional semiconductor channel layer to the gate dielectric layer;
preparing a source electrode and a drain electrode on two sides of the two-dimensional semiconductor channel layer;
adjusting the growth sequence of elements of the passivation layer on the surface of the two-dimensional semiconductor channel layer according to different channel types, and growing the passivation layer in a circulating and reciprocating manner;
the adjusting of the growth sequence of the passivation layer elements according to different channel types comprises: for an n-type channel, first growing a first element and then growing a second element; and for the p-type channel, first growing the second element and then growing the first element; wherein the electronegativity of the first element is weaker than that of the second element.
2. The method of claim 1, wherein fabricating a gate electrode on a substrate comprises:
coating photoresist on the surface of a substrate, and exposing and developing the photoresist;
growing metal or metal compound on the surfaces of the substrate and the photoresist to be used as a gate electrode;
and washing off the photoresist to obtain the patterned gate electrode.
3. The method according to claim 2, wherein a metal or a metal compound is grown as the gate electrode by a magnetron sputtering method or an ion beam sputtering method or an electron beam evaporation method; the thickness of the gate electrode is 10nm-50 nm; the metal material is Pt, Ti, Cu or Au, and the metal compound material is metal nitride.
4. The method of claim 1, wherein transferring the two-dimensional semiconductor channel layer onto a gate dielectric layer comprises:
spin-coating polymethyl methacrylate on the surface of the two-dimensional semiconductor channel layer, and drying;
transferring the two-dimensional semiconductor channel layer to a gate dielectric layer by taking polymethyl methacrylate as a carrier;
and removing the polymethyl methacrylate on the surface of the two-dimensional semiconductor channel layer.
5. The method of claim 4, wherein after the step of transferring the two-dimensional semiconductor channel layer onto the gate dielectric layer, the method further comprises:
and coating photoresist on the surface of the two-dimensional semiconductor channel layer, and patterning the two-dimensional semiconductor channel layer through an exposure and development technology to obtain the patterned two-dimensional semiconductor channel layer.
6. The method of claim 1, wherein fabricating a source electrode and a drain electrode on both sides of the two-dimensional semiconductor channel layer comprises:
coating photoresist on the two-dimensional semiconductor channel layer, and performing exposure and development operations;
growing metal on the surface of the photoresist to be used as a source electrode and a drain electrode;
and washing the photoresist to obtain the patterned source electrode and drain electrode.
7. The method of claim 6, wherein the metal is grown as the source and drain electrodes by an electron beam evaporation method; the thickness of the source electrode and the drain electrode is 10nm-50 nm; the metal is made of Pt, Ti, Cu or Au.
8. The method according to claim 1, wherein the gate dielectric layer is prepared by atomic layer deposition, magnetron sputtering or ion beam sputtering, the gate dielectric layer is made of a binary oxide type, and the thickness of the gate dielectric layer is 5nm to 200 nm; the two-dimensional semiconductor channel layer is made of graphene and MoS2、MoSe2Or WSe2(ii) a The passivation layer is made of TiO2、HfO2Or Al2O3。
9. A field effect transistor prepared by the method of any of claims 1 to 8, comprising:
the semiconductor device comprises a substrate, a gate electrode, a gate dielectric layer, a two-dimensional semiconductor channel layer, a source electrode, a drain electrode and a passivation layer; the gate electrode is positioned above the substrate, the gate dielectric layer covers the gate electrode and the surface of the substrate, the two-dimensional semiconductor channel layer is positioned above the gate dielectric layer, the source electrode and the drain electrode are positioned on two sides of the two-dimensional semiconductor channel layer, and the passivation layer is positioned on the surface of the two-dimensional semiconductor channel layer.
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