CN110112073A - Field effect transistor tube preparation method and field effect transistor - Google Patents
Field effect transistor tube preparation method and field effect transistor Download PDFInfo
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- CN110112073A CN110112073A CN201910326880.4A CN201910326880A CN110112073A CN 110112073 A CN110112073 A CN 110112073A CN 201910326880 A CN201910326880 A CN 201910326880A CN 110112073 A CN110112073 A CN 110112073A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The present invention provides a kind of field effect transistor tube preparation method and field effect transistors, belong to field effect transistor manufacturing technology field.The field effect transistor tube preparation method includes: to prepare gate electrode on substrate；Gate dielectric layer is prepared in the substrate and surface gate electrode；Two-dimensional semiconductor channel layer is transferred to gate dielectric layer surface；Source electrode and drain electrode is prepared in the two sides of the two-dimensional semiconductor channel layer；In the two-dimensional semiconductor channel layer surface, the succession of passivation layer element, the growth of passivation layer to move in circles are adjusted according to different channel types.Field effect transistor tube preparation method provided by the invention, can prepare the field effect transistor of lower subthreshold swing, and have adjusted the threshold voltage of transistor, improve the switching speed and stability of transistor, reduce the signal noise and power consumption of transistor.
Description
Technical field
The present invention relates to field effect transistor manufacturing technology field more particularly to a kind of field effect transistor tube preparation method and
Field effect transistor.
Background technique
Rear mole of epoch, traditional silicon substrate three dimensional field effect transistor is on the path of size reduction, since short channel is imitated
Physics limits, and more high research and development and manufacturing cost, people should be waited to begin to focus on two-dimensional semiconductor in this field
Using.MoS2, MoSe2Etc. two-dimensional materials, short channel is not present due to not having a dangling bonds, and in the case where single layer or few layer
Effect, the reasons such as at low cost become the emphasis of research.But in the field, there is also some critical problems not to solve, such as:
Since the defect of material defect itself and material and insulating layer contact interface causes channel region to there are many shallow defect states, these are shallow
Defect state can be such that subthreshold swing increases, and cause transistor device speed of opening the light slow, and power consumption is big, and makes threshold voltage
For a biggish negative voltage, the power consumption of transistor device is increased, keeps transistor device unstable.
Summary of the invention
(1) technical problems to be solved
The present invention provides a kind of field effect transistor tube preparation method and field effect transistors, more than at least partly solving
The technical issues of proposed.
(2) technical solution
According to an aspect of the invention, there is provided a kind of field effect transistor tube preparation method, comprising:
Gate electrode is prepared on substrate；
Gate dielectric layer is prepared in the substrate and surface gate electrode；
Two-dimensional semiconductor channel layer is transferred on gate dielectric layer；
Source electrode and drain electrode is prepared in the two sides of the two-dimensional semiconductor channel layer；
In the two-dimensional semiconductor channel layer surface, the succession of passivation layer element is adjusted according to different channel types
Growth of passivation layer.
In some embodiments, the succession of passivation layer element is adjusted according to different channel types, comprising:
For n-type channel, the first element, regrowth second element are first grown；
For p-type channel, second element, the first element of regrowth are first grown；Wherein, the elecrtonegativity of the first element is compared with second
The elecrtonegativity of element is weak.
In some embodiments, gate electrode is prepared on substrate, comprising:
It is exposed and develops in substrate surface resist coating and to the photoresist；
In the substrate and photoresist surface growth metal or metallic compound as gate electrode；
The photoresist is washed away, patterned gate electrode is obtained.
In some embodiments, it is grown using magnetically controlled sputter method or ion beam sputtering method or electron beam evaporation method
Metal or metallic compound are as gate electrode；The gate electrode with a thickness of 10nm-50nm；The material of the metal be Pt, Ti,
Cu or Au, the metal compound material are metal nitride.
In some embodiments, two-dimensional semiconductor channel layer is transferred on gate dielectric layer, comprising:
Poly- polymethacrylic acid methyl ester is spin-coated on two-dimensional semiconductor channel layer surface, and is dried；
Using poly- polymethacrylic acid methyl ester as carrier, the two-dimensional semiconductor channel layer is transferred on gate dielectric layer；
Remove the poly- polymethacrylic acid methyl ester of the two-dimensional semiconductor channel layer surface.
In some embodiments, it is described two-dimensional semiconductor channel layer is transferred to the step on gate dielectric layer after, institute
State method further include:
In the two-dimensional semiconductor channel layer surface resist coating, the two-dimensional semiconductor channel layer is patterned,
Obtain patterned two-dimensional semiconductor channel layer.
In some embodiments, source electrode and drain electrode is prepared in the two sides of the two-dimensional semiconductor channel layer, comprising:
In the two-dimensional semiconductor channel layer resist coating, and carry out development and exposing operation；
Metal or metallic compound are grown as source electrode and drain electrode on the photoresist surface；
The photoresist is washed away, patterned source electrode and drain electrode is obtained.
In some embodiments, using electron beam evaporation method growth metal as source electrode and drain electrode；The source electricity
Pole and drain electrode with a thickness of 10nm-50nm；The material of the metal is Pt, Ti, Cu or Au.
In some embodiments, the gate dielectric layer is prepared using atomic layer deposition or magnetron sputtering or ion beam sputtering,
The material of the gate dielectric layer be binary oxide type, the gate dielectric layer with a thickness of 5nm-200nm；The two dimension is partly led
The material of body channel layer is graphene, MoS2、MoSe2Or WSe2；The material of the passivation layer is TiO2、HfO2Or Al2O3。
According to another aspect of the present invention, a kind of field effect transistor light of above-mentioned provided method preparation is provided,
Include:
Substrate, gate electrode, gate dielectric layer, two-dimensional semiconductor channel layer, source electrode, drain electrode and passivation layer；The grid
Electrode is located above the substrate, and the gate dielectric layer is covered in the gate electrode and the substrate surface, and the two dimension is partly led
Body channel layer is located above the gate dielectric layer, and the source electrode and drain electrode are located at two-dimensional semiconductor channel layer two sides,
The passivation layer is located at the two-dimensional semiconductor channel layer surface.
(3) beneficial effect
It can be seen from the above technical proposal that field effect transistor tube preparation method of the present invention and field effect transistor at least have
There are one of following beneficial effect or in which a part:
(1) field effect transistor tube preparation method provided by the invention, by using have polar compound as channel
The passivation layer of layer surface, and according to the succession of different channel type adjusting passivation layer elements, the growth to move in circles is blunt
Change layer, electric dipole moment can be formed in channel layer surface, this electric dipole moment can reduce the energy level height of the shallow defect state of channel region, be allowed to
As deep defect level, the field effect transistor of lower subthreshold swing is prepared, and has adjusted the threshold voltage of transistor, is mentioned
The high switching speed and stability of transistor, reduces the signal noise and power consumption of transistor；
(2) field-effect transistor structure provided by the invention is simple, at low cost, high reliablity and can and traditional cmos process
It is compatible, be conducive to of the invention being widely popularized and applying.
Detailed description of the invention
Fig. 1 is the flow chart of field effect transistor tube preparation method provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of field effect transistor provided in an embodiment of the present invention.
In above-mentioned attached drawing, appended drawing reference meaning is specific as follows:
1- substrate, 2- gate electrode, 3- gate dielectric layer, 4- two-dimensional semiconductor channel layer, 5- drain electrode, 6- source electrode, 7- are blunt
Change layer.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
According to an aspect of the invention, there is provided a kind of field effect transistor tube preparation method, as shown in Figure 1, this method
Include the following steps:
Step S1, prepares gate electrode on substrate；
Step S2 prepares gate dielectric layer in substrate and surface gate electrode；
Two-dimensional semiconductor channel layer is transferred on gate dielectric layer by step S3；
Step S4 prepares source electrode and drain electrode in the two sides of two-dimensional semiconductor channel layer；
Step S5 adjusts passivation layer element according to different channel types in the two-dimensional semiconductor channel layer surface
Succession growth of passivation layer.
Field effect transistor tube preparation method and field effect transistor provided by the invention, by using with polar chemical combination
Passivation layer of the object as channel layer surface, and according to the succession of different channel type adjusting passivation layer elements, it recycles past
Multiple growth of passivation layer can form electric dipole moment in channel layer surface, this electric dipole moment can reduce the energy of the shallow defect state of channel region
Grade height, makes deep defect level, prepares the field effect transistor of lower subthreshold swing, and have adjusted transistor
Threshold voltage improves the switching speed and stability of transistor, reduces the signal noise and power consumption of transistor.
Wherein, the S1 prepares gate electrode, including following sub-step on substrate:
S11 is exposed and develops in substrate surface resist coating and to the photoresist: applying photoetching in substrate surface
Glue is exposed and develops to the photoresist using ultraviolet light；
S12, in substrate and photoresist surface growth metal or metallic compound as gate electrode: substrate and photoresist are put
Be placed in evaporator chamber, using magnetically controlled sputter method or ion beam sputtering method or electron beam evaporation method growth metal or
Metallic compound is as gate electrode；Wherein, gate electrode with a thickness of 10nm-50nm；The material of metal can for Pt, Ti, Cu or
Person Au, metal compound material are metal nitride such as TiN；
S13 washes away photoresist, obtains patterned gate electrode: the substrate for making gate electrode is put into acetone soln
It is middle to impregnate about 15 minutes, wash away photoresist；The substrate for having gate electrode is put into dehydrated alcohol and is impregnated about 5 minutes, acetone is washed away；
There to be the substrate of gate electrode with being dried with nitrogen, obtains patterned gate electrode.
It in step S2, prepares in gate dielectric layer, can be splashed using atomic layer deposition or magnetic control in substrate and surface gate electrode
The material penetrated or the methods of ion beam sputtering prepares gate dielectric layer, and prepare gate dielectric layer is binary oxide, such as SiO2、
HfO2And Al2O3, gate dielectric layer with a thickness of 5nm-200nm.
Two-dimensional semiconductor channel layer is transferred on gate dielectric layer by the S3, including following sub-step:
Poly- polymethacrylic acid methyl ester is spin-coated on two-dimensional semiconductor channel layer surface, and dried by S31；
Two-dimensional semiconductor channel layer is transferred on gate dielectric layer by S32 using poly- polymethacrylic acid methyl ester as carrier；
S33 removes the poly- polymethacrylic acid methyl ester of the two-dimensional semiconductor channel layer surface.
Wherein, the material of two-dimensional semiconductor channel layer can be graphene, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2,
ReS2Or black phosphorus etc..
In the present embodiment, after the S3, before the S4, this method further include:
In two-dimensional semiconductor channel layer surface resist coating, two-dimensional semiconductor channel layer is patterned, is obtained specific
The two-dimensional semiconductor channel layer of figure.Specifically, in two-dimensional semiconductor channel layer surface resist coating, using ultraviolet light to photoetching
Glue is exposed and develops, and then falls extra semiconductor material using oxyanion precursor bombardment, obtains patterned two dimension and partly lead
Body channel layer.
The S4 prepares source electrode and drain electrode, including following sub-step in the two sides of two-dimensional semiconductor channel layer:
S4l is exposed and development operation in two-dimensional semiconductor channel layer surface resist coating；
S42 grows metal or metallic compound as source electrode and drain electrode on photoresist surface: using electron beam evaporation
The methods of photoresist surface growth metal as source electrode and drain electrode；Wherein, the position of source electrode and drain electrode can be mutual
Change, source electrode and drain electrode with a thickness of 10nm-50nm, the material of source electrode and drain electrode can for elemental metals such as Pt, Ti,
Cu or Au；
S43 washes away photoresist, obtains the source electrode and drain electrode of special pattern: will make source electrode and drain electrode
Substrate be put into acetone soln and impregnate about 15 minutes, wash away photoresist；The substrate of active electrode and drain electrode is put into anhydrous
It is impregnated in ethyl alcohol about 5 minutes, washes away acetone；By the substrate of active electrode and drain electrode with being dried with nitrogen, patterned source is obtained
Electrode and drain electrode.
The S5 adjusts the growth of passivation layer element according to different channel types in two-dimensional semiconductor channel layer surface
Sequence growth of passivation layer, specifically, adjusting two-dimensional material surface according to different channel types using technique for atomic layer deposition
The succession of passivation layer element: for n-type channel, need first to grow the weaker element of electronegativity, regrowth electronegativity is stronger
Element；For p-type channel, need first to grow the stronger element of electronegativity, the weaker element of regrowth electronegativity；Wherein, blunt
The thickness for changing layer is generally 2nm-20nm；The temperature of atomic layer deposition is 100 DEG C -400 DEG C；Passivation layer has polar chemical combination
Species include TiO2、HfO2、Al2O3.For example, for n-type channel, if the material that passivation layer uses is Al2O3, then blunt in growth
When changing layer, need first to grow the weaker Al element of one layer of electronegativity, the stronger O element of regrowth electronegativity forms Al2O3, then
It grows one layer of Al element and O element respectively again, forms Al2O3, what is looped back and forth like this grows to required thickness.
Field effect transistor tube preparation method provided by the invention, by using have polar compound as channel layer table
The passivation layer in face first grows the lesser element of electronegativity in channel layer surface using technique for atomic layer deposition for n-type channel,
The stronger element of regrowth electronegativity first grows electronegativity in channel layer surface using technique for atomic layer deposition for p-type channel
It is directed downwardly to form positive/negative electrfic centre in channel surface for stronger element, the lesser element of regrowth electronegativity, reciprocation cycle
Electric dipole moment, this electric dipole moment can reduce the energy level height of the shallow defect state of channel region, make deep defect level, prepare more
The field effect transistor of low subthreshold swing, and threshold voltage is had adjusted, the switching speed and stability of transistor are improved, is dropped
The low signal noise and power consumption of transistor.
According to another aspect of the present invention, a kind of field-effect prepared using method provided by the above embodiment is provided
Transistor, as shown in Fig. 2, the field effect transistor includes:
Substrate 1, gate electrode 2, gate dielectric layer 3, two-dimensional semiconductor channel layer 4, source electrode 5, drain electrode 6 and passivation layer 7；
Wherein, gate electrode 2 is located at 1 top of substrate, and gate dielectric layer 3 is covered in 1 surface of gate electrode 2 and substrate, two-dimensional semiconductor channel layer 4
Above gate dielectric layer 3, source electrode 5 and drain electrode 6 are located at 4 top of two-dimensional semiconductor channel layer, and passivation layer 7 is located at two dimension half
4 surface of conductor channel layer.
In the present embodiment, substrate 1 is insulating materials, such as glass；The thickness of gate electrode 2 can between 10nm-50nm,
Used material can be elemental metals such as Pt, Ti, Cu, Au or metal nitride such as TiN；3 thickness of gate dielectric layer is general
For 5nm-200nm, used material is binary oxide, such as SiO2、HfO2、Al2O3；The material of two-dimensional semiconductor channel layer 4
It can be graphene, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ReS2Or black phosphorus；, source electrode 5 and drain electrode 6 it is thick
Degree can be between 10nm-50nm, and used material can be elemental metals such as Pt, Ti, Cu or Au；The thickness of passivation layer 7
Having polar chemical combination species used by generally 2nm-20nm is TiO2、HfO2Or Al2O3。
Field-effect transistor structure provided by the invention is simple, at low cost, and high reliablity simultaneously can be simultaneous with traditional cmos process
Hold, is conducive to of the invention being widely popularized and applying.
So far, attached drawing is had been combined the present embodiment is described in detail.According to above description, those skilled in the art
There should be clear understanding to the present invention.
It should be noted that in attached drawing or specification text, the implementation for not being painted or describing is affiliated technology
Form known to a person of ordinary skill in the art, is not described in detail in field.
It should also be noted that, can provide the demonstration of the parameter comprising particular value herein, but these parameters are without definite etc.
In corresponding value, but analog value can be similar in acceptable error margin or design constraint.The side mentioned in embodiment
It is only the direction with reference to attached drawing, the protection scope being not intended to limit the invention to term.In addition, unless specifically described or must
The step of must sequentially occurring, there is no restriction for the sequences of above-mentioned steps in listed above, and can be changed according to required design or again
It is new to arrange.And above-described embodiment can be based on the considerations of design and reliability, and the collocation that is mixed with each other uses or and other embodiments
Mix and match uses, i.e., the technical characteristic in different embodiments can freely form more embodiments.
It should be noted that running through attached drawing, identical element is indicated by same or similar appended drawing reference.In the above description,
Some specific embodiments are used for description purposes only, and should not be construed to the present invention has any restrictions, and only the present invention is real
Apply the example of example.When may cause the understanding of the present invention and cause to obscure, conventional structure or construction will be omitted.It should be noted that figure
In the shape and size of each component do not reflect actual size and ratio, and only illustrate the content of the embodiment of the present invention.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (10)
1. a kind of field effect transistor tube preparation method, which is characterized in that the described method includes:
Gate electrode is prepared on substrate；
Gate dielectric layer is prepared in the substrate and surface gate electrode；
Two-dimensional semiconductor channel layer is transferred on gate dielectric layer；
Source electrode and drain electrode is prepared in the two sides of the two-dimensional semiconductor channel layer；
In the two-dimensional semiconductor channel layer surface, grown according to the succession that different channel types adjusts passivation layer element
Passivation layer.
2. the method according to claim 1, wherein adjusting the life of passivation layer element according to different channel types
Long sequence, comprising:
For n-type channel, the first element, regrowth second element are first grown；
For p-type channel, second element, the first element of regrowth are first grown；Wherein, the elecrtonegativity of the first element is compared with second element
Elecrtonegativity it is weak.
3. the method according to claim 1, wherein preparing gate electrode on substrate, comprising:
It is exposed and develops in substrate surface resist coating and to the photoresist；
In the substrate and photoresist surface growth metal or metallic compound as gate electrode；
The photoresist is washed away, patterned gate electrode is obtained.
4. according to the method described in claim 3, it is characterized in that, using magnetically controlled sputter method or ion beam sputtering method or
Electron beam evaporation method grows metal or metallic compound as gate electrode；The gate electrode with a thickness of 10nm-50nm；It is described
The material of metal is Pt, Ti, Cu or Au, and the metal compound material is metal nitride.
5. the method according to claim 1, wherein two-dimensional semiconductor channel layer is transferred on gate dielectric layer,
Include:
Poly- polymethacrylic acid methyl ester is spin-coated on two-dimensional semiconductor channel layer surface, and is dried；
Using poly- polymethacrylic acid methyl ester as carrier, the two-dimensional semiconductor channel layer is transferred on gate dielectric layer；
Remove the poly- polymethacrylic acid methyl ester of the two-dimensional semiconductor channel layer surface.
6. according to the method described in claim 5, it is characterized in that, two-dimensional semiconductor channel layer is transferred to gate medium described
After step on layer, the method also includes:
In the two-dimensional semiconductor channel layer surface resist coating, by exposure and imaging technology to the two-dimensional semiconductor channel
Layer is patterned, and obtains patterned two-dimensional semiconductor channel layer.
7. the method according to claim 1, wherein in the two sides of two-dimensional semiconductor channel layer preparation source electricity
Pole and drain electrode, comprising:
In the two-dimensional semiconductor channel layer resist coating, and carry out exposure and imaging operation；
On the photoresist surface, growth metal is as source electrode and drain electrode；
The photoresist is washed away, patterned source electrode and drain electrode is obtained.
8. the method according to the description of claim 7 is characterized in that using electron beam evaporation method growth metal as source electrode
And drain electrode；The source electrode and drain electrode with a thickness of 10nm-50nm；The material of the metal is Pt, Ti, Cu or Au.
9. the method according to claim 1, wherein using atomic layer deposition or magnetron sputtering or ion beam sputtering
Prepare the gate dielectric layer, the material of the gate dielectric layer is binary oxide type, the gate dielectric layer with a thickness of 5nm-
200nm；The material of the two-dimensional semiconductor channel layer is graphene, MoS2、MoSe2Or WSe2；The material of the passivation layer is
TiO2、HfO2Or Al2O3。
10. a kind of field effect transistor using the described in any item method preparations of claim 1 to 9, which is characterized in that packet
It includes:
Substrate, gate electrode, gate dielectric layer, two-dimensional semiconductor channel layer, source electrode, drain electrode and passivation layer；The gate electrode
Above the substrate, the gate dielectric layer is covered in the gate electrode and the substrate surface, the two-dimensional semiconductor ditch
Channel layer is located above the gate dielectric layer, and the source electrode and drain electrode are located at two-dimensional semiconductor channel layer two sides, described
Passivation layer is located at the two-dimensional semiconductor channel layer surface.
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