CN109712872A - Enhance the method for semiconductor devices ion implanting lithographic process window - Google Patents
Enhance the method for semiconductor devices ion implanting lithographic process window Download PDFInfo
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- CN109712872A CN109712872A CN201811632069.0A CN201811632069A CN109712872A CN 109712872 A CN109712872 A CN 109712872A CN 201811632069 A CN201811632069 A CN 201811632069A CN 109712872 A CN109712872 A CN 109712872A
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Abstract
The present invention relates to a kind of methods for enhancing semiconductor devices ion implanting lithographic process window, it is related to semiconductor integrated circuit manufacturing technology, the method of the enhancing semiconductor devices ion implanting lithographic process window includes carrying out semiconductor device surface processing using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) first, then photoetching process is carried out, wherein, when carrying out semiconductor device surface processing using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H), the surface treatment time is 5S~120S, the plasma temperature of the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) is 100 DEG C~1000 DEG C, to solve the problems, such as photoresist (PR) bottom unfilled corner (Undercut), enhance ion implanting photoetching work Skill window, optimized device performance.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing technologies more particularly to a kind of enhancing semiconductor devices ion to infuse
Enter the method for lithographic process window.
Background technique
In semiconductor integrated circuit manufacturing technology, grid curb wall generallys use silicon nitride material, in the integrated electricity of semiconductor
It is commonly used photoresist (PR) in the photoetching process (photoetching process before such as ion implantation technology) of road manufacturing process, however photoresist (PR)
It is more sensitive to nitrogenous material, it easily causes photoresist (PR) denaturation and generates chamfering (Footing) phenomenon, prior art is usual
Achieve the purpose that solve chamfering (Footing) by oxygen (O2) processing before photoetching, however due to active area (AA) and shallowly
Channel separating zone (STI) light reflectivity difference is easy to produce the bottom photoresist (PR) unfilled corner (Undercut) problem.
Specifically, seeing Fig. 1, Fig. 2 and Fig. 3, Fig. 1 is the structural schematic diagram of semiconductor devices before photoetching process, and Fig. 2 is
Tradition O2 processing schematic and Fig. 3 are the unfilled corner schematic diagram generated after photoetching process before photoetching process.As shown in Figure 1, in crystalline substance
Justify the gate structure constituted on substrate including shallow channel isolation area, trap injection region and polysilicon gate and grid curb wall, wherein grid
Pole side wall generallys use silicon nitride material.As shown in Fig. 2, it is existing to generate chamfering (Footing) in order to avoid photoresist (PR) denaturation
As being handled usually before photoetching process by O2.As shown in figure 3, the photoresist bottom (PR) generates unfilled corner after photoetching process
(Undercut) problem, such as unfilled corner 100.
With the development of semiconductor integrated circuit technology, such as at 28 nanometers and following technology node, above-mentioned photoresist (PR) bottom
Portion's unfilled corner (Undercut) problem becomes can not ignore, because it directly affects subsequent ion injection (such as LDD/Halo ion
Injection and S/D ion implanting) region that defines, ion implanting lithographic process window is influenced, and then influence device performance.More
Although advanced 14 nanometers of finfet technologies can solve photoresist (PR) topography issues using anti-reflection coating (BARC) is increased,
Also increase process costs and complexity.
Therefore, under the premise of not increasing cost and process complexity, photoresist (PR) bottom unfilled corner (Undercut) is solved
Problem, enhancing ion implanting lithographic process window become industry problem.
Summary of the invention
One of present invention is designed to provide a kind of method for enhancing semiconductor devices ion implanting lithographic process window, packet
It includes: being carried out at semiconductor device surface using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) first
Reason, then carries out photoetching process, wherein using Nitrogen element (N) and protium (H) chemical compound gas or mixed gas into
When the processing of row semiconductor device surface, the surface treatment time is 5S~120S, the compound of Nitrogen element (N) and protium (H)
The plasma temperature of gas or mixed gas is 100 DEG C~1000 DEG C.
Further, the semiconductor devices includes a gate structure, and the gate structure includes grid curb wall, described
Grid curb wall is silicon nitride material.
Further, it is arrived after the surface treatment of the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
The time of photoetching process should be less than 5h.
Further, the semiconductor devices is 28 nanometers and following technology node.
Further, the chemical compound gas or mixed gas of the Nitrogen element (N) and protium (H) be NH3,
The mixture or N2H2 of N2H4, N2H2, N2 and H2 and the mixture of H2.
Further, it is partly led using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
When the processing of body device surface, the gas flow of the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) is
500sccm~5000sccm.
One embodiment of the invention, by the compound gas for using Nitrogen element (N) and protium (H) before photoetching process
Body or mixed gas carry out semiconductor device surface processing, solve the problems, such as photoresist (PR) bottom unfilled corner (Undercut), increase
Strong ion implanting lithographic process window, optimizes device performance.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of semiconductor devices before photoetching process.
Fig. 2 is tradition O2 processing schematic before photoetching process.
Fig. 3 is the unfilled corner schematic diagram that generates after photoetching process.
Fig. 4 be one embodiment of the invention photoetching process before the schematic diagram that is surface-treated.
Fig. 5 is schematic diagram after the photoetching process of one embodiment of the invention.
The reference numerals are as follows for main element in figure:
200, gate structure；210, polysilicon gate；220, grid curb wall.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In one embodiment of the invention, a kind of method for enhancing semiconductor devices ion implanting lithographic process window, packet are provided
It includes: being carried out at semiconductor device surface using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) first
Reason, then carries out photoetching process.
It is illustrated so that ammonia (NH3) carries out semiconductor device surface processing as an example as follows, sees Fig. 4 and Fig. 5, Fig. 4
For the schematic diagram that is surface-treated before the photoetching process of one embodiment of the invention and light that Fig. 5 is one embodiment of the invention
Schematic diagram after carving technology.As shown in figure 4, handling semiconductor device surface, Zhi Houru using ammonia (NH3) before photoetching process
Shown in Fig. 5, carry out photoetching process after, in the prior art (as shown in Figure 3) photoresist bottom (PR) generation unfilled corner (Undercut)
100 disappear, and obtain ideal photoresist (PR) pattern, and then subsequent ion injects (such as LDD/Halo ion implanting and S/D ion
Injection) region that defines of photoresist is accurate, enhance ion implanting lithographic process window, and then optimized device performance.
Wherein, the semiconductor devices includes a gate structure, and gate structure includes grid curb wall, which is nitrogen
Silicon nitride material.As shown in figure 4, including gate structure 200 on substrate, gate structure 200 includes polysilicon gate 210 and grid curb wall
220, wherein grid curb wall is silicon nitride material.
In an embodiment of the present invention, the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) are it
The gas for influencing the NHx (X=0,1,2) of photoresist pattern can be generated under condition of plasma, such as NH3, N2H4, N2H2, N2 and H2
Mixture or the mixture of N2H2 and H2 etc..
In an embodiment of the present invention, using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
When carrying out semiconductor device surface processing, the gas of the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
Flow 500sccm~5000sccm, to solve the problems, such as photoresist (PR) bottom unfilled corner (Undercut).
In an embodiment of the present invention, using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
When carrying out semiconductor device surface processing, the surface treatment time is 5S~120S, to solve the bottom photoresist (PR) unfilled corner
(Undercut) problem.
In an embodiment of the present invention, the chemical compound gas or mixed gas surface of Nitrogen element (N) and protium (H)
Time after processing to photoetching process should be less than 5h, to solve the problems, such as photoresist (PR) bottom unfilled corner (Undercut).
In an embodiment of the present invention, using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
Carry out semiconductor device surface processing when, the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) etc. from
Daughter temperature is 100 DEG C~1000 DEG C.
It even fails in this way, can not only improve photoetching process patterning distortion first, simplifies OPC treatment process.And
The fluctuation even device performance of device when there is tilt-angle ion injection, can be improved.
In an embodiment of the present invention, using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
Carry out semiconductor device surface processing when, the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) etc. from
Daughter temperature is 100 DEG C~1000 DEG C and the surface treatment time is 5S~120S to solve the bottom photoresist (PR) unfilled corner
(Undercut) problem.
In an embodiment of the present invention, above-mentioned semiconductor device is 28 nanometers and following technology node.
In this way, in an embodiment of the present invention, by using Nitrogen element (N) and protium (H) before photoetching process
Chemical compound gas or mixed gas carry out semiconductor device surface processing, solve the bottom photoresist (PR) unfilled corner
(Undercut) problem enhances ion implanting lithographic process window, optimizes device performance.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (6)
1. a kind of method for enhancing semiconductor devices ion implanting lithographic process window characterized by comprising use contain first
The chemical compound gas or mixed gas of nitrogen (N) and protium (H) carry out semiconductor device surface processing, then carry out light
Carving technology, wherein semiconductor devices is carried out using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H)
When surface treatment, the surface treatment time is 5S~120S, the chemical compound gas or mixing of Nitrogen element (N) and protium (H)
The plasma temperature of gas is 100 DEG C~1000 DEG C.
2. the method for enhancing semiconductor devices ion implanting lithographic process window according to claim 1, which is characterized in that
The semiconductor devices includes a gate structure, and the gate structure includes grid curb wall, and the grid curb wall is silicon nitride material
Material.
3. the method for enhancing semiconductor devices ion implanting lithographic process window according to claim 1, which is characterized in that
Time after the surface treatment of the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H) to photoetching process answers small
In 5h.
4. the method for enhancing semiconductor devices ion implanting lithographic process window according to claim 1, which is characterized in that
The semiconductor devices is 28 nanometers and following technology node.
5. the method for enhancing semiconductor devices ion implanting lithographic process window according to claim 1, which is characterized in that
The chemical compound gas or mixed gas of the Nitrogen element (N) and protium (H) are the mixed of NH3, N2H4, N2H2, N2 and H2
Close object or the mixture of N2H2 and H2.
6. the method for enhancing semiconductor devices ion implanting lithographic process window according to claim 1, which is characterized in that
When carrying out semiconductor device surface processing using the chemical compound gas or mixed gas of Nitrogen element (N) and protium (H), contain
The gas flow of the chemical compound gas or mixed gas of nitrogen (N) and protium (H) is 500sccm~5000sccm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811632069.0A CN109712872B (en) | 2018-12-29 | 2018-12-29 | Method for enhancing ion implantation photoetching process window of semiconductor device |
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| CN201811632069.0A CN109712872B (en) | 2018-12-29 | 2018-12-29 | Method for enhancing ion implantation photoetching process window of semiconductor device |
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| CN109712872B CN109712872B (en) | 2021-02-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112382562A (en) * | 2020-11-02 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for improving photoresist morphology of ion implantation photoresist layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714037A (en) * | 1996-05-17 | 1998-02-03 | Microunity Systems Engineering, Inc. | Method of improving adhesion between thin films |
| CN1959944A (en) * | 2005-11-03 | 2007-05-09 | 联华电子股份有限公司 | Method for removing photoresist, and method for fabricating semiconductor component |
| CN101577223A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Grid, semiconductor apparatus and methods for forming grid, doped area and nitrogen-containing side wall substrate |
-
2018
- 2018-12-29 CN CN201811632069.0A patent/CN109712872B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714037A (en) * | 1996-05-17 | 1998-02-03 | Microunity Systems Engineering, Inc. | Method of improving adhesion between thin films |
| CN1959944A (en) * | 2005-11-03 | 2007-05-09 | 联华电子股份有限公司 | Method for removing photoresist, and method for fabricating semiconductor component |
| CN101577223A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Grid, semiconductor apparatus and methods for forming grid, doped area and nitrogen-containing side wall substrate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112382562A (en) * | 2020-11-02 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for improving photoresist morphology of ion implantation photoresist layer |
| CN112382562B (en) * | 2020-11-02 | 2024-03-12 | 上海华力集成电路制造有限公司 | Method for improving photoresist morphology of ion implantation photoetching layer |
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