CN101777493A - Hard mask layer etching method - Google Patents
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- CN101777493A CN101777493A CN201010102334A CN201010102334A CN101777493A CN 101777493 A CN101777493 A CN 101777493A CN 201010102334 A CN201010102334 A CN 201010102334A CN 201010102334 A CN201010102334 A CN 201010102334A CN 101777493 A CN101777493 A CN 101777493A
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Abstract
The invention discloses a hard mask layer etching method, which comprises the steps of providing a semiconductor substrate on which a hard mask layer, a bottom anti-reflection layer and a graphic light resistance layer are sequentially formed; curing the graphic light resistance layer; etching the bottom anti-reflection layer by taking the cured graphic light resistance layer as a mask so as to form a graphic bottom anti-reflection layer; and etching the hard mask layer by taking the cured graphic light resistance layer and the graphic bottom anti-reflection layer as masks so as to from a graphic hard mask layer. The invention can increase etching selection ratio, ensures that the side wall of the cured graphic light resistance layer is smoother after the bottom anti-reflection layer is etched, and improves the performance of a semiconductor device.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of hard mask layer etching method.
Background technology
Along with the continuous development of semiconductor fabrication, also more and more littler as the live width of the grid of weighing the semiconductor fabrication technological level.At present, the live width of grid can be accomplished 65nm even littler, the driving voltage of the semiconductor device that little grid live width can reduce to form, and then reduce power consumption; In addition, little grid live width also can make the dimensions of semiconductor devices of formation reduce, and improves integrated level, increases the quantity of unit are semiconductor-on-insulator device, reduces production costs.
Along with reducing of semiconductor device live width, the 193nm photoresistance replaces the 248nm photoresistance gradually, but the 193nm photoresistance is soft usually, and thickness is also thinner, in order to obtain the good grid of profile, uses hard mask layer through regular meeting in the grid manufacture process.
Specifically, use the hard mask layer etching method of 193nm photoresistance to generally include following step: at first, to provide Semiconductor substrate, be formed with hard mask layer, bottom anti-reflection layer and graphical photoresist layer on the described Semiconductor substrate successively; Then, be mask with described graphical photoresist layer, the described bottom anti-reflection layer of etching is to form the graphic bottom anti-reflection layer; Next, do mask with described graphical photoresist layer and graphic bottom anti-reflection layer, the described hard mask layer of etching is to form graphical hard mask layer.
In order to obtain preferable profile, what adopt usually during the described bottom anti-reflection layer of etching is dry etching, described dry etching can be divided into chemical etching (Chemical Etching), physical property etching (Physical Etching) and reactive ion etching (RIE) according to the principle that etching produces.Wherein, the chemical etching mainly is that atomic group (Radicals) or reactive (Reactive) ion that utilizes plasma (plasma) to produce carries out etching with the layer generation activity chemistry reaction that is etched.The physical property etching be meant that utilization is starched by electricity and cathode electrode between the positively charged ion that quickens of potential difference, and bombardment electrode plate surface, this phenomenon is called " ion bombardment ", is also referred to as ise.Reactive ion etching is the main flow lithographic technique between chemical etching and physical property etching, obtains a balance point between rerum natura and voltinism.Wherein, during the described bottom anti-reflection layer of dry etching, the etching gas of employing can be the mist of carbon tetrafluoride and hydrogen bromide, perhaps is the mist of hydrogen bromide and oxygen.
Yet, in actual production, find, no matter adopt above-mentioned which kind of dry etch process, after the etching bottom anti-reflection layer, because the influence of the ion that uses in the dry etching, the sidewall surfaces of graphical photoresist layer become very coarse (roughness), this coarse surface can cause grid rough of follow-up formation, and the etching selection of above-mentioned hard mask layer etching method is lower, and then causes the leakage current of semiconductor device to increase decreased performance.
Summary of the invention
The invention provides a kind of hard mask layer etching method, lower with the selection that solves existing lithographic method, and after the etching bottom anti-reflection layer, the comparatively coarse problem of sidewall surfaces of graphical photoresist layer.
For solving the problems of the technologies described above, the invention provides a kind of hard mask layer etching method, comprising: Semiconductor substrate is provided, is formed with hard mask layer, bottom anti-reflection layer and graphical photoresist layer on the described Semiconductor substrate successively; Solidify described graphical photoresist layer; With the graphical photoresist layer after solidifying is mask, and the described bottom anti-reflection layer of etching is to form the graphic bottom anti-reflection layer; Do mask with graphical photoresist layer after the described curing and graphic bottom anti-reflection layer, the described hard mask layer of etching is to form graphical hard mask layer.
Further, utilize bromize hydrogen gas to solidify described graphical photoresist layer.
Further, described bottom anti-reflection layer is the organic bottom antireflective layer, the etching gas that is adopted during the described bottom anti-reflection layer of etching is carbon tetrafluoride and titanium dioxide helium, it is characterized in that, the gas ratio of described carbon tetrafluoride and titanium dioxide helium is 9: 1～17: 1, and the pressure during the described bottom anti-reflection layer of etching in the reative cell is lower than 6mTorr.
Further, the material of described hard mask layer is a silicon nitride.
Further, the thickness of described hard mask layer is 1800～2200
The thickness of described bottom anti-reflection layer is 700～900
The thickness of described graphical photoresist layer is 2600～3000
Compared with prior art, hard mask layer etching method provided by the invention has the following advantages:
The present invention is before the etching bottom anti-reflection layer, increased the step of solidifying graphical photoresist layer, this curing schedule can make the surface hardening of described graphical photoresist layer, thereby increase resistance to follow-up etch step of carrying out, improved etching selection ratio, after guaranteeing the etching bottom anti-reflection layer, the sidewall of the graphical photoresist layer after the curing is comparatively smooth, and the thickness of the graphical photoresist layer after remaining curing after the etching is bigger;
In addition, during the described bottom anti-reflection layer of etching of the present invention, the etching gas that is adopted is carbon tetrafluoride and titanium dioxide helium, the gas ratio of described carbon tetrafluoride and titanium dioxide helium is 9: 1～17: 1, help making the sidewall of the graphical photoresist layer after the etch step smooth, improved the performance of semiconductor device.
Description of drawings
Fig. 1 is the flow chart of the hard mask layer etching method that the embodiment of the invention provided;
Fig. 2 A to Fig. 2 D is the generalized section of each step corresponding construction of the hard mask layer etching method that the embodiment of the invention provided.
Embodiment
Please refer to Fig. 1, it is the flow chart of the hard mask layer etching method that the embodiment of the invention provided, and in conjunction with this figure, this lithographic method may further comprise the steps:
Step S10 provides Semiconductor substrate, is formed with hard mask layer, bottom anti-reflection layer and graphical photoresist layer on the described Semiconductor substrate successively;
Step S11 solidifies described graphical photoresist layer;
Step S12 is a mask with the graphical photoresist layer after solidifying, and the described bottom anti-reflection layer of etching is to form the graphic bottom anti-reflection layer;
Step S13 does mask with graphical photoresist layer after the described curing and graphic bottom anti-reflection layer, and the described hard mask layer of etching is to form graphical hard mask layer.
The present invention is before the described bottom anti-reflection layer of etching, increased the step of solidifying graphical photoresist layer, this curing schedule can make the surface hardening of graphical photoresist layer, thereby increase resistance to follow-up etch step of carrying out, improved etching selection ratio, after guaranteeing the etching bottom anti-reflection layer, the sidewall of the graphical photoresist layer after the curing is comparatively smooth, and the thickness of the graphical photoresist layer after remaining curing after the etching is bigger.
Below in conjunction with generalized section hard mask layer etching method of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should the described those skilled in the art of understanding can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
With reference to figure 2A, at first, provide Semiconductor substrate 200, be formed with hard mask layer 230, bottom anti-reflection layer 240 and graphical photoresist layer 250 on this Semiconductor substrate 200 successively.
In specific embodiment of the present invention, hard mask layer 230 is to be used to make grid, therefore, on described Semiconductor substrate 200, also be formed with gate dielectric 210 and be positioned at grid conducting layer 220 on the gate dielectric 210, wherein, hard mask layer 230, bottom anti-reflection layer 240 and graphical photoresist layer 250 are to be positioned at successively on the grid conducting layer 220.
The material of described gate dielectric 210 can be silica, and the material of grid conducting layer 220 can be polysilicon.Resistivity for the grid that reduces to form, can also in grid conducting layer 220, mix impurity, for example, can mix phosphorus or arsenic as in the polysilicon of N type metal oxide semiconductor transistor gate, in being used as the polysilicon of P-type mos transistor gate, can mix the compound of boron or boron.Preferable, described gate dielectric 210 and grid conducting layer 220 can form by the boiler tube depositional mode.
In a specific embodiment of the present invention, the material of described hard mask layer 230 is a silicon nitride, and described hard mask layer 230 can form by the chemical vapour deposition (CVD) mode; Described bottom anti-reflection layer 240 is the organic bottom antireflective layer, and it can form by the mode of spin coating.
Described graphical photoresist layer 250 can form by following steps; At first, spin coating photoresistance on bottom anti-reflection layer 240, described photoresistance are the photoresistance of 193nm; Then, can form graphical photoresist layer 250 by technologies such as exposure and developments, described bottom anti-reflection layer 240 can be eliminated or reduce in exposure technology, and reverberation is to the influence of the profile of graphical photoresist layer 250.
In a specific embodiment of the present invention, the thickness of hard mask layer 230 is thicker, for example, hard mask layer 230 can be 1800～2200
The thickness of bottom anti-reflection layer 240 is 700～900
And the thickness of graphical photoresist layer 250 only is 2600～3000
With reference to figure 2B, committed step of the present invention is, after forming graphical photoresist layer 250, solidifies described graphical photoresist layer 250, and to form the graphical photoresist layer 250a after solidifying, described curing schedule can make the surface hardening of graphical photoresist layer 250.
Described curing schedule is finished in etching machine bench, when carrying out this curing schedule, pressure in the reative cell of etching machine bench is lower than 6mTorr, substrate bias power is 0V, can utilize bromize hydrogen gas to solidify graphical photoresist layer 250, described bromize hydrogen gas can with the surface reaction of graphical photoresist layer 250, make the surface hardening of graphical photoresist layer 250, thereby increase resistance to follow-up etch step of carrying out, improve etching selection ratio, after guaranteeing etching bottom anti-reflection layer 240 steps, the sidewall of the graphical photoresist layer 250a after the curing is comparatively smooth, and degree of roughness reduces.
Yet will be appreciated that, in other specific embodiment of invention, also can utilize alternate manner to solidify graphical photoresist layer, for example, can utilize modes such as ultraviolet curing, electron beam treatment or hot curing to solidify described graphical photoresist layer.
With reference to figure 2C, and in conjunction with Fig. 2 B, be mask with the graphical photoresist layer 250a after solidifying, etching bottom anti-reflection layer 240 is to form graphic bottom anti-reflection layer 240a.
Because before etching bottom anti-reflection layer 240 steps, increased the step of solidifying graphical photoresist layer 250, make the surface hardening of graphical photoresist layer 250, increased resistance to follow-up etch step of carrying out, after can guaranteeing etching bottom anti-reflection layer 240 steps, the sidewall of the graphical photoresist layer 250a after the curing is comparatively smooth; And, because the hardness of the graphical photoresist layer 250a after solidifying is bigger, improved etching selection ratio, can guarantee that after etching bottom anti-reflection layer 240 steps, the thickness of the graphical photoresist layer 250a after the remaining curing is greater than 200
Guarantee that it can be used as the mask layer in follow-up etching hard mask layer 230 steps of carrying out.
At a specific embodiment of the present invention, during etching bottom anti-reflection layer 240, pressure in the reative cell of etching apparatus is lower than 6mTorr, the etching gas that is adopted is carbon tetrafluoride and titanium dioxide helium, the gas ratio of described carbon tetrafluoride and titanium dioxide helium is 9: 1～17: 1, utilize the carbon tetrafluoride and the titanium dioxide helium of this gas ratio to come etching carbon tetrafluoride and titanium dioxide helium, help making the sidewall of the graphical photoresist layer after the etch step comparatively smooth, and then improved the performance of semiconductor device.
With reference to figure 2D, and in conjunction with Fig. 2 C, next, do mask with graphical photoresist layer 250a and graphic bottom anti-reflection layer 240a after solidifying, etching hard mask layer 230 is to form graphical hard mask layer 230a.Because the hardness of the graphical photoresist layer 250a after solidifying is bigger, improved etching selection ratio, and the sidewall of graphical photoresist layer 250a is comparatively smooth, therefore, although the thickness of hard mask layer 230 is bigger, still can form the preferable graphical hard mask layer 230a of profile.
Need to prove that in above-mentioned specific embodiment, described hard mask layer 230a is used to form grid, yet will be appreciated that, in other embodiment of the present invention, described hard mask layer also can be used for making other semiconductor device structure.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. hard mask layer etching method comprises:
Semiconductor substrate is provided, is formed with hard mask layer, bottom anti-reflection layer and graphical photoresist layer on the described Semiconductor substrate successively;
Solidify described graphical photoresist layer;
With the graphical photoresist layer after solidifying is mask, and the described bottom anti-reflection layer of etching is to form the graphic bottom anti-reflection layer;
Do mask with graphical photoresist layer after the described curing and graphic bottom anti-reflection layer, the described hard mask layer of etching is to form graphical hard mask layer.
2. hard mask layer etching method as claimed in claim 1 is characterized in that, utilizes bromize hydrogen gas to solidify described graphical photoresist layer.
3. hard mask layer etching method as claimed in claim 1 or 2 is characterized in that, described bottom anti-reflection layer is the organic bottom antireflective layer.
4. hard mask layer etching method as claimed in claim 3 is characterized in that, the etching gas that is adopted during the described bottom anti-reflection layer of etching is carbon tetrafluoride and titanium dioxide helium.
5. hard mask layer etching method as claimed in claim 4 is characterized in that, the gas ratio of described carbon tetrafluoride and titanium dioxide helium is 9: 1～17: 1.
6. hard mask layer etching method as claimed in claim 5 is characterized in that, the pressure during the described bottom anti-reflection layer of etching in the reative cell is lower than 6mTorr.
7. hard mask layer etching method as claimed in claim 1 is characterized in that, the material of described hard mask layer is a silicon nitride.
8. hard mask layer etching method as claimed in claim 7 is characterized in that the thickness of described hard mask layer is
9. hard mask layer etching method as claimed in claim 8 is characterized in that the thickness of described bottom anti-reflection layer is
10. hard mask layer etching method as claimed in claim 9 is characterized in that the thickness of described graphical photoresist layer is
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| CN201010102334A CN101777493A (en) | 2010-01-28 | 2010-01-28 | Hard mask layer etching method |
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Cited By (8)
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| CN102148184A (en) * | 2011-03-15 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for improving roughness of side wall of shallow trench isolation |
| CN102468139A (en) * | 2010-11-03 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Patterning methodology for uniformity control |
| CN104681416A (en) * | 2013-11-27 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method for semiconductor device and grid electrode |
| CN104681417A (en) * | 2013-11-27 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device and grid electrode |
| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN105470120A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Polysilicon etching method |
| CN109216164A (en) * | 2017-06-30 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Patterned mask layer and forming method thereof |
| CN111769037A (en) * | 2020-05-29 | 2020-10-13 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
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| CN102468139A (en) * | 2010-11-03 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Patterning methodology for uniformity control |
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| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN105470120A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Polysilicon etching method |
| CN109216164A (en) * | 2017-06-30 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Patterned mask layer and forming method thereof |
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| CN111769037A (en) * | 2020-05-29 | 2020-10-13 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
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