CN101567313A - Grid manufacturing method - Google Patents
Grid manufacturing method Download PDFInfo
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- CN101567313A CN101567313A CNA2009100525456A CN200910052545A CN101567313A CN 101567313 A CN101567313 A CN 101567313A CN A2009100525456 A CNA2009100525456 A CN A2009100525456A CN 200910052545 A CN200910052545 A CN 200910052545A CN 101567313 A CN101567313 A CN 101567313A
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Abstract
The invention discloses a grid manufacturing method which comprises the steps of: providing a substrate; forming a gate oxide, a polycrystalline silicon layer, a hard masking layer and a patterning photoresist layer sequentially on the substrate; etching the hard masking layer to form a patterning hard masking layer by taking the patterning photoresist layer as a mask, and removing a part of the patterning photoresist layer simultaneously; etching the polycrystalline silicon layer and the gate oxide by taking the residual patterning photoresist layer and the patterning hard masking layer as a mask, simultaneously removing the residual patterning photoresist layer completely and removing a part of the patterning hard masking layer; and forming a grid by removing the residual patterning hard masking layer. The method can avoid the occurrence of photoresist residue, improve the yield of a semiconductor device, saves production cost and improve production efficiency.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of grid production method.
Background technology
When semiconductor device processing technology developed into deep-submicron (deep submicron) technology, the integrated level of integrated circuit was more and more higher, and size of semiconductor device is more and more littler, and the size of grid is also more and more littler.At present, semiconductor device generally adopts the material of polysilicon as grid.
Detailed, please refer to Figure 1A to Fig. 1 E, it is the generalized section of each step corresponding construction of existing grid production method.
At first, shown in Figure 1A, on substrate 110, form gate oxide 120, polysilicon layer 130 and hard mask layer 140, and on described hard mask layer 140, form photoresist layer.Along with constantly reducing of grid size, the thickness of photoresist layer is also more and more thinner, and in general, the thickness of photoresist layer only is several thousand dusts.Then, by photoetching and developing process, form patterning photoresist layer 151.
Then, shown in Figure 1B, be mask with described patterning photoresist layer 151, the described hard mask layer 140 of dry etching forms patterning hard mask layer 141.The material of described hard mask layer 140 can be silicon dioxide or silicon oxynitride.Because the etching gas that etching hard mask layer 140 is adopted also has corrasion to photoresistance, therefore in this step, described patterning photoresist layer 151 also is etched away a part.
Then, shown in Fig. 1 C,, remove remaining patterning photoresist layer 152 by the mode of oxygen plasma ashing.
Next, shown in Fig. 1 D, be mask with described patterning hard mask layer 141, dry etching polysilicon layer 130 and gate oxide 120, simultaneously, described patterning hard mask layer 141 also is etched away a part.
At last, shown in Fig. 1 E, utilize the wet method mode to remove remaining hard mask layer 142, to form grid structure.
At present, industry is utilized the described hard mask layer of same etch chamber etching, polysilicon layer and gate oxide usually, and utilize this etch chamber to remove remaining patterning photoresist layer, yet, mode by the oxygen plasma ashing removes in the process of photoresistance and very easily produces the photoresistance residue, and these photoresistance residues influence normally carrying out of subsequent etching process attached to wafer surface or etch chamber inside, cause etching to abend, reduced the yield of semiconductor device.
But, if select independent equipment to remove photoresistance,, increased production cost, and needed wafer is transferred to another equipment from a cavate though can avoid occurring defective such as photoresistance residue, prolonged the process time.
Summary of the invention
The invention provides a kind of grid production method, can avoid occurring photoresistance residue phenomenon, improve the yield of semiconductor device, and can shorten the process time, reduce production costs, enhance productivity.
For solving the problems of the technologies described above, the invention provides a kind of grid production method, comprising: a substrate is provided; On described substrate, form gate oxide, polysilicon layer, hard mask layer and patterning photoresist layer successively; With described patterning photoresist layer is mask, and the described hard mask layer of etching forms the patterning hard mask layer, and described patterning photoresist layer is partly removed simultaneously; With remaining patterning photoresist layer and described patterning hard mask layer is mask, described polysilicon layer of etching and gate oxide, and described remaining patterning photoresist layer is removed fully simultaneously, and described patterning hard mask layer is partly removed; Remove remaining patterning hard mask layer, form grid.
Further, the material of described hard mask layer is silicon dioxide or silicon oxynitride.
Further, the thickness of described patterning photoresist layer is 2600～2800 dusts.
Further, remove remaining patterning hard mask layer by the wet method mode.
Can draw from above technical scheme, compared with prior art, the present invention has the following advantages:
Grid production method provided by the present invention, in the process of etching hard mask layer, remove the part photoresistance, and in the process of described polysilicon layer of etching and gate oxide, remove remaining photoresistance, save the step that removes photoresistance, saved production cost, improved production efficiency, also avoid simultaneously the appearance of photoresistance residue phenomenon, improved the yield of semiconductor device.
Description of drawings
Figure 1A～1E is the generalized section of each step corresponding construction of existing grid production method;
Fig. 2 is the flow chart of the grid production method that one embodiment of the invention provided;
Fig. 3 A～3D is the generalized section of each step corresponding construction of the grid production method that one embodiment of the invention provided.
Embodiment
For purpose of the present invention, feature are become apparent, the specific embodiment of the present invention is further described below in conjunction with accompanying drawing.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of aid illustration one embodiment of the invention lucidly.
Core concept of the present invention is, save the step that removes photoresistance, but in the process of etching hard mask layer, remove a part of patterning photoresist layer, and in the process of etch polysilicon layer and gate oxide, remove remaining patterning photoresist layer, saved production cost, improved production efficiency, simultaneously also can avoid the photoresistance residue occurring, improve the yield of semiconductor device.
Please refer to Fig. 2, it is the flow chart of the grid production method that one embodiment of the invention provided, and in conjunction with this figure, the method comprising the steps of:
Below in conjunction with generalized section grid production method of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
Fig. 3 A～3D is the generalized section of each step corresponding construction of the grid production method that one embodiment of the invention provided.
With reference to Fig. 3 A, at first, provide semi-conductive substrate 310, on described substrate 310, form gate oxide 320, polysilicon layer 330, hard mask layer 340 successively.The material of described Semiconductor substrate 310 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, the material of described gate oxide 320 can be a kind of or combination in silicon dioxide, the silicon oxynitride, and the material of described hard mask layer 340 can be silicon dioxide or silicon oxynitride.Preferably, described hard mask layer 340 is a silicon dioxide, can form by the mode of thermal oxidation or chemical vapour deposition (CVD).
On described hard mask layer 340, be formed with photoresist layer, and, form patterning photoresist layer 351 by photoetching and developing process.Because the size of grid is more and more littler, so the thickness of photoresist layer also constantly reducing, and for example, for the photoresistance of 193nm, the thickness of described patterning photoresist layer only is 2600～2800 dusts.
With reference to figure 3B, be mask with described patterning photoresist layer 351, the described hard mask layer 340 of etching forms a patterning hard mask layer 341.
In order to obtain preferable edge contour, what described etching process generally adopted is dry etching, described dry etching can be divided into chemical etching (Chemical Etching), physical property etching (Physical Etching) and reactive ion etching (RIE) according to the principle that etching produces.Wherein, the chemical etching mainly is that atomic group (Radicals) or reactive (Reactive) ion that utilizes plasma (plasma) to produce carries out etching with the layer generation activity chemistry reaction that is etched.The physical property etching be meant that utilization is starched by electricity and cathode electrode between the positively charged ion that quickens of potential difference, and bombardment electrode plate surface, this phenomenon is called " ion bombardment ", is also referred to as ise.Reactive ion etching is the main flow lithographic technique between chemical etching and physical property etching, obtains a balance point between rerum natura and voltinism, finds out optimum process parameters.
In etching process, these retes that do not need originally to be etched of the material that blocks material (as photoresistance and hard mask layer) or lower floor of the upper layer of material that is etched also can suffer etching simultaneously, an important target of etching procedure obtains high selectivity exactly, the so-called selection than the ratio that is etch rate between the different material.But no matter utilize above-mentioned which kind of etching mode, can't guarantee that also photoresistance is not etched fully.Therefore in actual etching process, in the time of the described hard mask layer of etching 340, described patterning photoresist layer 351 also is etched away a part.
With reference to figure 3C, be mask with remaining patterning photoresist layer 352 and patterning hard mask layer 341, described polysilicon layer 330 of etching and gate oxide 320.
Simultaneously, described patterning hard mask layer 341 is etched away a part, because photoresist layer is extremely thin, so remaining patterning photoresist layer 352 can be removed fully, therefore need not to increase photoresistance in addition removes step, has saved cost, has improved production efficiency, also can avoid simultaneously the appearance of photoresistance residue phenomenon, improve the yield of semiconductor device.
With reference to figure 3D, last, remove remaining patterning hard mask layer 342 by the wet method mode, to form grid structure.Preferably, can utilize hydrofluoric acid to remove remaining patterning hard mask layer 342, those skilled in the art can be known concrete technological parameter by experiment, and the present invention will not limit.
In sum, the present invention has saved the step that removes photoresistance, but in the process of etching hard mask layer, remove partially patterned photoresist layer, and in the process of etch polysilicon layer and gate oxide, remove remaining patterning photoresist layer, saved cost, improved production efficiency, also avoid simultaneously the appearance of photoresistance residue phenomenon, improved the yield of semiconductor device.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (4)
1, a kind of grid production method comprises:
One substrate is provided;
On described substrate, form gate oxide, polysilicon layer, hard mask layer and patterning photoresist layer successively;
With described patterning photoresist layer is mask, and the described hard mask layer of etching forms the patterning hard mask layer, and described patterning photoresist layer is partly removed simultaneously;
With remaining patterning photoresist layer and described patterning hard mask layer is mask, described polysilicon layer of etching and gate oxide, and described remaining patterning photoresist layer is removed fully simultaneously, and described patterning hard mask layer is partly removed;
Remove remaining patterning hard mask layer, form grid.
2, grid production method as claimed in claim 1 is characterized in that, the material of described hard mask layer is silicon dioxide or silicon oxynitride.
3, grid production method as claimed in claim 1 is characterized in that, the thickness of described patterning photoresist layer is 2600～2800 dusts.
4, grid production method as claimed in claim 1 is characterized in that, removes remaining patterning hard mask layer by the wet method mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100525456A CN101567313A (en) | 2009-06-04 | 2009-06-04 | Grid manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100525456A CN101567313A (en) | 2009-06-04 | 2009-06-04 | Grid manufacturing method |
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| CN101567313A true CN101567313A (en) | 2009-10-28 |
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| CNA2009100525456A Pending CN101567313A (en) | 2009-06-04 | 2009-06-04 | Grid manufacturing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270573A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid |
| CN102890150A (en) * | 2012-09-20 | 2013-01-23 | 上海集成电路研发中心有限公司 | Manufacturing method of silicon nanowire arrays in biological chips |
| CN103681497A (en) * | 2012-09-04 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Production method for semiconductor device |
| CN111649912A (en) * | 2020-06-02 | 2020-09-11 | 兰州空间技术物理研究所 | Accelerated life test method for ion thruster |
-
2009
- 2009-06-04 CN CNA2009100525456A patent/CN101567313A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270573A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid |
| CN103681497A (en) * | 2012-09-04 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Production method for semiconductor device |
| CN103681497B (en) * | 2012-09-04 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of semiconductor devices |
| CN102890150A (en) * | 2012-09-20 | 2013-01-23 | 上海集成电路研发中心有限公司 | Manufacturing method of silicon nanowire arrays in biological chips |
| CN102890150B (en) * | 2012-09-20 | 2016-08-24 | 上海集成电路研发中心有限公司 | The manufacture method of silicon nanowire array in a kind of biochip |
| CN111649912A (en) * | 2020-06-02 | 2020-09-11 | 兰州空间技术物理研究所 | Accelerated life test method for ion thruster |
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Application publication date: 20091028 |