CN102543713B

CN102543713B - Method for etching oxide silicon grid compensating isolation region

Info

Publication number: CN102543713B
Application number: CN201210047386.2A
Authority: CN
Inventors: 杨渝书; 李程; 陈玉文
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2012-02-28
Filing date: 2012-02-28
Publication date: 2014-05-28
Anticipated expiration: 2032-02-28
Also published as: CN102543713A

Abstract

The invention relates to the manufacturing field of semi-conductors, and particularly relates to a method for etching an oxide silicon grid compensating isolation region. The method is realized by improving the plasma oxide silicon grid compensating isolation region etching technology, the non-plasmas oxide silicon etching technology is realized by adopting the diluted hydrofluoric acid (DHF) wet etching process, and is integrated with the etched polymer cleaning technology, that is, a DHF trough is added to a wet cleaning acid trough to achieve no plasma damage and the etching technology with high etching selection ratio (oxide silicon to silicon) under the condition that technological machines and steps are not increased, thereby reducing etching loss of silicon substrates.

Description

A kind of method of etching silicon oxide gate compensation isolation area

Technical field

The present invention relates to semiconductor integrated circuit and manufacture field thereof, relate in particular to a kind of method of etching silicon oxide gate compensation isolation area.

Background technology

Along with the integrated level of integrated circuit improves constantly, the develop rapidly that semiconductor technology also continues.In semiconductor technology, the etching of silica grid compensation isolated area is the key technique that is related to transistor service behaviour, and general traditional handicraft method is completed by the plasma dry etching of anisotropic, its etching technics has main etching and two steps of over etching; That wherein, main etching processing step mainly adopts is C ₄f ₈/ O ₂the mist of/Ar is mainly to utilize CF active group to complete the etching to silica, due to C ₄f ₈so be high-carbon fluorine can keep the etch rate of silica to silicon in etching process high selectivity than gas, and O ₂as clean air, the polymer that energy cleaning reaction generates, to make reaction keep certain etch rate, Ar destroys the keyed jointing of silicon oxide surface as bombarding ion, and adopts the method for etching terminal detecting (endpoint) to judge the situation of oxide removal; Over etching processing step is mainly used for the residual oxide of open area to carry out etching removal, and finally forms qualified compensation isolated area pattern, general employing and the chemical gas of main etching processing step identical type, but gas ratio changes, both C ₄f ₈increase clean air O ₂reduce, and the bias voltage radio-frequency power of leading anisotropic etching reduces, impel etching characteristic to more high selectivity (silica is to silicon) and isotropic etching future development, to reduce the etching of silicon substrate and to form final pattern, over etching generally adopts timing controlled.

Fig. 1-4th, the method structural representation of conventional oxidation silicon gate compensation isolated area etching (oxide offset spacer); As Figure 1-4, the method of conventional oxidation silicon gate compensation isolated area etching (oxide offset spacer) includes following processing step: first, silicon oxide layer deposited 13 on the silicon substrate 11 that is provided with polysilicon gate (poly gate) 14 and gate oxide level (gate oxide) 12, with the upper surface of cover gate oxide layer 12 and sidewall and the upper surface thereof of polysilicon gate 14; Then, adopt main etching technique to remove the silicon oxide layer that covers polysilicon gate 14 and grid oxic horizon 13 upper surfaces, and silicon oxide layer on part polysilicon gate 14 sidewalls, side wall 131 formed; Afterwards, adopt over etching technique to remove the pad oxide and the partial silicon substrate that are not covered by side wall 131 and polysilicon gate 14, in etching process, can on remaining silicon substrate 111, be formed with polymer (polymer) 15; Finally, carry out the cleaning of polymer 15.

But, in conventional oxidation silicon gate compensation isolated area lithographic method, because silica etching is a kind of process of being partial to physical etchings, in etching process, be difficult to reach the high etching selection ratio of silica to silicon, general selection than in 10, this just causes in silica over etching process, can form more loss to silicon substrate below, thereby the performance of device is had a negative impact; In addition, the use of the characteristic of plasma dry etching (Ions Bombardment) and oxygen, determines that it can cause damage (plasma damage) and oxidation to a certain degree to silicon substrate in etching process, and then the loss that has strengthened silicon substrate.

Summary of the invention

The invention discloses a kind of method of etching silicon oxide gate compensation isolation area, wherein, comprise the following steps:

Step S1: there is silicon oxide layer deposited on the silicon substrate of polysilicon gate one;

Step S2: using plasma dry etching method carries out the main etching technique of silicon oxide layer;

Step S3: the polymer that chemical cleaning step S2 produces, and adopt diluted hydrofluoric acid wet etching to carry out over etching technique, to remove the remaining silicon oxide layer of step S2, form grid compensation isolated area pattern.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, also deposits grid oxic horizon on the silicon substrate of the described polysilicon gate in described step S1.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, described grid oxic horizon covers the upper surface of described silicon substrate, described polysilicon gate part covers the upper surface of described grid oxic horizon, and described silicon oxide layer covers the upper surface of described grid oxic horizon and the sidewall of described polysilicon gate and the upper surface thereof that are not covered by described polysilicon gate.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, the material of described silicon oxide layer is silicon dioxide.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, the mist that adopts dry plasma etch in described step S2 is C4F8/O2/Ar, and pressure is 10-30mT, and RF power is 200-700W.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, time timing controlled in described step S2, etched portions silicon oxide layer, formation silica residual layer, to prevent that plasma etching from damaging described silicon substrate.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, the thickness of described silica residual layer is 25-35A.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, in described step S3, chemical cleaning is wet-cleaned.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, adopts diluted hydrofluoric acid groove to carry out the cleaning of polymer in described step S3.

The method of above-mentioned etching silicon oxide gate compensation isolation area, wherein, controls the etch rate of silica by adjusting the concentration of hydrofluoric acid in described step S3, to prevent the over etching of its sidewall to silica compensation isolated area.

In sum, owing to having adopted technique scheme, the present invention proposes a kind of method of etching silicon oxide gate compensation isolation area, by the improvement of plasma etching silicon oxide gate compensation isolation area technique, adopt diluted hydrofluoric acid (Dilute Hydrofluoric Acid, be called for short DHF) silicon nitride process of wet etching non-plasma, and be integrated in the polymer cleaning after etching, in wet-cleaned acid tank, increase DHF groove, thereby reach in the situation that not increasing technique board and step, realize without plasma damage, and the etching technics of silica to the high etching selection ratio of silicon, thereby reduce the etching loss of silicon substrate.

Accompanying drawing explanation

Fig. 1-4th, the method structural representation of conventional oxidation silicon gate compensation isolated area etching (oxide offset spacer);

Fig. 5-8th, the structural representation of the method for etching silicon oxide gate compensation isolation area of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:

As shown in Fig. 5-8, the method for a kind of etching silicon oxide gate compensation isolation area of the present invention, concrete comprises the following steps:

First, there is silicon oxide layer deposited 23 on the silicon substrate 21 of polysilicon gate 24 one; Wherein, the upper surface of silicon substrate 21 is coated with grid oxic horizon 22, the upper surface of polysilicon gate 24 part cover gate oxide layers 22, the silicon oxide layer 23 of deposition covers the upper surface of the grid oxic horizon 22 not covered by polysilicon gate 24 and sidewall and the upper surface thereof of polysilicon gate 24, and the material of silicon oxide layer 23 is silicon dioxide (SiO preferably ₂).

Then, adopt mist C ₄f ₈/ O ₂/ Ar, the pressure of 10-30mT, the RF power of 200-700W, carries out plasma dry etching, so that silicon oxide layer is carried out to main etching technique, by utilizing anisotropic etching feature, to begin to take shape compensation isolated area pattern, and by the timing controlled to etch period, retain certain silicon oxide layer, form silica residual layer 231, prevent plasma etching damage silicon substrate 21; Wherein, the thickness of silica residual layer is 25-35A, preferably 30A.

Finally, adopt the polymer 25 producing in the above-mentioned dry plasma etch technique of chemical cleaning, and adopt diluted hydrofluoric acid (DHF) wet etching to carry out over etching technique, to remove silica residual layer 231, form grid compensation isolated area pattern.

Wherein, in chemical cleaning technology, adopt wet clean process, and be provided with diluted hydrofluoric acid groove with cleaning cleaning polyalcohol 25, and in the technique of removal silica residual layer 231, control the etch rate of silica by adjusting the concentration of hydrofluoric acid, to prevent the over etching of its sidewall 232 to silica compensation isolated area.

In sum, owing to having adopted technique scheme, the present invention proposes a kind of method of etching silicon oxide gate compensation isolation area, by the improvement of plasma etching silicon oxide gate compensation isolation area technique, adopt the silicon oxide etching technique of diluted hydrofluoric acid wet etching non-plasma, and be integrated in the polymer cleaning after etching, in wet-cleaned acid tank, increase DHF groove, thereby reach in the situation that not increasing technique board and step, realize without plasma damage, and the etching technics of silica to the high etching selection ratio of silicon (silica: silicon > 100:1), thereby reduce the etching loss of silicon substrate, finally improve product yield and reduced production cost.

By explanation and accompanying drawing, provide the exemplary embodiments of the ad hoc structure of embodiment, based on spirit of the present invention, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, but these contents are not as limitation.

For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.

Claims

1. a method for etching silicon oxide gate compensation isolation area, is characterized in that, comprises the following steps:

Step S3: the polymer that chemical cleaning step S2 produces, and adopt diluted hydrofluoric acid wet etching to carry out over etching technique, to remove the remaining silicon oxide layer of step S2, form grid compensation isolated area pattern;

Wherein, the main etching technique described in step S2 is anisotropic etching.

2. the method for etching silicon oxide gate compensation isolation area according to claim 1, is characterized in that, also deposits grid oxic horizon on the silicon substrate of the described polysilicon gate in described step S1.

3. the method for etching silicon oxide gate compensation isolation area according to claim 2, it is characterized in that, described grid oxic horizon covers the upper surface of described silicon substrate, described polysilicon gate part covers the upper surface of described grid oxic horizon, and described silicon oxide layer covers the upper surface of described grid oxic horizon and the sidewall of described polysilicon gate and the upper surface thereof that are not covered by described polysilicon gate.

4. according to the method for the etching silicon oxide gate compensation isolation area described in any one in claims 1 to 3, it is characterized in that, the material of described silicon oxide layer is silicon dioxide.

5. the method for etching silicon oxide gate compensation isolation area according to claim 4, is characterized in that, the mist that adopts dry plasma etch in described step S2 is C ₄f ₈/ O ₂/ Ar, pressure is 10-30mT, RF power is 200-700W.

6. the method for etching silicon oxide gate compensation isolation area according to claim 5, it is characterized in that time timing controlled in described step S2, etched portions silicon oxide layer, form silica residual layer, to prevent that plasma etching from damaging described silicon substrate.

7. the method for etching silicon oxide gate compensation isolation area according to claim 6, is characterized in that, the thickness of described silica residual layer is 25-35A.

8. the method for etching silicon oxide gate compensation isolation area according to claim 1, is characterized in that, in described step S3, chemical cleaning is wet-cleaned.

9. the method for etching silicon oxide gate compensation isolation area according to claim 8, is characterized in that, adopts diluted hydrofluoric acid groove to carry out the cleaning of polymer in described step S3.

10. the method for etching silicon oxide gate compensation isolation area according to claim 9, it is characterized in that, in described step S3, control the etch rate of silica by adjusting the concentration of hydrofluoric acid, to prevent the over etching of its sidewall to silica compensation isolated area.