CN102479716B - Manufacturing method of transistor - Google Patents
Manufacturing method of transistor Download PDFInfo
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- CN102479716B CN102479716B CN201010565896.XA CN201010565896A CN102479716B CN 102479716 B CN102479716 B CN 102479716B CN 201010565896 A CN201010565896 A CN 201010565896A CN 102479716 B CN102479716 B CN 102479716B
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- sacrifice layer
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Abstract
The invention provides a manufacturing method of a transistor. The method comprises the following steps: providing a semiconductor substrate which is formed with a sacrificial layer and a dummy grid in order, wherein, spacers are formed on the semiconductor substrate at two sides of the sacrificial layer and the dummy grid; forming a source region and a drain region in the semiconductor substrate at the two sides of the dummy grid and the spacers; forming an interlayer dielectric layer which is level with the dummy grid on the semiconductor substrate; removing the dummy grid and the sacrificial layer, and forming a groove which is exposed from the semiconductor substrate; forming a gate dielectric layer at a bottom of the groove; forming a high-K dielectric layer on a sidewall of the groove and the gate dielectric layer respectively; forming a metal grid on the high-K dielectric layer in the groove, wherein, the metal grid is level with the interlayer dielectric layer. The gate dielectric layer of the present invention has a complete structure, adhesiveness between the high-K dielectric layer and the gate dielectric layer is raised, leakage current of the transistor is reduced, and stability of the transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the manufacture method of transistor.
Background technology
Along with integrated circuit feature size is contracted to the field of deep-submicron, the grid size of transistor reduces, and the thickness correspondingly as the silicon dioxide layer of gate dielectric layer also needs to reduce, and to improve the grid capacitance of transistor, prevents device from occurring short-channel effect.But when gate dielectric layer thickness reduces gradually, the thickness of gate dielectric layer is decreased to below 3 nanometers, produces a lot of problem thereupon, such as: (1) leakage current increases; (2), namely there is impurity concentration gradient between gate dielectric layer and Semiconductor substrate in Impurity Diffusion, described impurity can be diffused in Semiconductor substrate or be fixed in gate dielectric layer from grid, finally affects the performance of device.
Therefore, those skilled in the art adopt new gate dielectric layer to replace existing gate dielectric layer to replace existing silicon dioxide.In order to keep the electric capacity of gate dielectric layer constant, those skilled in the art adopt high-k (high K) dielectric layer as new gate dielectric layer.Described high-K dielectric layer has good thermal stability and mechanical strength, can obtain less leakage current.
The method that prior art utilizes high-K dielectric layer to make transistor please refer to Fig. 1 to Fig. 5.First, please refer to Fig. 1, provide Semiconductor substrate 100, be formed with isolation structure 101 in described Semiconductor substrate 100, described isolation structure 101 is for the isolation between adjacent transistor.Described Semiconductor substrate 100 surface is also formed with gate dielectric layer 102, dummy grid 103 successively and is positioned at the side wall 104 of described gate dielectric layer 102, dummy grid 103 both sides.
Then, continue with reference to figure 1, with described dummy grid 103 and side wall 104 for mask, carry out ion implantation, formation source region 105 and drain region 106 in the Semiconductor substrate 100 of described dummy grid 103 and side wall 104 both sides.
Then, please refer to Fig. 2, described Semiconductor substrate 100 is formed the interlayer dielectric layer 107 flushed with described dummy grid 103, and the material of described interlayer dielectric layer 107 is silica.
Then, please refer to Fig. 3, carry out etching technics, remove described dummy grid 103 (composition graphs 2), form the groove exposing described gate dielectric layer 102.
Then, please refer to Fig. 4, in sidewall and the bottom formation high-K dielectric layer 108 of described groove.
Finally, please refer to Fig. 5, the high-K dielectric layer in described groove is formed metal gates 109, described metal gates 109 flushes with described interlayer dielectric layer 105.
Be can also find more information about existing preparation method of transistor in the Chinese patent application of CN101661883A at publication number.
Finding in practice, there is leakage current, the unstable properties of device in the transistor that existing method makes.
Summary of the invention
The problem that the present invention solves there is provided a kind of manufacture method of transistor, and described method reduces the leakage current of transistor, improves the performance of device.
For solving the problem, the invention provides a kind of manufacture method of transistor, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with sacrifice layer, dummy grid successively, the Semiconductor substrate of described sacrifice layer and dummy grid both sides is formed with side wall;
Source region and drain region is formed in the Semiconductor substrate of described dummy grid and side wall both sides;
Form the interlayer dielectric layer flushed with described dummy grid on the semiconductor substrate;
Remove described dummy grid and sacrifice layer, form the groove exposing described Semiconductor substrate;
Gate dielectric layer is formed at described channel bottom;
Described trenched side-wall and gate dielectric layer form high-K dielectric layer;
High-K dielectric layer in described groove forms metal gates, and described metal gates flushes with described interlayer dielectric layer.
Alternatively, the material of described Semiconductor substrate is silicon, and the material of described sacrifice layer is silica, and the material of described side wall is silicon nitride.
Alternatively, the removal technique of described dummy grid is plasma etch process or wet-etching technology.
Alternatively, the removal technique of described sacrifice layer is plasma etch process.
Alternatively, the etching selection ratio of described plasma etch process to described sacrifice layer and Semiconductor substrate is greater than 15: 1, and the etching selection ratio of described plasma etch process to described sacrifice layer and side wall is greater than 5: 1.
Alternatively, described plasma etch process adopts the plasma group of Nitrogen ion, fluorine ion and hydrogen ion composition as etching ion.
Alternatively, the etching gas of described plasma etch process is N
xh
yand N
mf
nmist.
Alternatively, N in described plasma etch process
xh
yand N
mf
nvolume flow ratio be 3: 1 ~ 10: 1.
Alternatively, described plasma etching industrial comprises:
Main etch step, utilizes described plasma group to etch described sacrifice layer, forming reactions material;
Annealing steps, is heated to volatilization by the reactive material in described main etch step;
Cleaning, removes the gas produced in described annealing steps.
Alternatively, the temperature of described main etch step is less than 100 degrees Celsius.
Alternatively, the temperature of described annealing steps is greater than 100 degrees Celsius and is less than 400 degrees Celsius.
Alternatively, described reactive material is water, silicon fluoride ammonia, and described water becomes steam in described annealing steps, and described silicon fluoride ammonia is decomposed into the mist of silicon tetrafluoride gas and ammonia in described annealing steps.
Alternatively, the material of described gate dielectric layer is silica.
Compared with prior art, the present invention has the following advantages:
First the present invention provides and is formed with sacrifice layer, the Semiconductor substrate of dummy grid and side wall, then in the Semiconductor substrate of described dummy grid and side wall both sides, source region and drain region is formed, then the interlayer dielectric layer flushed with described dummy grid is formed on the semiconductor substrate, then, remove described dummy grid and sacrifice layer, form the groove exposing described Semiconductor substrate, gate dielectric layer is formed at described channel bottom, described trenched side-wall and gate dielectric layer form high-K dielectric layer, high-K dielectric layer in described groove forms metal gates, described metal gates flushes with described interlayer dielectric layer, because the present invention first removes described sacrifice layer, again gate dielectric layer is being made, thus the surface texture of the gate dielectric layer formed is complete, and prior art is owing to carrying out causing damage to the surface texture of described gate dielectric layer when etching technics removes described dummy grid, thus the gate dielectric layer surface texture of prior art is imperfect, therefore, the surface texture of the gate dielectric layer that the present invention is formed is complete, thus improve the adhesiveness between high-K dielectric layer and described gate dielectric layer formed on described gate dielectric layer, reduce the leakage current of transistor, improve the stability of transistor,
Further optimally, described sacrifice layer utilizes plasma etching to carry out, the etching selection ratio of described plasma etch process to described sacrifice layer and Semiconductor substrate is greater than 15: 1, thus when carrying out etching technics and removing described sacrifice layer, described Semiconductor substrate can not be damaged, thus make the adhesiveness between the gate dielectric layer of follow-up formation and Semiconductor substrate good, reduce the leakage current of transistor, the etching selection ratio of described plasma etch process to described sacrifice layer and side wall is greater than 5: 1, thus when carrying out etching technics and removing described sacrifice layer, described side wall can not be damaged.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the preparation method of transistor schematic flow sheet of prior art;
Fig. 6 is preparation method of transistor schematic flow sheet of the present invention;
Fig. 7 ~ Figure 12 is the preparation method of transistor schematic flow sheet of one embodiment of the invention.
Embodiment
There is leakage current, the unstable properties of device in the transistor that existing method makes.Study discovery through inventor, cause the reason of the problems referred to above to be that the adhesiveness of high-K dielectric layer and gate dielectric layer and side wall is bad.Particularly, incorporated by reference to Fig. 3, carrying out removing in the process of described dummy grid 103, sustaining damage of described gate dielectric layer 102 and side wall 104, thus make the adhesiveness of high-K dielectric layer 108 (Fig. 4) and described side wall 102 and the gate dielectric layer 108 formed bad, this causes the leakage current of transistor, thus have impact on the performance of device.
In order to solve the problem, inventor proposes a kind of manufacture method of transistor, and please refer to the preparation method of transistor schematic flow sheet of the present invention shown in Fig. 6, described method comprises:
Step S1, provides Semiconductor substrate, and described Semiconductor substrate is formed with sacrifice layer, dummy grid successively, and the Semiconductor substrate of described sacrifice layer and dummy grid both sides is formed with side wall;
Step S2, forms source region and drain region in the Semiconductor substrate of described dummy grid and side wall both sides;
Step S3, forms the interlayer dielectric layer flushed with described dummy grid on the semiconductor substrate;
Step S4, removes described dummy grid and sacrifice layer, forms the groove exposing described Semiconductor substrate;
Step S5, forms gate dielectric layer at described channel bottom;
Step S6, described trenched side-wall and gate dielectric layer form high-K dielectric layer;
Step S7, the high-K dielectric layer in described groove forms metal gates, and described metal gates flushes with described interlayer dielectric layer.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.
In order to technical scheme of the present invention is described better, please refer to the preparation method of transistor schematic flow sheet of the one embodiment of the invention shown in Fig. 7 ~ Figure 12.
First, please refer to Fig. 7, provide Semiconductor substrate 200, be formed with isolation structure 201 in described Semiconductor substrate 200, described isolation structure 201 is for the isolation between adjacent transistor.Described Semiconductor substrate 200 is formed with successively sacrifice layer 202, dummy grid 203, the Semiconductor substrate 200 of described sacrifice layer 202 and dummy grid 203 both sides is formed with side wall 204.
As an embodiment, the material of described Semiconductor substrate 200 is silicon.In other examples, described Semiconductor substrate 200 can also be silicon-on-insulator substrate (SOI), germanium silicon etc.
Described isolation structure 201 can be fleet plough groove isolation structure (STI) or field oxidation structure.Described fleet plough groove isolation structure or field oxidation structure same as the prior art, as the known technology of those skilled in the art, do not explain at this.
Sacrifice layer 202 of the present invention is for the protection of the surface of Semiconductor substrate 200; preventing described Semiconductor substrate 200 to be subject to, the damage of etching technics (such as forming the etching technics of described dummy grid 203) is follow-up will be removed, and forms gate dielectric layer in the position at described sacrifice layer 202 place.
As an embodiment, the material of described sacrifice layer 202 is silica, and it can utilize chemical vapor deposition method or thermal oxidation technology to make.The thickness of described sacrifice layer 202 is identical with the thickness of the follow-up gate dielectric layer that will be formed, and in the present embodiment, the thickness of described sacrifice layer 202 is 10 ~ 100 dusts, and the thickness of such as described sacrifice layer 202 can be 10 dusts, 50 dusts or 100 dusts.
The material of described dummy grid 203 is polysilicon, and it can utilize chemical vapor deposition method to make.The thickness range of described dummy grid 203 is 500 ~ 8000 dusts, such as, be 500 dusts, 3000 dusts, 5000 dusts or 8000 dusts.
As an embodiment, the material of described side wall 204 is silicon nitride.
Then, still with reference to figure 7, in the Semiconductor substrate of described dummy grid and side wall both sides, form source region 205 and drain region 206.Described source region 205 and drain region 206 are formed by source and drain ion implantation (SD implant), and the method for described source and drain ion implantation is same as the prior art, as the known technology of those skilled in the art, does not explain at this.
Then, please refer to Fig. 8, described Semiconductor substrate 200 is formed the interlayer dielectric layer 207 flushed with described dummy grid 203.The material of described interlayer dielectric layer 207 can be silica, silicon nitride, carborundum or silicon oxynitride.In the present embodiment, the material of described interlayer dielectric layer 207 is silicon nitride.Described interlayer dielectric layer 207 can utilize the method for chemical vapour deposition (CVD) to make.
Then, please refer to Fig. 9, remove described dummy grid.The minimizing technology of described dummy grid is the method for wet etching or plasma etching.Described in described wet etching or plasma etching, the method for dummy grid is identical with method for etching plasma with existing wet etching, as the known technology of those skilled in the art, does not describe in detail at this.
Then, with reference to Figure 10, remove described sacrifice layer 202, form the groove exposing described Semiconductor substrate 200.As the preferred embodiments of the present invention, the minimizing technology of described sacrifice layer 202 is plasma etch process.
Inventor finds, plasma etch process adopts the plasma ions group of different kinds of ions composition as etching ion, such as utilize the plasma group of carbon ion and hydrogen ion composition as etching ion, described sacrifice layer 202 is etched, can have no to remove described sacrifice layer 202 with remaining, but the plasma group of described carbon ion and hydrogen ion composition is to the etching selection lower (described Selection radio is less than 10: 1) of described sacrifice layer 202 and Semiconductor substrate 200, make described Semiconductor substrate 200 may be subject to the corrasion of the plasma group of described carbon ion and hydrogen ion composition, thus damage the surface of described Semiconductor substrate 200, and the plasma group of described carbon ion and hydrogen ion composition is to the etching selection lower (described Selection radio is less than 10: 1) of described sacrifice layer 202 and side wall 204, make described side wall 204 may be subject to the corrasion of the plasma group of described carbon ion and hydrogen ion composition, thus damage side wall 204.No matter be that described Semiconductor substrate 200 is damaged or described side wall 204 damages, all can affect the high-K dielectric layer of follow-up formation and the adhesiveness of described Semiconductor substrate 200 or described side wall 204, thus can transistor drain current be caused.
Inventor finds through research, when the etching selection ratio of described plasma etch process to described sacrifice layer 202 and Semiconductor substrate 200 is greater than 15: 1, less, negligible to the corrasion of described Semiconductor substrate 200; When the etching selection ratio of described plasma etch process to described sacrifice layer 202 and side wall 204 is greater than 5: 1, less to the corrasion of described side wall 204, substantially negligible, therefore, inventor considers that the parameter of plasma etching technics is optimized setting, with the effect making described plasma etching reach above-mentioned.
As a preferred embodiment, the plasma group that the present invention utilizes Nitrogen ion, fluorine ion and hydrogen ion to form carries out described plasma etching, the etching selection of plasma group to described sacrifice layer 202 and Semiconductor substrate 200 based on above-mentioned Nitrogen ion, fluorine ion and hydrogen ion composition is larger, and larger to the etching selection of described sacrifice layer 202 and described side wall 204.Described plasma etch process utilizes N
xh
yand N
mf
nmist carry out, wherein N
xh
yand N
mf
nvolume flow ratio be 3: 1 ~ 10: 1, such as described N
xh
yand N
mf
nvolume flow ratio can be 3: 1,7: 1 or 10: 1.Wherein, described x+y=1, m+n=1.
In a preferred embodiment of the invention, described plasma etching utilizes NH
3and NF
3mist carry out, wherein NH
3and NF
3volume flow proportion be 5: 1.
Described plasma etch process comprises the steps:
Main etch step, the plasma group utilizing described Nitrogen ion, fluorine ion and hydrogen ion to form etches described sacrifice layer 210, forming reactions material, and the temperature of described main etch step is less than 100 degrees Celsius;
Annealing steps, the reactive material in described main etch step is heated to volatilization, the temperature of described annealing steps should be greater than 100 degrees Celsius and be less than 400 degrees Celsius, and the temperature of such as described annealing steps can 150 degrees Celsius, 250 degrees Celsius or 400 degrees Celsius;
Cleaning, removes the gas produced in described annealing steps.
As one embodiment of the present of invention, the reactive material that described main etch step produces is water and (NH
4)
2siF
6(silicon fluoride ammonia).When follow-up annealing steps, described water becomes steam, and described silicon fluoride ammonolysis craft is SiF
6(silicon tetrafluoride) gas and NH
3the mist of (ammonia).
Based on the parameter of above-mentioned etch step; the etching selection ratio of described plasma etch process to described sacrifice layer 202 and Semiconductor substrate 200 is greater than 20: 1; when the etching selection ratio of described plasma etch process to described sacrifice layer 202 and side wall 204 is greater than 8: 1, protect Semiconductor substrate 200 and side wall 204.
Then, please refer to Figure 11, form gate dielectric layer 210 in the bottom of described groove, described gate dielectric layer 210 is positioned at described Semiconductor substrate 200 surface.The material of described gate dielectric layer 210 is silica, and it can utilize thermal oxidation technology or chemical vapor deposition method to make.The thickness range of described gate dielectric layer 210 is 10 ~ 100 dusts.
Because described Semiconductor substrate 200 does not sustain damage in the etching technics removing described sacrifice layer 202 (in conjunction with Figure 10), thus the surface of described Semiconductor substrate 200 is smooth, this makes described gate dielectric layer 210 and the good adhesion of Semiconductor substrate 200, reduces the leakage current of transistor.
Because described gate dielectric layer 210 for again to be formed after described plasma etch process, the therefore structural integrity of described gate dielectric layer 210, thus be conducive to improving the high-K dielectric layer of follow-up formation and the adhesiveness of gate dielectric layer 210, reduce the leakage current of transistor.
Then, please continue with reference to Figure 11, described trenched side-wall and gate dielectric layer 210 form high-K dielectric layer 208.Described high-K dielectric layer 208 is adjacent with described side wall 208.The thickness range of described high-K dielectric layer 208 is 10 ~ 100 dusts.The material of described high-K dielectric layer 208 can be hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide etc.
The manufacture method of described high-K dielectric layer 208 is same as the prior art, as the known technology of those skilled in the art, is not described in detail at this.
Because described side wall 208 is not subject to the damage of the etching technics removing described sacrifice layer 202, thus described side wall 208 surface texture is complete, and described high-K dielectric layer 208 can be attached on described side wall 208 better.
The structural integrity of described gate dielectric layer 210, thus described high-K dielectric layer 208 is good with the adhesiveness of gate dielectric layer 210, thus reduce the leakage current of transistor.
Finally, please refer to Figure 12, the high-K dielectric layer in described groove is formed metal gates 209, described metal gates 209 flushes with described interlayer dielectric layer 205.Material and the manufacture method of described metal gates 209 are same as the prior art, as the known technology of those skilled in the art, do not repeat at this.
To sum up, preparation method of transistor of the present invention, the dummy grid forming sacrifice layer on a semiconductor substrate and be positioned at above described sacrifice layer, after carrying out removing the etching technics of described dummy grid, described sacrifice layer is removed, and forms gate dielectric layer in the position of described sacrifice layer, present invention, avoiding the damage that gate dielectric layer is subject to etching technics, improve the adhesiveness between high-K dielectric layer and gate dielectric layer, thus subtract the leakage current of transistor.And the present invention also removes the parameter of the etching technics of described sacrifice layer by optimal design-aside, protect Semiconductor substrate and side wall.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (7)
1. a manufacture method for transistor, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with sacrifice layer, dummy grid successively, the Semiconductor substrate of described sacrifice layer and dummy grid both sides is formed with side wall;
Source region and drain region is formed in the Semiconductor substrate of described dummy grid and side wall both sides;
Form the interlayer dielectric layer flushed with described dummy grid on the semiconductor substrate;
Remove described dummy grid and sacrifice layer, form the groove exposing described Semiconductor substrate, the removal technique of described sacrifice layer is plasma etch process, described plasma etch process adopts the plasma group of Nitrogen ion, fluorine ion and hydrogen ion composition as etching ion, further, described plasma etching industrial comprises: main etch step, utilizes described plasma group to etch described sacrifice layer, forming reactions material, the temperature of described main etch step is less than 100 degrees Celsius; Annealing steps, the reactive material in described main etch step is heated to volatilization, the temperature of described annealing steps is greater than 250 degrees Celsius and is less than 400 degrees Celsius; Cleaning, the gas produced in described annealing steps is removed, the etching selection ratio of described plasma etch process to described sacrifice layer and Semiconductor substrate is greater than 15:1, and the etching selection ratio of described plasma etch process to described sacrifice layer and side wall is greater than 5:1;
Gate dielectric layer is formed at described channel bottom;
Described trenched side-wall and gate dielectric layer form high-K dielectric layer;
High-K dielectric layer in described groove forms metal gates, and described metal gates flushes with described interlayer dielectric layer.
2. the manufacture method of transistor as claimed in claim 1, it is characterized in that, the material of described Semiconductor substrate is silicon, and the material of described sacrifice layer is silica, and the material of described side wall is silicon nitride.
3. the manufacture method of transistor as claimed in claim 2, it is characterized in that, the removal technique of described dummy grid is plasma etch process or wet-etching technology.
4. the manufacture method of transistor as claimed in claim 1, it is characterized in that, the etching gas of described plasma etch process is N
xh
yand N
mf
nmist.
5. the manufacture method of transistor as claimed in claim 4, is characterized in that, N in described plasma etch process
xh
yand N
mf
nvolume flow ratio be 3:1 ~ 10:1.
6. the manufacture method of transistor as claimed in claim 1, it is characterized in that, described reactive material is water, silicon fluoride ammonia, and described water becomes steam in described annealing steps, and described silicon fluoride ammonia is decomposed into the mist of silicon tetrafluoride gas and ammonia in described annealing steps.
7. the manufacture method of transistor as claimed in claim 1, it is characterized in that, the material of described gate dielectric layer is silica.
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| CN102479716B true CN102479716B (en) | 2015-03-11 |
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| CN103871857B (en) * | 2012-12-18 | 2017-09-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN104347348A (en) * | 2013-08-09 | 2015-02-11 | 联华电子股份有限公司 | Removing manufacturing process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465290B1 (en) * | 2000-03-27 | 2002-10-15 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device using a polymer film pattern |
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
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| US9159808B2 (en) * | 2009-01-26 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective etch-back process for semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6465290B1 (en) * | 2000-03-27 | 2002-10-15 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device using a polymer film pattern |
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
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