CN1700421A - Method for forming nano-line width polysilicon gate etching mask pattern - Google Patents
Method for forming nano-line width polysilicon gate etching mask pattern Download PDFInfo
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- CN1700421A CN1700421A CN 200410047532 CN200410047532A CN1700421A CN 1700421 A CN1700421 A CN 1700421A CN 200410047532 CN200410047532 CN 200410047532 CN 200410047532 A CN200410047532 A CN 200410047532A CN 1700421 A CN1700421 A CN 1700421A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000005530 etching Methods 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 12
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000003292 glue Substances 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000004380 ashing Methods 0.000 claims abstract description 9
- 238000003631 wet chemical etching Methods 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 15
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- 238000005260 corrosion Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000003085 diluting agent Substances 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000007704 wet chemistry method Methods 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000008367 deionised water Substances 0.000 claims description 2
- 229910021641 deionized water Inorganic materials 0.000 claims description 2
- 238000011161 development Methods 0.000 claims description 2
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
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- -1 flow 20-80sccm Substances 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
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- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
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- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
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- 238000001352 electron-beam projection lithography Methods 0.000 description 1
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- 238000010884 ion-beam technique Methods 0.000 description 1
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Abstract
A method for forming a mask pattern for etching a polysilicon gate with a nanometer line width mainly comprises the following steps: (1) depositing polysilicon on ultra-thin gate dielectric, and then depositing TEOS SiO2A film; (2) photoetching a gate pattern; (3) ashing glue; (4) fluorination and baking; (5) reaction ion etching TEOS SiO2(ii) a (6) Removing the photoresist and cleaning; (7) wet chemical etching of TEOS SiO2To achieve the required line width. The invention can prepare the polysilicon gate etching mask with the line width of 15-50 nanometersAnd (3) a film pattern.
Description
Technical field
The invention belongs to the process of sub-micro semiconductor device, relate in particular to a kind of formation method of 15-50 nano-scale linewidth polysilicon gate etching mask pattern.
Background technology
Reducing of transistors characteristics, the decline that can bring the raising on integrated circuit density and the performance and be split in cost on the Elementary Function.Therefore from from integrated circuit is born, the competition of semiconductor industry just focuses in the miniaturization of processing dimension all the time.The characteristic size of big production in 2010 (physical gate is long) is 18 nanometers.Device size drops to inferior 50 nanometers near the limit of Scaling down, to face severe technological challenge, mainly show some parameter of device, as the difficulty that can not scaled down causes of threshold voltage and supply voltage (as serious short-channel effect, excessive OFF leakage current, Ion reduces, and total power consumption is excessive) and the restriction of fundamental technology: all approach the limit of technology as photoetching, ultra-thin gate dielectric, super shallow junction, low-resistance interconnection etc., be faced with the barrier that is difficult to go beyond.Photoetching process particularly.Existing advanced person's photoetching process technology is as the deep ultraviolet exposure technique of 248 nano wave lengths, cooperate phase shift mask and optical approach effect correction, can process 180-130 nano-scale linewidth figure, utilize the excimer laser exposure technology of 193 nano wave lengths of highest level, can process the 130-100 nano graph, but device systems is very complicated, the cost costliness.Generally believe that 100 nanofeature live widths are limit of optical lithography.At present, Study of Exposure Technology of future generation in the world mainly contains extreme ultraviolet photolithographic, electron beam projection lithography, X ray projection lithography and ion beam projection lithography etc.The apparatus expensive of these technology also has suitable distance from big production practicability.Any actually technology can replace optical lithography, does not also have final conclusion.Even adopt at present most promising electron beam exposure also can only reach live width level about 100 nanometers, also do not reach inferior 50 nano-scale linewidths.
Summary of the invention
The object of the present invention is to provide a kind of formation method of nano-scale linewidth polysilicon gate etching mask pattern, the live width that this method can form is the 15-50 nanometer.
The present invention is a kind of not only economic but also practical effective ways that can reach inferior 50 nanometers even inferior 20 nano-scale linewidth etch mask figures.This method does not need large-scale very expensive special equipment, and method is reliable, stable, repeat, and realizes easily, and can reach the 20 nanoscale microfabrication levels that present miscellaneous equipment and method can't reach.
The present invention is the method that the glue pattern of the 90-250 nano-scale linewidth of optical exposure or electron beam exposure acquisition is converted to the mask pattern of 15-50 nm polysilicon grid etching.The concrete steps of this method are:
Step 1: deposit polysilicon film on ultra-thin gate dielectric, deposit tetraethoxysilane thermal decomposition SiO then
2(TEOS SiO
2) film;
Step 2: photoetching forms the glue gate figure;
Step 3: the ashing of glue;
Step 4: fluoridize and toast;
Step 5: reactive ion etching TEOS SiO
2
Step 6: remove photoresist and clean;
Step 7: wet chemical etching technique reaches the requirement live width and ends.
Wherein step 1 is after finishing local field oxidation isolation, and forming gate dielectric film thickness is the 1.2-5 nanometer, deposit 100-300 nano-multicrystal silicon fiml on it, 620 ℃ of furnace temperature, silane (SiH
4), adopting then 720 ℃ of following TEOS thermal decompositions, deposition thickness is the TEOS SiO of 50-100 nanometer again
2Film.
Wherein step 2 photoetching forms glue pattern, comprises optical exposure, is 248 nanometers or 193 nanometer excimer laser exposures and electron beam exposure etc. as wavelength, after the development, and the live width scope 90-250 nanometer of grid glue pattern.
Wherein the ashing of step 3 glue is that utilization oxygen plasma in rf electric field carries out isotropic etching to glue, reaches the purpose of further dwindling the glue pattern live width.Radio-frequency power 30-100 watt, operating pressure 200-800m τ, reacting gas oxygen (O
2), flow 20-80sccm, diluent gas helium (He), flow 30-120sccm, electrode spacing 1-2 centimetre, electrode temperature 30-40 ℃, etch period is determined according to the glue thickness that will remove.
Wherein step 4 is fluoridized and baking is to adopt reacting gas and glue surface reaction to form one deck duricrust, has improved the softening temperature of glue, makes glue indeformable in back baking process, is a kind of method of raising anti-aliasing degree.Radio-frequency power 30-100 watt, operating pressure 200-800m τ, reacting gas CF
4, flow 30-80sccm, diluent gas helium (He), flow 50-150sccm, electrode spacing 1-2 centimetre, electrode temperature 30-40 ℃.125-135 ℃ of back baking temperature, the 35-45 branch progressively slowly is warming up to 125-135 ℃ from 90 ℃, and after constant temperature 35-45 minute, slowly cooling ends 90 ℃ again, takes out cool to room temperature, to reduce the distortion that stress that excessive temperature differentials causes causes thin adhesive tape.
Step 5 reactive ion etching TEOS SiO wherein
2Be to utilize the reactive ion etching method of anisotropic etching to etch away unwanted TEOS SiO
2, only stay the TEOSSiO under the glue mask pattern
2Radio-frequency power 200-400 watt, reacting gas is carbon tetrafluoride Freon-14 (CF
4)/fluoroform (CHF
3)/argon gas (Ar), CF
4Flow 6-30sccm, CHF
3Flow 20-150sccm, Ar flow 150-350sccm, operating pressure 100-300m τ, electrode spacing 1-2 centimetre, 0 ℃ of electrode temperature.
Wherein step 6 is removed photoresist and cleaning is to utilize wet chemistry to remove photoresist, and cleans then, to carry out next step wet chemical etching technique.Removing photoresist is in 120 ℃, with " removing photoresist 3
#" after liquid removed photoresist 10 minutes, clean with same solution, use 1 then
#Liquid is washed by water hot N 10 times again in 60 ℃ of cleanings 5 minutes
2The middle drying gets final product.
Of the present invention 3
#Liquid is H
2SO
4: H
2O
2=4-6: 1.
Of the present invention 1
#Liquid is NH
4OH: H
2O
2: H
2O=0.7-0.9: 1: 4-6.
Step 7 wet chemical etching technique TEOS SiO wherein
2Be the isotropism of utilizing wet chemical etching technique, erode TEOS SiO from top and both sides equably
2, longitudinally corrosion thinning TEOS SiO
2The thickness of film, lateral encroaching has reduced live width.The TEOS SiO that etching time removes as requested
2Thickness decision.For ease of control, some are advisable corrosion rate slowly.Corrosive liquid is hydrofluoric acid (HF concentration is 40%)/isopropyl alcohol (IPA)/H
2O=0.4-0.6%: 0.01-0.04%: 1, corrosion temperature is a room temperature.
As can be seen, core technology of the present invention is the combination of ashing technology and hard mask dressing technique from above-described method.
Wherein ashing technology is to react in plasma by oxygen atom and photoresist to reach the isotropically purpose of etching photoresist, thereby further dwindles the glue pattern live width.Oxygen molecule is broken down into elemental oxygen (O) in rf electric field, the basis of photoresist is hydrocarbon polymer, and oxygen atom and photoresist reaction generate main product such as volatile carbon monoxide, carbon dioxide and water.These products are taken away by vacuum system.
Hard mask dressing technique is to utilize the reactive ion etching method of anisotropic etching to etch away unwanted TEOS SiO
2, only stay the TEOS SiO under the glue mask pattern after the ashing
2, promptly the glue mask pattern accurately is copied into TEOS SiO
2Hard mask pattern.After removing photoresist and cleaning, to TEOSSiO
2Hard mask carries out isotropic wet chemical etching technique, erodes TEOS SiO from top and both sides equably
2, longitudinally corrosion thinning TEOS SiO
2The thickness of film, lateral encroaching have reduced TEOS SiO
2The live width of hard mask pattern.Thereby realized hard mask finishing.Etching time live width as requested, the TEOS SiO that just will remove
2Thickness decision.
Description of drawings
Fig. 1 is the structural representation after the present invention exposure.
Fig. 2 is the electron scanning micrograph of glue gate figure behind the cineration technics of the present invention.
Fig. 3 is the TEOS SiO behind the mask trim process of the present invention
2The electron scanning micrograph of grid mask pattern.
Fig. 4 is the cross sectional photograph of the high resolution transmission electron microscope of the long 27 nanometer cmos devices of grid of application the present invention preparation.
Embodiment
Embodiment 1
Step 1: be growth 200 nano-multicrystal silicon fimls on the ultra-thin gate dielectric film of 1.4 nanometers at equivalent oxidation bed thickness (EOT), then at 720 ℃ of following deposit 75 nanometer tetraethoxysilane thermal decomposition SiO
2Film.
Step 2: with SAL 601 negative glue, e-beam direct write lithography forms 100-110 nanometer glue pattern.Fig. 1 has provided the structural representation after the exposure.
Step 3: carry out the ashing of glue, 60 watts of radio-frequency powers, reacting gas O
240sccm, diluent gas He 60sccm, operating pressure 450m τ, 1.5 centimetres of electrode distances, 35 ℃ of electrode temperatures.The about 75-80 nm/min of etch rate, the wide 50-55 nanometer of control tree lace.Fig. 2 has provided the SEM photo of glue gate figure behind the cineration technics, and the live width after the ashing is 54.9 nanometers.
Step 4: fluoridize and toast 40 watts of radio-frequency powers, CF
4100sccm, He 60sccm, operating pressure 500m τ fluoridizes 40 seconds time; Insert 90 ℃ baking oven after fluoridizing, rise to 130 ℃ with 30 minutes, constant temperature is after 40 minutes, reduces to 90 ℃ of taking-ups from 130 ℃, and temperature fall time is no less than 40 minutes.
Step 5: reactive ion etching TEOS SiO
2, 300 watts of radio-frequency powers, CHF
3/ CF
4/ Ar=50sccm/10sccm/250sccm, operating pressure 200m τ, terminal point trigger and end, and do not have quarter.
Step 6: wet chemistry removes photoresist, and 120 ℃, 3
#Liquid removed photoresist 10 minutes, and 3
#Liquid cleaned 10 minutes, then in 60 ℃, with 1
#Liquid cleaned 5 minutes, deionized water rinsing 10 times, hot N
2The middle drying gets final product.3
#Liquid is H
2SO
4: H
2O
2=5: 1; 1
#Liquid is NH
4OH: H
2O
2: H
2O=0.8: 1: 5.
Step 7: wet-chemical etching TEOS SiO
2, corrosive liquid proportioning HF (HF concentration is 40%)/IPA/H
2O=0.5%/0.02%/1, about 0.3 nm/sec of corrosion rate, control TEOS SiO
2Mask pattern live width 20 nano-scale.Fig. 3 has provided the TEOS SiO behind the mask trim process
2Mask pattern, live width are 21.3 nanometers.
Fig. 4 has provided the cross sectional photograph of the high resolution transmission electron microscope of using the long 27 nanometer cmos devices of grid that the present invention succeeds in developing.Device property is good.
Claims (8)
1. the formation method of a nano-scale linewidth polysilicon gate etching mask pattern, the live width of formation is the 15-50 nanometer, its key step is:
Step 1: deposit polysilicon film on ultra-thin gate dielectric, deposit tetraethoxysilane thermal decomposition SiO then
2Film;
Step 2: with excimer laser or electron beam exposure, photoetching forms the glue gate figure;
Step 3: the ashing of glue, with oxygen plasma glue is carried out isotropic etching, radio-frequency power 30-100 watt, operating pressure 200-800m τ, reacting gas oxygen, flow 20-80sccm, diluent gas helium, flow 30-120sccm, electrode spacing 1-2 centimetre, electrode temperature 30-40 ℃;
Step 4: use CF
4Gas is fluoridized and is toasted;
Step 5: reactive ion etching tetraethoxysilane thermal decomposition SiO anisotropically
2Film;
Step 6: remove photoresist and clean with wet chemistry; In 120 ℃, be H with volume ratio
2SO
4: H
2O
2=4-6: 1 solution removes photoresist, 10 minutes time; Same solution cleans; Is NH in 60 ℃ with volume ratio
4OH: H
2O
2: H
2The solution of O=0.7-0.9: 1: 4-6 cleaned 5 minutes; Hot N
2Dry in the atmosphere;
Step 7: wet chemical etching technique under the room temperature, corrosive liquid are hydrofluoric acid/isopropyl alcohol/H of 40%
2O=0.4-0.6%: 0.01-0.04%: 1, reach the requirement live width and end.
2. formation method according to claim 1 is characterized in that, wherein the grid medium thickness in the step 1 is the 1.2-5 nanometer, and the polysilicon thickness is the 100-300 nanometer, TEOS SiO
2Thickness 50-100 nanometer.
3. formation method according to claim 1 is characterized in that, wherein the excimer laser wavelength that uses in the step 2 is 248 or 193 nanometers, uses the excimer laser special glue; The electron beam exposure electron beam adhesive; After the development, form the gate figure of glue, live width scope 90-250 nanometer.
4. formation method according to claim 1 is characterized in that, wherein the etch period of step 3 is determined according to glue thickness.
5. formation method according to claim 1 is characterized in that, wherein the radio-frequency power in the step 4 is 30 watts-100 watts, CF
4Flow 30-80sccm, operating pressure 200-800m τ, diluent gas helium, flow 50-150sccm, electrode spacing 1-2 centimetre, electrode temperature 30-40 ℃; Baking temperature 125-135 ℃, stoving time 35-45 minute.
6. formation method according to claim 1 is characterized in that, wherein the etching gas that adopts in the step 5 is carbon tetrafluoride Freon-14/fluoroform/argon gas, CF
4Flow 6-30sccm, CHF
3Flow 20-150sccm, Ar flow 150-360sccm, operating pressure 100-300m τ, radio-frequency power 200-400 watt, electrode spacing 1-2 centimetre, 0 ℃ of electrode temperature.
7. formation method according to claim 1 is characterized in that, wherein the cleaning in the step 6 also comprises deionized water rinsing, hot N
2Dry in the atmosphere.
8. formation method according to claim 1 is characterized in that, the wherein thickness that removes as required of the etching time in the step 7 and corrosion rate decision.
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|---|---|---|---|
| CNB2004100475327A CN100342497C (en) | 2004-05-21 | 2004-05-21 | Method for forming nano-line width polysilicon gate etching mask pattern |
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|---|---|---|---|
| CNB2004100475327A CN100342497C (en) | 2004-05-21 | 2004-05-21 | Method for forming nano-line width polysilicon gate etching mask pattern |
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| CN100342497C CN100342497C (en) | 2007-10-10 |
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- 2004-05-21 CN CNB2004100475327A patent/CN100342497C/en not_active Expired - Fee Related
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| CN101197262B (en) * | 2006-12-04 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Grids production method |
| CN101554991B (en) * | 2009-05-11 | 2012-01-18 | 北京大学 | Processing method of diverse nano structure |
| CN101572290B (en) * | 2009-06-02 | 2010-09-08 | 中国科学院上海微系统与信息技术研究所 | Method for preparing columnar nanometer heating electrode |
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| CN102618936A (en) * | 2012-03-21 | 2012-08-01 | 北京通美晶体技术有限公司 | Gallium arsenide surface chemical etching method and chemical etchant |
| CN102618936B (en) * | 2012-03-21 | 2015-01-14 | 北京通美晶体技术有限公司 | Gallium arsenide surface chemical etching method and chemical etchant |
| CN107526190A (en) * | 2016-06-22 | 2017-12-29 | 信利（惠州）智能显示有限公司 | A kind of LTPS preparation technology |
| CN110581170A (en) * | 2019-08-13 | 2019-12-17 | 中山市华南理工大学现代产业技术研究院 | GaN-based MIS-HEMT device with Г type gate and preparation method thereof |
| WO2021027242A1 (en) * | 2019-08-13 | 2021-02-18 | 中山市华南理工大学现代产业技术研究院 | Gan-based mis-hemt device having г-shaped gate and preparation method |
| CN112436038A (en) * | 2020-11-23 | 2021-03-02 | 安徽熙泰智能科技有限公司 | Novel pixel definition layer of silicon-based Micro OLED Micro-display device and preparation method thereof |
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