CN101197262B - Grids production method - Google Patents
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- CN101197262B CN101197262B CN2006101190615A CN200610119061A CN101197262B CN 101197262 B CN101197262 B CN 101197262B CN 2006101190615 A CN2006101190615 A CN 2006101190615A CN 200610119061 A CN200610119061 A CN 200610119061A CN 101197262 B CN101197262 B CN 101197262B
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Abstract
The invention relates to a manufacture method for grid, which comprises the following steps of: providing a semi-conductor substrate and forming a conductive layer on the semi-conductor substrate; revolving and coating optical carved glue layer on the conductive layer and imaging to form a grid pattern; transferring the grid pattern to the conductive layer through etching; measuring the line width of the grid and judging whether the bottom of the grid has a foot-shaped drawback, and performing directional plasma etching for the grid which has the foot-shaped drawback. The grid formed by the method has a better side wall profile.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the manufacture method of grid in particularly a kind of semiconductor device.
Background technology
Along with semiconductor fabrication is showing improvement or progress day by day, the size of its grid is more and more littler, the device drive voltage that little grid live width can reduce to form, and then reduce power consumption; Simultaneously the size of the entire device of formation is reduced, integrated level improves, thereby industry always forms less grid size by the whole bag of tricks.In number of patent application is 200410093459 Chinese patent, a kind of technology that reduces the grid live width is disclosed, Fig. 1 to Fig. 5 is the generalized section of the technology corresponding structure of described patent disclosure.
As shown in Figure 1, semi-conductive substrate 100 at first is provided, on described Semiconductor substrate 100, form grid oxic horizon 102, deposition one polysilicon layer 104 on described grid oxic horizon 102, deposition one hard mask layer 106 on described polysilicon layer 104, described hard mask layer 106 is a kind of in silica or the silicon nitride.
As shown in Figure 2, spin coating one photoresist layer on described hard mask layer 106, and by the exposure and the formation photoresist figure 108 that develops.Make the live width of photoresist figure 108 reduce by isotropic etching.
As shown in Figure 3, described photoresist figure 108 is transferred on the described hard mask layer 106, formed hard mask pattern 106a by photoetching.As shown in Figure 4, make hard mask pattern 106a live width reduce by the isotropic etching, form gate patterns 106b, because hard mask pattern 106a top is subjected to 108 protections of photoresist figure, etching is only laterally being carried out.
As shown in Figure 5, removing described photoresist figure 108, is mask with described gate patterns 106b, and the described polysilicon layer 104 of etching forms grid 104a.Above-mentioned grid technology reaches the purpose that forms little live width grid by the two-step reduction to photoresist figure 108 and hard mask pattern 106a, yet when making the structure that forms as shown in Figure 4, photoresist figure 108 is easy to peel off when hard mask pattern 106a live width forms gate patterns 106b reducing, and causes other defective.When 65nm even littler live width, for avoiding above-mentioned defect influence, generally do not introduce hard mask layer 106, but directly on polysilicon, form the photoresist figure of grid, form polysilicon gate by etching.Its step is as follows: as shown in Figure 6, provide semiconductor substrate 200, form an oxide layer 202 on the described semiconductor-based end 200, deposition one polysilicon layer 204 on described oxide layer 202.As shown in Figure 7, spin coating one anti-reflecting layer 205 on described polysilicon layer 204, and on described anti-reflecting layer the spin coating photoresist layer, form gate patterns 206 by photoetching, form gate patterns 206 technologies and can adopt photoresist to cut down technology or employing high-resolution exposure technology (for example 193nm exposure technology).
As shown in Figure 8, described gate patterns 206 is transferred on the described polysilicon layer 204, formed grid 204a by etching.
With described gate patterns 206 is mask layer, the described polysilicon layer 204 that is not covered by gate patterns 206 of etching and form grid 204a, etching generally adopts dry etching, the polymer that dry etching plasma and photoresist effect produce in the etching process can be attached to the both sides of grid 204a, after to be etched the finishing, can form sufficient shape profile (Foot) in grid 204a bottom, as shown in Fig. 8 a 207.This foot shape profile 207 makes grid change to the unlatching performance of conducting channel in the substrate, caused electrically can not satisfying the demands of the device that forms.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of grid, to solve existing grid production method forms sufficient shape profile in gate bottom problem.
For achieving the above object, the manufacture method of a kind of grid provided by the invention comprises: the semiconductor substrate is provided, forms conductive layer on the described semiconductor-based end; Spin coating photoresist layer and carry out graphically on described conductive layer forms gate pattern; By etching described gate pattern is transferred on the described conductive layer, formed grid; Described grid is carried out the directional plasma etching.
The direction of described directional plasma etching and the angle of described semiconductor-based basal surface are 70 to 90 degree.
Described plasma is an oxygen gas plasma.
The pressure of the environment of described oxygen gas plasma is 2 to 15Torr.
The radio frequency source power that produces described oxygen gas plasma is 100 to 1000 watts, and the flow of oxygen is 50 to 500sccm.
Described conductive layer is a kind of or its combination in polysilicon, the metal silicide.
This method further comprises: remove described photoresist layer by ashing, and carry out wet-cleaned.
Mutually deserved, the present invention also provides a kind of manufacture method of grid, comprising: the semiconductor substrate is provided, forms conductive layer on the described semiconductor-based end; Spin coating photoresist layer and carry out graphically on described conductive layer forms gate pattern; By etching described gate pattern is transferred on the described conductive layer, formed grid; Measure the live width of described grid, judge according to measurement result whether described gate bottom has sufficient shape profile,, described grid is carried out the directional plasma etching if having; If do not have, finish the manufacturing of grid.
Adopt optics critical size method of measurement to measure the live width of described gate bottom.
According to the time of the measurement result decision of described grid live width being carried out the directional plasma etching to described grid.
Adopt oxygen gas plasma that described grid is carried out the directional plasma etching.
The present invention also provides a kind of manufacture method of grid, comprising: form conductive layer on the first semiconductor-based end; Spin coating photoresist layer and carry out graphically on described conductive layer forms gate pattern; By etching described gate pattern is transferred on the described conductive layer, formed grid; Measure the live width of described grid; Judge according to measurement result whether described gate bottom has sufficient shape profile; If have, the grid that forms is carried out the directional plasma etching at the second follow-up semiconductor-based end.
The grid that forms is carried out at the second follow-up semiconductor-based end the time of directional plasma etching according to the measurement result decision of the suprabasil grid of first semiconductor.
Described plasma is an oxygen gas plasma.
Compared with prior art, the present invention has the following advantages:
The present invention is by directed oxygen gas plasma etching, the polymer that is formed at the gate bottom sidewall is removed, make the grid that forms have profile preferably, and then make that the grid that forms is sensitive more controlled to the unlatching of conducting channel, improved the unfailing performance of device; In addition; in the dry etching process; the volatile accessory substance that produces usually again crystallization fall after rise on the surface at the semiconductor-based end, form residual defects, also can remove residue defective and other pollutant of described semiconductor-based basal surface by the directional plasma etching.
The inventive method is also by measuring the grid of finishing etching to judge whether described gate lateral wall bottom has sufficient shape profile, whether described grid is carried out the time of directional plasma etching and directional plasma etching with decision, make the gate bottom that forms not have sufficient shape profile, and needn't carry out the directional plasma etching the suprabasil grid of each semiconductor.Simultaneously, measurement and directional plasma etching all can be finished in etching apparatus, and the described semiconductor-based end needn't take out from etching apparatus, also needn't cut into slices, and has simplified technology and has improved efficient, make cost reduce, and save time.
This method is also by measuring the suprabasil grid of the first half conductor conductor, to judge whether the grid that forms needs the directional plasma etching at follow-up the semiconductor-based end, and the time of directional plasma etching, avoid the repeatedly transmission of the semiconductor-based end between different chamber, and repeatedly expose to the open air with external environment condition in, reduced contaminated may.
Description of drawings
Fig. 1 to Fig. 5 is the generalized section of each step counter structure of manufacture method of existing a kind of grid;
Fig. 6 to Fig. 8 is the generalized section of each step counter structure of manufacture method of existing another kind of grid;
Fig. 8 a is the grid structure schematic diagram with sufficient shape defective of existing grid production method manufacturing;
Fig. 9 is the flow chart of first embodiment of method constructed in accordance;
Figure 10 to Figure 15 is the generalized section of each step counter structure of first embodiment of method constructed in accordance;
Figure 16 is the flow chart of second embodiment of method constructed in accordance;
Figure 17 is the flow chart of the 3rd embodiment of method constructed in accordance;
Figure 18 is the flow chart of the 4th embodiment of method constructed in accordance.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 9 is the flow chart of first embodiment of grid production method of the present invention.As shown in Figure 9, at first, provide the semiconductor substrate, on the described semiconductor-based end, form conductive layer (S200).Described semiconductor-based bottom materials comprises a semi-conductive substrate and an oxide layer, and described Semiconductor substrate can be a kind of in the semi-conducting materials such as monocrystalline silicon, polysilicon, amorphous silicon, germanium, and described thickness of oxide layer is 5 to 100nm.Described conductive layer is a kind of or its combination in polysilicon, the metal silicide, and the method that forms described conductive layer is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Spin coating photoresist and carry out graphically on described conductive layer forms gate pattern (S210).Described photoresist is a chemically-amplified resist.Before the described photoresist of spin coating, on described conductive layer, form an anti-reflecting layer earlier, described anti-reflecting layer is used for reducing reverberation the influencing forming gate pattern at exposure process of described conductive layer surface.Send into exposure sources and expose at the semiconductor-based end that will be formed with anti-reflecting layer and photoresist layer, by exposing the design transfer on the mask plate (mask) to described photoresist layer, remove the photoresist that is not exposed by developing then, the photoresist figure that remaines on the described conductive layer forms gate pattern.
The semiconductor-based end that will have described gate pattern, move into etching apparatus, removes not by the conductive layer that described gate pattern covered by the plasma dry etching, and described gate pattern is transferred on the conductive layer, forms grid (S220).
Behind etching formation grid, original position (in-situ) is carried out directional plasma etching (S230) to the described semiconductor-based basal surface that is formed with grid.Described directional plasma is an oxygen gas plasma.The bombardment direction of described directed oxygen gas plasma and the angle of described semiconductor-based basal surface are 70 to 90 degree, the pressure of the environment of described directed oxygen gas plasma is 2 to 15Torr, the radio frequency source power that produces described directed oxygen gas plasma is 100 to 1000 watts, and the flow of oxygen is 50 to 500sccm.When the conductive layer of the described polysilicon material of etching, generally select fluorine-containing gas for use, fluorine and photoresist effect meeting generate on polymer and the sidewall attached to grid, influence further carrying out of etching, cause the profile that has sufficient shape at the gate bottom sidewall that forms, by directed oxygen gas plasma etching, the polymer of described gate bottom sidewall can be removed, make grid have profile preferably, and then make grid sensitive more controlled to the unlatching of conducting channel, improved the unfailing performance of device; In addition; in the dry etching process; the volatile accessory substance that produces is crystallization and falling after rise on the surface at the semiconductor-based end again usually, forms residual defects, also can remove residue defective and other pollutant of described semiconductor-based basal surface by the directional plasma etching.
Manufacture method first embodiment to described grid is described in detail below in conjunction with accompanying drawing.Figure 10 to Figure 15 is the generalized section of each step corresponding construction of first embodiment of the grid production method according to the present invention.
As shown in figure 10, on semi-conductive substrate 300, form oxide layer 302.Described Semiconductor substrate 300 can the time polysilicon, monocrystalline silicon, amorphous silicon, germanium, arsenicization a kind of in sowing, also can be silicon on the insulating barrier.Described oxide layer 302 forms by the method for thermal oxidation or deposition, and its thickness is about 1 to 100nm.This oxide layer 302 is the gate oxide of the grid of follow-up formation, and also as the resilient coating when follow-up ion implantation technology, energetic ion is to the damage of described Semiconductor substrate 300 when reducing the ion injection.
As shown in figure 11, form a conductive layer 304 on described oxide layer 302, described conductive layer 304 is a kind of or its combination in polysilicon, the metal silicide, and described conductive layer 304 also can be a metal.Conductive layer described in the present embodiment 304 is a polysilicon.The method of its formation is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
As shown in figure 12, spin coating anti-reflecting layer 305 on described conductive layer 304, spin coating photoresist layer 306 on described anti-reflecting layer 305, described anti-reflecting layer 305 reduce or eliminate the influence of reverberation in exposure process on described conductive layer 304 surfaces.Send into exposure sources and expose at the semiconductor-based end that will be formed with anti-reflecting layer 305 and photoresist layer 306, by exposing the design transfer on the mask plate (mask) to described photoresist layer 306, remove the photoresist that is not exposed by developing, the photoresist figure that remaines on the described conductive layer forms gate pattern 306a as shown in figure 13.
As shown in figure 14, be mask with described gate pattern 306a, the described conductive layer 304 of etching is removed describedly not by the conductive layer of gate pattern 306a and anti-reflecting layer 305a protection, forms grid 304a in described conductive layer 304.Described etching is the plasma dry etching, and the chemical gas of etching is generally fluoro-gas.
As shown in figure 15, the surface that will be formed with the Semiconductor substrate 300 of grid 304a expose to the open air with directed oxygen gas plasma 308 environment in, directed oxygen gas plasma etching is carried out on the surface of described Semiconductor substrate 300.This orientation oxygen gas plasma etching and aforementioned etching form grid technology and can carry out in same chamber, i.e. the directed etching of original position; The etching direction of described directional plasma and the angle of described semiconductor-based basal surface are 70 to 90 degree, the pressure of the environment of described directed oxygen gas plasma is 2 to 15Torr, the radio frequency source power that produces described directed oxygen gas plasma 308 is 100 to 1000 watts, and the flow of oxygen is 50 to 500sccm.By directed oxygen gas plasma bombardment, the polymer of described grid 304a bottom sidewall can be removed, make the grid 304a that forms have profile preferably, and then make grid 304a sensitive more controlled, improved the unfailing performance of device the unlatching of conducting channel.In addition; in the dry etching process, the usually crystallization again of volatile accessory substance of generation falls the surface at the semiconductor-based end after rise; form residual defects, can remove residue defective and other pollutant of described semiconductor-based basal surface by the directional plasma etching.In directed oxygen gas plasma etching process, the gate pattern 306a of photoresist makes described grid 304a top not be subjected to the damage of directed oxygen gas plasma etching as protective layer on described grid 304a; Simultaneously because the directivity of directed etching can not cause damage to described grid 304a side wall upper part.Described directed etching also can be carried out in other chamber, repeats no more here.
After finishing described directed oxygen gas plasma etching, remove described photoresist layer 306a and anti-reflecting layer 305a by ashing (Ash), and then carry out wet-cleaned, remove surface contaminant, form grid 304a.
Figure 16 is the flow chart of second embodiment of manufacture method of the present invention.
As shown in figure 16, provide the semiconductor substrate, on the described semiconductor-based end, form conductive layer (S300).The described semiconductor-based end, comprise a semi-conductive substrate and an oxide layer, and described Semiconductor substrate can be a kind of in the semi-conducting materials such as monocrystalline silicon, polysilicon, amorphous silicon, germanium, and described thickness of oxide layer is 5 to 100nm.Described conductive layer is a kind of or its combination in polysilicon, the metal silicide, and the method that forms described conductive layer is physical vapour deposition (PVD) or chemical vapour deposition (CVD), and conductive layer described in the present embodiment is a polysilicon.
Spin coating photoresist and carry out graphically on described conductive layer forms gate pattern (S310).Described photoresist is a chemically-amplified resist, before the described photoresist of spin coating, forms an anti-reflecting layer earlier on described conductive layer, and described anti-reflecting layer is used for reducing the reverberation of conductive layer surface in the influence of exposure process to formation gate patterns profile.Send into exposure sources and expose at the semiconductor-based end that will be formed with anti-reflecting layer and photoresist layer, by exposing the design transfer on the mask plate (mask) to described photoresist layer, remove the photoresist that is not exposed by developing, the photoresist figure that remaines on the described conductive layer forms gate pattern.
The semiconductor-based end that will have described gate pattern, move into etching apparatus, removes not by the conductive layer that described gate pattern covered by the plasma dry etching, and described gate pattern is transferred on the conductive layer, forms grid (S320).
After forming grid, measure the live width (S330) that (Optical CriticalDimension) method is measured described grid by the optics critical size at described the semiconductor-based end.Measurement to described grid can be carried out in the chamber of described semiconductor etching device, the chamber that is used to measure the grid live width is different with the chamber that etching forms grid, for example, the chamber that the described conductive layer of etching forms grid is first chamber, measures the live width of described grid and carries out at second chamber.The suprabasil a plurality of grids of described semiconductor can be regarded the diffraction grating of a reflection as, the OCD method is by a branch of polarised light being projected on the described diffraction grating and diffracted, accept the described diffraction light line data of going forward side by side by photosensitive unit and handle the live width obtain grid, the OCD method of measurement can obtain the live width at positions such as grid upper, middle and lower, can judge the profile of gate lateral wall according to the live width that records position, grid upper, middle and lower.With respect to the existing method that needs by the destructiveness monitoring of section (Crosss section) and SEM, the OCD method of measurement can be by measuring the side wall profile of grid, needn't cut, simplify technology, reduced the profile of the grid of expense and monitoring etching that can be real-time, so that the etching technics parameter is adjusted, make the gate profile that forms reach requirement.
Judge according to the result who measures whether described gate bottom has sufficient shape profile (S340),, finish manufacturing (S360) described grid if do not have.
If judgement learns that described gate bottom has sufficient shape profile according to measurement result, described first chamber is sent at this semiconductor-based end with sufficient shape profile grid, the suprabasil grid of described semiconductor is carried out directed oxygen plasma etching (S350).According to the time of the measurement result decision of described grid live width being carried out directed etching to described grid, the direction of described directed oxygen gas plasma and the angle of described semiconductor-based basal surface are 70 to 90 degree, the pressure of the environment of described directed oxygen gas plasma is 2 to 15Torr, the radio frequency source power that produces described directed oxygen gas plasma is 100 to 1000 watts, and the flow of oxygen is 50 to 500sccm.Described grid is carried out directed oxygen plasma etching also can in the 3rd other chamber, carry out, repeat no more here.After described grid carried out the directional plasma etching, finish the manufacturing of grid.
Figure 17 is the flow chart of the 3rd embodiment of manufacture method of the present invention.
As shown in figure 17, provide the semiconductor substrate, on the described semiconductor-based end, form conductive layer (S300).The described semiconductor-based end, comprise a semi-conductive substrate and an oxide layer, and described Semiconductor substrate can be a kind of in the semi-conducting materials such as monocrystalline silicon, polysilicon, amorphous silicon, germanium, and described thickness of oxide layer is 5 to 100nm.Described conductive layer is a kind of or its combination in polysilicon, the metal silicide, and the method that forms described conductive layer is physical vapour deposition (PVD) or chemical vapour deposition (CVD), and conductive layer described in the present embodiment is a polysilicon.
Spin coating photoresist and carry out graphically on described conductive layer forms gate pattern (S310).Described photoresist is a chemically-amplified resist, before the described photoresist of spin coating, forms an anti-reflecting layer earlier on described conductive layer, and described anti-reflecting layer is used for reducing the reverberation of conductive layer surface in the influence of exposure process to formation gate patterns profile.Send into exposure sources and expose at the semiconductor-based end that will be formed with anti-reflecting layer and photoresist layer, by exposing the design transfer on the mask plate (mask) to described photoresist layer, remove the photoresist that is not exposed by developing, the photoresist figure that remaines on the described conductive layer forms gate pattern.
The semiconductor-based end that will have described gate pattern, move into etching apparatus, removes not by the conductive layer that described gate pattern covered by the plasma dry etching, and described gate pattern is transferred on the conductive layer, forms grid (S320).
After forming grid, measure the live width (S330) that (Optical CriticalDimension) method is measured described grid by the optics critical size at described the semiconductor-based end.Measurement to described grid can be carried out in the chamber of described semiconductor etching device, the chamber that is used to measure the grid live width is different with the chamber that etching forms grid, for example, the chamber that the described conductive layer of etching forms grid is first chamber, measures the live width of described grid and carries out at second chamber.The suprabasil a plurality of grids of described semiconductor can be regarded the diffraction grating of a reflection as, the OCD method is by a branch of polarised light being projected on the described diffraction grating and diffracted, accept the described diffraction light line data of going forward side by side by photosensitive unit and handle the live width obtain grid, the OCD method of measurement can obtain the live width at positions such as grid upper, middle and lower, can judge the profile of gate lateral wall according to the live width that records positions such as grid upper, middle and lower.With respect to the existing method that needs by the destructiveness monitoring of section (Crosss section) and SEM, the OCD method of measurement can be by measuring the side wall profile of grid, needn't cut, simplify technology, reduced the profile of the grid of expense and monitoring etching that can be real-time, so that the etching technics parameter is adjusted, make the gate profile that forms reach requirement.
Judge according to the result who measures whether described gate bottom has sufficient shape profile (S340),, finish manufacturing (S360) described grid if do not have.
If judgement learns that described gate bottom has sufficient shape profile according to measurement result, first chamber is sent at this semiconductor-based end with sufficient shape profile, the suprabasil grid of described semiconductor is carried out directed oxygen plasma etching (S350).According to the time of the measurement result decision of described grid live width being carried out directed etching to described grid, the direction of described directed oxygen gas plasma and the angle of described semiconductor-based basal surface are 70 to 90 degree, the pressure of the environment of described directed oxygen gas plasma is 2 to 15Torr, the radio frequency source power that produces described directed oxygen gas plasma is 100 to 1000 watts, and the flow of oxygen is 50 to 500sccm.In the present embodiment, measure to judge whether described gate lateral wall bottom has sufficient shape profile by the grid of finishing etching being carried out OCD, with decision whether described grid is carried out directed oxygen gas plasma etching, and the time of directed oxygen gas plasma etching, needn't carry out the directional plasma etching to the suprabasil grid of each semiconductor; Simultaneously, measurement and directed oxygen gas plasma etching are all finished in etching apparatus, and the described semiconductor-based end needn't take out from etching apparatus, also needn't cut into slices, and has simplified technology and has improved efficient, make cost reduce simultaneously, save time.Described grid is carried out the technology of directed oxygen plasma etching and also can in the 3rd other chamber, carry out, repeat no more here.
After described grid carried out the directional plasma etching, measure the live width of the grid of the directed oxygen plasma etching of described process once more by the OCD method, and judge according to measurement result whether described gate bottom also has sufficient shape profile, if proceed the directional plasma etching; If there is not the manufacturing of finishing described grid.
Figure 18 is the flow chart of the 4th embodiment of manufacture method of the present invention.
As shown in figure 18,, on the first semiconductor-based end, form conductive layer (S400).The described first semiconductor-based end, comprised a semiconductor substrate and an oxide layer.The described semiconductor-based end can be a kind of in the semi-conducting materials such as monocrystalline silicon, polysilicon, amorphous silicon, germanium, and described thickness of oxide layer is 5 to 100nm.Described conductive layer is a kind of or its combination in polysilicon, the metal silicide, and the method that forms described conductive layer is physical vapour deposition (PVD) or chemical vapour deposition (CVD), and conductive layer described in the present embodiment is a polysilicon.
Spin coating photoresist and carry out graphically on described conductive layer forms gate pattern (S410).Described photoresist is a chemically-amplified resist, before the described photoresist of spin coating, forms an anti-reflecting layer earlier on described conductive layer, and described anti-reflecting layer is used for reducing the reverberation of conductive layer surface in the influence of exposure process to formation gate patterns profile.Send into exposure sources and expose at the first semiconductor-based end that will be formed with anti-reflecting layer and photoresist layer, by exposing the design transfer on the mask plate (mask) to described photoresist layer, remove the photoresist that is not exposed by developing, the photoresist figure that remaines on the described conductive layer forms gate pattern.
The first semiconductor-based end that will have described gate pattern, move into etching apparatus, removes not by the conductive layer that described gate pattern covered by the plasma dry etching, and described gate pattern is transferred on the conductive layer, forms grid (S420).
After forming grid, measure the live width (S430) that (Optical CriticalDimension) method is measured described grid by the optics critical size at described the semiconductor-based end.Measurement to described grid can be carried out in the chamber of described semiconductor etching device, the chamber that is used to measure the grid live width is different with the chamber that etching forms grid, for example, the chamber that the described conductive layer of etching forms grid is first chamber, measures the live width of described grid and carries out at second chamber.The suprabasil a plurality of grids of described first semiconductor can be regarded the diffraction grating of a reflection as, the OCD method is by polarised light being projected on the described diffraction grating and diffracted, accept the described diffraction light line data of going forward side by side by photosensitive unit and handle the live width obtain grid, the OCD method of measurement can obtain the live width at positions such as grid upper, middle and lower, can judge the profile of gate lateral wall according to the live width that records positions such as grid upper, middle and lower.With respect to the existing method that needs by the destructiveness monitoring gate lateral wall profile of section (Crosss section) and SEM, the OCD method of measurement can be by measuring the side wall profile of grid, and needn't cut, simplified technology, reduced expense and and the profile of the grid of monitoring etching that can be real-time, so that the etching technics parameter is adjusted, make the gate profile that forms reach requirement.
After finishing measurement, the described first semiconductor-based end, removed etching apparatus, finish manufacturing (S460) described grid to the suprabasil grid of described first semiconductor.
According to the measurement result of the suprabasil grid live width of described first semiconductor is judged whether described gate bottom has sufficient shape profile (S440);
If judgement learns that the suprabasil gate bottom of described first step semiconductor has sufficient shape profile according to measurement result, this result is fed back to described first chamber, to carrying out directed oxygen gas plasma etching (S450) in the second semiconductor-based end of finishing the grid manufacturing in described first chamber.According to the time that the measurement result of the suprabasil grid live width of described first semiconductor is determined the suprabasil grid of described second semiconductor is carried out directed oxygen gas plasma etching, described directed oxygen gas plasma is an oxygen gas plasma.The direction of described directed oxygen gas plasma and the angle of described semiconductor-based basal surface are 70 to 90 degree, the pressure of the environment of described directed oxygen gas plasma is 2 to 15Torr, the radio frequency source power that produces described oxygen gas plasma is 100 to 1000 watts, and the flow of oxygen is 50 to 500sccm.Judge whether the follow-up suprabasil grid of second semiconductor is carried out directed oxygen gas plasma etching and the time of carrying out directed oxygen plasma etching by measurement to grid at the first semiconductor-based end, finish the suprabasil grid of described second semiconductor carried out the directional plasma etching after, measure the live width of the suprabasil grid of this second semiconductor and judge its side wall profile by OCD again, with as whether the follow-up suprabasil grid of the 3rd semiconductor being carried out the directed etching of plasma ..., and the like, the described feedback of method can to(for) a plurality of semiconductor-based end of continuous manufacturing makes the grid that forms on each semiconductor-based end have profile preferably.This method can avoid the semiconductor substrate between first chamber and second chamber repeatedly transmission and repeatedly expose to the open air with external environment condition in, can save time simultaneously.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1. the manufacture method of a grid comprises:
The semiconductor substrate is provided, on the described semiconductor-based end, forms conductive layer;
Spin coating photoresist layer and carry out graphically on described conductive layer forms gate pattern;
By etching described gate pattern is transferred on the described conductive layer, formed grid;
Described grid is carried out oxygen directional plasma etching;
Wherein, the angle of the direction of described directional plasma etching and described semiconductor-based basal surface is 70 to 90 degree.
2. the manufacture method of grid as claimed in claim 1 is characterized in that: the pressure of the environment of described oxygen gas plasma is 2 to 15Torr.
3. the manufacture method of grid as claimed in claim 1, it is characterized in that: the radio frequency source power that produces described oxygen gas plasma is 100 to 1000 watts.
4. the manufacture method of grid as claimed in claim 1 is characterized in that: the flow that produces the oxygen of described oxygen gas plasma is 50 to 500sccm.
5. the manufacture method of grid as claimed in claim 1, it is characterized in that: described conductive layer is a kind of or its combination in polysilicon, the metal silicide.
6. the manufacture method of grid as claimed in claim 1, it is characterized in that: this method further comprises: remove described photoresist layer by ashing, and carry out wet-cleaned.
7. the manufacture method of grid as claimed in claim 1 is characterized in that: described grid is carried out the step of directional plasma etching and described gate pattern transferred to the step original position execution that forms grid on the described conductive layer by etching.
8. the manufacture method of a grid comprises:
The semiconductor substrate is provided, on the described semiconductor-based end, forms conductive layer;
Spin coating photoresist layer and carry out graphically on described conductive layer forms gate pattern;
By etching described gate pattern is transferred on the described conductive layer, formed grid;
Adopt optics critical size method of measurement to measure the live width of described grid, judge according to measurement result whether described gate bottom has sufficient shape profile,, described grid is carried out the directional plasma etching with oxygen gas plasma if having; Wherein, the angle of the direction of described directional plasma etching and described semiconductor-based basal surface is 70 to 90 degree;
If do not have, finish the manufacturing of grid.
9. the manufacture method of grid as claimed in claim 8 is characterized in that: according to the time of the measurement result decision of described grid live width being carried out the directional plasma etching to described grid.
10. the manufacture method of a grid comprises:
On the first semiconductor-based end, form conductive layer;
Spin coating photoresist layer and carry out graphically on described conductive layer forms gate pattern;
By etching described gate pattern is transferred on the described conductive layer, formed grid;
Adopt optics critical size method of measurement to measure the live width of described grid;
Judge according to measurement result whether described gate bottom has sufficient shape profile;
If have, the grid that forms is carried out the directional plasma etching at the second follow-up semiconductor-based end with oxygen gas plasma; Wherein, the angle of the direction of described directional plasma etching and described semiconductor-based basal surface is 70 to 90 degree;
If do not have, need not the grid that forms is carried out described directional plasma etching at the second follow-up semiconductor-based end.
11. the manufacture method of grid as claimed in claim 10 is characterized in that: the time of the grid that forms being carried out at the second follow-up semiconductor-based end the directional plasma etching according to the measurement result decision of the suprabasil grid of first semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101190615A CN101197262B (en) | 2006-12-04 | 2006-12-04 | Grids production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101190615A CN101197262B (en) | 2006-12-04 | 2006-12-04 | Grids production method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101197262A CN101197262A (en) | 2008-06-11 |
| CN101197262B true CN101197262B (en) | 2010-06-09 |
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| CN102136418B (en) * | 2010-01-27 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for grid etching |
| CN102270573A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid |
| CN104681416B (en) * | 2013-11-27 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices and grid |
| CN104241100A (en) * | 2014-09-23 | 2014-12-24 | 上海华力微电子有限公司 | Small-size graph making method |
| CN113053771B (en) * | 2021-03-17 | 2022-05-24 | 长鑫存储技术有限公司 | Method for judging contour of semiconductor structure |
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| US6686292B1 (en) * | 1998-12-28 | 2004-02-03 | Taiwan Semiconductor Manufacturing Company | Plasma etch method for forming uniform linewidth residue free patterned composite silicon containing dielectric layer/silicon stack layer |
| CN1700421A (en) * | 2004-05-21 | 2005-11-23 | 中国科学院微电子研究所 | Method for forming nanowire wide polycrystalline silicon gate etching mask images |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6686292B1 (en) * | 1998-12-28 | 2004-02-03 | Taiwan Semiconductor Manufacturing Company | Plasma etch method for forming uniform linewidth residue free patterned composite silicon containing dielectric layer/silicon stack layer |
| CN1700421A (en) * | 2004-05-21 | 2005-11-23 | 中国科学院微电子研究所 | Method for forming nanowire wide polycrystalline silicon gate etching mask images |
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| JP特开平8-340004A 1996.12.24 |
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