CN100576509C - The manufacture method of self-aligned contact hole - Google Patents
The manufacture method of self-aligned contact hole Download PDFInfo
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- CN100576509C CN100576509C CN200610119142A CN200610119142A CN100576509C CN 100576509 C CN100576509 C CN 100576509C CN 200610119142 A CN200610119142 A CN 200610119142A CN 200610119142 A CN200610119142 A CN 200610119142A CN 100576509 C CN100576509 C CN 100576509C
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Abstract
A kind of manufacture method of self-aligned contact hole comprises: the semiconductor substrate is provided, has two grids at least on the described semiconductor-based end; Form etching barrier layer along described gate surface, form dielectric layer on described etching barrier layer, the top of described dielectric layer is higher than described top portions of gates; Form the contact hole pattern of photoresist on described dielectric layer, and form T type opening in the described dielectric layer by being etched in, the bottom of described opening is between described two grids; Remove described photoresist; Sidewall and bottom by the described opening of wet-cleaned; Etching is removed the etching barrier layer of described opening sidewalls and bottom.The defective that does not open the contact hole bottom and the grid shoulder is pruned in the manufacture method of self-aligned contact hole can be eliminated or reduce to this method.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of self-aligned contact hole.
Background technology
Along with dimensions of semiconductor devices reduces day by day, device cell integrated on the unit are is more and more, and the density of device also strengthens gradually, and the size between the device constantly reduces, and this has also strengthened the difficulty of making.For example, at 90nm and following technology node thereof, gap in the memory cell between the grid becomes very little, manufacturing becomes comparatively difficult in order to the technology of the contact hole of connection source, drain electrode and upper strata metal wire in the gap between above-mentioned grid, the manufacture method that industry is introduced self aligned contact hole overcomes this difficulty, and number of patent application is the manufacture method that 200510055489.3 Chinese patent discloses a kind of self-aligned contact hole.Fig. 1～Fig. 4 is the generalized section of each step corresponding structure of manufacture method of the self-aligned contact hole of this patent disclosure.
As shown in Figure 1, one semiconductor substrate 100 with different components structure such as field and trap (not shown) at first is provided, on described semiconductor substrate 100, be formed with a plurality of grid structures, wherein said grid structure forms by first hard mask layer 102 and the grid conductive layer 101 that piles up, and described grid conductive layer 101 materials are a kind of or combination in polysilicon, tungsten, tungsten nitride and the tungsten silicide.Described first hard mask layer 102 is a kind of in silicon nitride, the silica.Form etching barrier layer 103 on the described semiconductor substrate 100 that is formed with grid structure, described etching barrier layer 103 materials are silicon nitride.Then, form insulating barrier 104 on described etching barrier layer 103, described insulating barrier 104 can be the silicon boron glass, a kind of in the boron-phosphorosilicate glass.
As shown in Figure 2, by the described insulating barrier 104 of chemico-mechanical polishing planarization, and the etching barrier layer 103 on described first hard mask layer 102 is exposed.On described insulating barrier 104, form second hard mask layer 105, spin coating photoresist 106 and form contact hole pattern on described second hard mask layer 105 by exposure imaging.
As shown in Figure 3, described second hard mask layer 105 of etching is transferred to the contact hole pattern in the described photoresist 106 in second hard mask layer 105, removes described photoresist 106.
As the barrier layer, the described insulating barrier 104 of etching forms contact hole 107 as shown in Figure 4 with second hard mask layer 105, till being etched to etching barrier layer 103 on the substrate between the grid structure and exposing.Simultaneously, second hard mask layer 105 also is etched away as sacrifice layer.Remove 103 materials of the etching barrier layer on the pole plate between the described grid structure by etching again, and remove the polymer residue that in etch process, produces by buffer oxide etch liquid (BOE).
The method that adopts when the described insulating barrier 104 of etching forms contact hole 107 is a dry etching, and main etching gas is the plasma of fluoro-gas, for example C
2F
4, C
3F
8Deng, the plasma of described fluorine-containing gas can produce polymer when the described insulating barrier 104 of etching, the polymer that produces is attached to the bottom of the contact hole of etching formation, can influence further etching to etching barrier layer 103, increased the time of etching, make etching gas damage the shoulder of described first hard mask layer 102 simultaneously, form defective 110 as shown in Figure 4.
The process of existing another kind of autoregistration etching is as follows:
As shown in Figure 5; on semi-conductive substrate 200, be formed with grid 202; described grid both sides are formed with side wall layer (spacer); the top is formed with the protective layer (not shown); between described grid 202 and substrate 200, oxide layer 201 is arranged, be formed with source electrode and drain electrode (not shown) in the described substrate 200.The side wall layer and the protective layer outside at described Semiconductor substrate 200 and grid 202 form an etching barrier layer 203, and described etching barrier layer 203 is a silicon nitride, forms an insulating barrier 204 on described.
As shown in Figure 6, on described insulating barrier 204, form photoresist layer and form contact hole pattern 207.
As shown in Figure 7, the insulating barrier 204 of the described contact hole pattern of etching 207 bottoms forms contact hole 207a.
As shown in Figure 8, continue etching and remove the etching barrier layer 203 of described contact hole 207a sidewall and bottom, then by oxygen gas plasma bombardment (O
2Flash) sidewall of described contact hole 207a is then removed described photoresist layer 206 to remove the polymer that etching process produces, and cleans the polymer of described trenched side-wall and bottom again with diluent hydrofluoric acid solution.Described method has following defective: because at the fluorine-containing gas of etching gas multidigit of the dry plasma of described insulating barrier 204 processes of etching, in etching process, generate polymer easily, the polymer that generates can be attached to the sidewall and the bottom of the opening that etches, stop further carrying out of etching, thereby make the etching comparatively difficulty that becomes when removing the following etching barrier layer 203 of contact hole 207a, form the defective of not opening bottom the contact hole 207a easily; On the other hand, can etching the prune shoulder of described grid of etching gas forms defective 208 as shown in Figure 9, if this semiconductor device is a random asccess memory, then easily causes word line and bitline short circuits.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of self-aligned contact hole, with the problem that does not open the contact hole bottom and the grid shoulder is pruned in the manufacture method that solves existing self-aligned contact hole.
For achieving the above object, the manufacture method of a kind of self-aligned contact hole provided by the invention comprises: the semiconductor substrate is provided, has two grids at least on the described semiconductor-based end; Form etching barrier layer along described gate surface, form dielectric layer on described etching barrier layer, the top of described dielectric layer is higher than described top portions of gates; Form the contact hole pattern of photoresist on described dielectric layer, and form the T-shape opening in the described dielectric layer by being etched in, the bottom of described opening is between described two grids; Remove described photoresist; Sidewall and bottom with the described opening of wet-cleaned; Etching is removed the etching barrier layer of described opening sidewalls and bottom.
Described etching barrier layer is a kind of in silicon nitride, the carborundum.
Described dielectric layer is a kind of or its combination in phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, black diamond, the spin-coating glass.
Use C
4F
8And CH
2H
2Mist described dielectric layer is carried out etching, and use Ar and CO as assist gas.
Use CHF
3Described etching barrier layer is carried out etching, and use Ar and O
2As assist gas.
The cleaning fluid of described wet-cleaned is the hydrofluoric acid of dilution.
Accordingly, the present invention also provides a kind of manufacture method of self-aligned contact hole, comprise: a semiconductor-based end that has two grids at least is provided, described gate surface is formed with first dielectric layer in upper edge, the described semiconductor-based end, be formed with second dielectric layer on described first dielectric layer, the top of described second dielectric layer is higher than described top portions of gates; In described second dielectric layer, form the T-shape opening, and the bottom of described opening is between described two grids; Sidewall and bottom by the described opening of wet-cleaned; Remove first dielectric layer of described open bottom.
Described first dielectric layer is a silicon nitride, a kind of in the carborundum.
Described second dielectric layer is a kind of or its combination in phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, black diamond, the spin-coating glass.
The step that forms the T-shape opening in described second dielectric layer is as follows: spin coating photoresist layer and form contact hole pattern on described second dielectric layer; Second dielectric layer to described first dielectric layer of the described contact hole pattern of etching bottom exposes; Remove described photoresist layer by ashing.
The cleaning fluid of described wet-cleaned is the hydrofluoric acid of dilution.
The present invention also provides a kind of manufacture method of autoregistration opening, comprise: the semiconductor substrate is provided, on the described semiconductor-based end, be formed with at least two projections, be formed with first dielectric layer on described projection surface, upper edge, the described semiconductor-based end, be formed with second dielectric layer on described first dielectric layer, the top of described second dielectric layer is higher than the top of described projection; Form the T-shape opening in described second dielectric layer, the bottom of described opening is between described two projections; Sidewall and bottom by the described opening of wet-cleaned; Remove first dielectric layer of described opening sidewalls and bottom.
Described projection is transistorized grid, and described first dielectric layer is a silicon nitride, and described second dielectric layer is a low dielectric constant insulating material.
Compared with prior art, the present invention has the following advantages:
The technology of described dielectric layer and etching barrier layer is decomposed into three step process with etching when forming self-aligned contact hole in the present invention: the first step forms "T"-shaped opening by being etched in the described dielectric layer, and described first time etching stopping when described etching barrier layer exposes till, then with the sidewall of the described opening of wet-cleaned and bottom to remove the polymer that deposits when the first step etching, then remove the etching barrier layer material of described open bottom and sidewall once more with dry etching.The inventive method has been removed attached to the polymer on the etching barrier layer in the described opening by wet-cleaned, guaranteed when etching is removed described etching barrier layer, to carry out smoothly, and reduced time of etching, thereby make the contact hole bottom of formation have bigger live width and profile preferably; In addition, because the described etching barrier layer of etching is comparatively smooth, the time of etching is also shorter, makes that etching gas causes less damage or can not cause damage top portions of gates when etching is removed described etching barrier layer, has improved the process window of etching.
Available technology adopting dry method oxygen gas plasma etching (O
2Flash) remove polymer in the described opening, still, excessive oxygen flow causes the state labile of chamber easily in the described dry method oxygen gas plasma; Described oxygen gas plasma also can cause damage to the photoresist layer on the described dielectric layer simultaneously, causes the live width of the open top that forms after the etching excessive, easily causes the connection between the contact hole; In addition, the oxygen gas plasma of dry method can only the part the described opening of removing in polymer; The present invention adopts wet-cleaned to replace the oxygen gas plasma etching of dry method to remove the polymer of described open bottom and sidewall with respect to prior art, has overcome the shortcoming of above-mentioned dry method oxygen gas plasma etching.
Description of drawings
Fig. 1 to Fig. 4 is the generalized section of the manufacture method corresponding construction of existing a kind of self-aligned contact hole;
Fig. 5 to Fig. 9 is the generalized section of the manufacture method corresponding construction of existing another kind of self-aligned contact hole;
Figure 10 is the flow chart of first embodiment of the manufacture method of self-aligned contact hole of the present invention;
Figure 11 to Figure 17 is the generalized section of each step corresponding structure of first embodiment of the manufacture method of self-aligned contact hole of the present invention;
Figure 18 is the flow chart of second embodiment of the manufacture method of self-aligned contact hole of the present invention;
Figure 19 is the flow chart of the 3rd embodiment of method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The manufacture method of self-aligned contact hole of the present invention at first has formation etching barrier layer and dielectric layer at least at the semiconductor-based end of two gate bumps, spin coating photoresist and form contact hole pattern on described dielectric layer then, form opening by being etched in the described dielectric layer, the bottom of described opening is between described two grids, pass through the sidewall and the bottom of the described opening of wet-cleaned then, the polymer that removal produces when etching, then remove the etching barrier layer of described opening sidewalls and bottom again by dry etching, form contact hole.The inventive method is divided into first step dry etching, wet-cleaned, the second step dry etching three step process with the technology that etching forms contact hole, remove the polymer that first step dry etching produces by wet-cleaned, carry out the second step etching then, avoided the polymer of described first step etching to go on foot the influence of etching to second and cause open bottom not opened, also alleviated of the reduction of the second step etching gas described grid shoulder.
Figure 10 is the flow chart of first embodiment of the manufacture method of self-aligned contact hole of the present invention.
As shown in figure 10, at first, provide a semiconductor-based end (S100) that has two grids at least, described grid is the stack architecture of polysilicon or polysilicon and metal silicide, be formed with side wall in described grid both sides, side wall is a kind of or its combination in silica, the silicon nitride.In the described semiconductor-based end, be formed with shallow trench isolation to be formed with the source region, in described active area, be formed with source electrode and drain electrode.
Form etching barrier layer along described gate surface, on described etching barrier layer, form dielectric layer (S110).Described etching barrier layer is a kind of in silicon nitride, the carborundum, and its thickness is 50 to 600A, and the mode of formation is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).Described dielectric layer is a kind of or its combination in phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, black diamond, the spin-coating glass.The top of described dielectric layer is higher than the top of described grid, and its formation method can be a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), the ald.The dielectric layer of deposition passes through cmp so that the upper surface planarization.
Spin coating photoresist on described dielectric layer, and by exposure imaging formation contact hole pattern, described contact hole pattern is between described two grids, its live width is greater than the distance between described two grids, with described photoresist layer as resist, the dielectric layer of the described contact hole pattern of etching below, in described dielectric layer, form the T-shape opening, the bottom of described opening is between described two grids (S120), the gas of the described dielectric layer of etching is the mist of C4F8, CH2H2, and uses Ar and CO as assist gas.
Remove described photoresist by the oxygen gas plasma ashing, and clean (S130) with the mixed solution of sulfuric acid and hydrogen peroxide.
By the sidewall and the bottom of the described opening of wet-cleaned, remove the polymer (S140) that when the described dielectric layer of etching forms opening, produces.The cleaning fluid that wet-cleaned is selected for use is the hydrofluoric acid of dilution.Owing to when the described dielectric layer of etching forms opening, select fluorine-containing gas for use, in etching process, can produce polymer, described polymer can deposit and attached to the bottom and the sidewall of the opening that forms, if do not remove, can stop further etching to lower floor's etching barrier layer, thereby make etching gas carry out etching to described top portions of gates for a long time, cause the grid shoulder to be pruned, this step can be removed polymer attached to described opening sidewalls and bottom by the hydrofluoric acid of dilution, guaranteed next step can be thoroughly fully and remove the etching barrier layer of described opening sidewalls and bottom in the short period.
Remove the etching barrier layer (S150) of described opening sidewalls and bottom by etching.The gas of the described etching barrier layer of etching is CHF
3, and use Ar and O
2As assist gas.Etching terminal monitor layer when described etching barrier layer forms opening as the described dielectric layer of etching; can protect the not damage of subject plasma of grid when forming described T-shape opening; behind the formation opening in described dielectric layer; need to remove by the method for etching; expose source electrode or drain electrode with the contact hole bottom that guarantee to form at described the semiconductor-based end, thereby in described contact hole, fill the metal interconnecting wires conducting that metal for example can make source electrode or drain electrode and upper strata behind the electric conducting material such as tungsten.
The present invention is decomposed into three step process with the technology of described dielectric layer of etching and etching barrier layer when forming self-aligned contact hole, the first step is etched in and forms "T"-shaped opening in the described dielectric layer, and described first time etching stopping when described etching barrier layer exposes till, use the sidewall and the bottom of the described opening of wet-cleaned then, to remove the polymer that deposits when the first step etching, then remove the etching barrier layer material of described open bottom and sidewall once more with dry etching.The inventive method has been removed attached to the polymer on the etching barrier layer in the described opening by wet-cleaned, guaranteed when etching is removed described etching barrier layer, to carry out smoothly, and reduced time of etching, thereby make the contact hole bottom of formation have bigger live width and profile preferably; In addition, because the described etching barrier layer of etching is comparatively smooth, the time of etching is also shorter, makes that etching gas causes less damage or can not cause damage top portions of gates when etching is removed described etching barrier layer, has improved the process window of etching.
Below in conjunction with profile the inventive method is described in detail.Figure 11 to Figure 17 is the generalized section of each step corresponding structure of first embodiment of the manufacture method of self-aligned contact hole of the present invention.
As shown in figure 11, provide semiconductor substrate 300, in the described semiconductor-based end 300, isolated groove 301 is arranged, in described isolated groove 301, be filled with insulating material for example silica, silicon nitride or its combination.Described isolated groove 301 can be that shallow trench isolation is from (STI) or carrying out local oxide isolation (LOCOS).In the active area at the described semiconductor-based end 300, be formed with source electrode 306 and drain electrode 304.Be formed with oxide layer 302 on the described semiconductor-based end 300, it can be a kind of in silica or the carbon oxygen silicon compound.Be formed with grid 303 on described oxide layer 302, described grid 303 is the stack architecture of polysilicon layer or polysilicon and metal silicide, and described metal silicide can be a titanium silicide, nickle silicide, cobalt silicide, tungsten silicide, a kind of or its combination in the tantalum silicide.On described grid 303, be formed with silicon nitride layer 307, described silicon nitride layer 307 as the mask layer of grid 303 in order to protect described grid 303 injury-free in subsequent technique.Be formed with side wall 305 in described grid 303 outsides, its material can be a kind of or its combination in silica, the silicon nitride, and side wall described in the present embodiment 305 is a silicon nitride.
As shown in figure 12, on the described semiconductor-based end 300 with grid 303, form etching barrier layer 308 along described gate surface.Described etching barrier layer 308 is a kind of in silicon nitride, the carborundum, and its thickness is 50 to 600, and the mode of formation is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).Etching barrier layer described in the present embodiment 308 is a silicon nitride.Described etching barrier layer 308 protects described grid 303 and the semiconductor-based end 300 injury-free in follow-up etching technics as grid 303 and the protective layer at the described semiconductor-based end 300.
As described in Figure 13, form dielectric layer 309 on described etching barrier layer 308, the top of described dielectric layer 309 is higher than the top of described grid.Described dielectric layer 309 is a kind of in phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, black diamond, the spin-coating glass or its combination, and its formation method is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD) or the ald.Dielectric layer described in the present embodiment 309 is a boron-phosphorosilicate glass.Come the upper surface of the described dielectric layer 309 of planarization by cmp.
As shown in figure 14, spin coating photoresist layer 310 and form contact hole pattern 311 on described dielectric layer 309 by exposure imaging, described contact hole pattern 311 is between described two grids and across the top of two grids, its concrete steps are as follows: spin coating anti-reflecting layer (not shown) on described dielectric layer 309 at first, described anti-reflecting layer is in order to reduce the reverberation of 309 upper surfaces of dielectric layer described in the post-exposure technology, thereby alleviate or eliminate the deterioration of the photoresist pattern contour that reverberation causes, for example fall trapezoidal photoresist pattern contour.The photoresist coating apparatus is sent at the described semiconductor-based end 300 that has anti-reflecting layer, at first pass through after the surface treatment spin coating photoresist on described anti-reflecting layer, described photoresist is a chemically-amplified resist, needs after the exposure to finish sensitization technology through further toasting.The exposure light source wavelength of chemically-amplified resist is 248nm or 193nm, or even 157nm.Remove solvent in the photoresist by soft roasting (Softbake) after finishing the spin coating photoresist, send into scanning type exposure machine (scanner) then and expose, the pattern that pre-defines on the mask plate (reticle) is transferred on the described chemically-amplified resist by exposure; Make exposure finish by postexposure bake (Post exposure bake), generate the material that dissolves in developer solution,, form contact hole pattern 311 by developing and washing and remove described soluble substance.Be not retained on the described dielectric layer 309 by the photoresist pattern of sensitization.
As described in Figure 15, the dielectric layer 309 of the described contact hole pattern of etching 311 belows, the gas of the described dielectric layer of etching is C
4F
8, CH
2H
2Mist, and use Ar and CO as assist gas.Be etched in when described etching barrier layer 308 exposes and stop, because the material silicon nitride of etching barrier layer 308 and the material boron-phosphorosilicate glass of dielectric layer 309 have different etch rates, etch rate to described etching barrier layer 308 is slower, and it is very fast to the etch rate of described dielectric layer 309, when the etching barrier layer 308 that is etched to top portions of gates exposes, etching gas begins the etching barrier layer 308 of top portions of gates is carried out etching with slower etch rate, simultaneously with the dielectric layer between two grids of speed etching faster, till when the etching barrier layer 308 at the semiconductor-based end 300 between two grids exposes, thereby in described dielectric layer 309, form " T " opening 312.
As shown in figure 16, remove described photoresist layer 310, and clean to remove the photoresist residue with sulfuric acid solution by oxygen gas plasma ashing (ashing).
Then, by the sidewall and the bottom of the described opening 312 of wet-cleaned, remove the polymer that when the described dielectric layer 309 of etching forms opening 312, produces.Wet method is carved and is cleaned the hydrofluoric acid of cleaning fluid for diluting of selecting for use.Owing to when the described dielectric layer 309 of etching forms opening 312, select fluorine-containing gas for use, in etching process, can produce polymer, described polymer can deposit and attached to the bottom and the sidewall of described opening 312, if do not remove, can stop further etching to lower floor's etching barrier layer 308, increase the time of etching, thereby make etching gas carry out etching to described top portions of gates, cause the grid shoulder to be pruned, this step can be removed polymer attached to described opening 312 sidewalls and bottom by the hydrofluoric acid of dilution, has guaranteed that next step can thoroughly remove the etching barrier layer 308 of described opening 312 sidewalls and bottom completely.
After finishing the cleaning to described opening 312 sidewalls and bottom, remove the etching barrier layer 308 of described opening 312 sidewalls and bottom by etching, etching gas is CHF
3, and use Ar and O
2As assist gas, form contact hole 312 as shown in figure 17.Filled conductive material such as metal material in described contact hole 312 form contact plug.
Figure 18 is the flow chart of second embodiment of the manufacture method of self-aligned contact hole of the present invention.
As shown in figure 18, provide a semiconductor-based end that has two grids at least, on the described semiconductor-based end, be formed with first dielectric layer and second dielectric layer (S200).Described first dielectric layer is a kind of in silicon nitride, the carborundum, and first dielectric layer described in the present embodiment is a silicon nitride; Described second dielectric layer is a kind of or its combination in phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, black diamond, the spin-coating glass.Second dielectric layer described in the present embodiment is a boron-phosphorosilicate glass.The top of described second dielectric layer is higher than the top of described grid.
In described second dielectric layer, form the T-shape opening, and the bottom of described opening is between described two grids (S210).The gas of described second dielectric layer of etching is C
4F
8, CH
2H
2Mist, and use Ar and O
2As assist gas.The step that forms the T-shape opening in described second dielectric layer is as follows, spin coating photoresist layer on described second dielectric layer, and by exposure imaging formation contact hole pattern, described contact hole pattern is between described two grids; Second dielectric layer to described first dielectric layer of the described contact hole pattern of etching bottom exposes; Remove described photoresist layer by ashing, the method for removing described photoresist layer is oxygen gas plasma dry etching and sulfuric acid solution wet-cleaned.
Sidewall and top with the described T-shape opening of hydrofluoric acid clean that dilutes, removal when forming described " T " opening attached to the polymer (S220) of described open bottom and sidewall, described polymer has stoped in next step technology the etching to described first dielectric layer, wet-cleaned by this step, can remove described polymer, guarantee carrying out smoothly of time road etching technics.
After finishing wet-cleaned to described opening, using gases CHF
3Described first dielectric layer is carried out etching, and use Ar and O
2As assist gas, remove first dielectric layer of described " T " opening sidewalls and bottom, form contact hole (S230).
Figure 19 is the flow chart of the 3rd embodiment of the inventive method.As shown in figure 19, at first provide the semiconductor substrate, be formed with at least two projections on the described semiconductor-based end, projection described in the present embodiment is a grid, is formed with side wall protective layer in described grid both sides; Be formed with first dielectric layer on described projection surface, upper edge, the described semiconductor-based end, first dielectric layer described in the present embodiment is a silicon nitride; Be formed with second dielectric layer on described first dielectric layer, the top of described second dielectric layer is higher than the top of described projection, and described second dielectric layer is an advanced low-k materials, and second dielectric layer described in the present embodiment is boron-phosphorosilicate glass (S300).
Spin coating photoresist and form patterns of openings on described second dielectric layer by exposure imaging, described patterns of openings is between described two projections, remove second dielectric layer of described patterns of openings bottom then by dry plasma, form "T"-shaped opening, the bottom of described opening is between described two projections (S310).Till when being etched to described first dielectric layer and exposing.The gas of described second dielectric layer of etching is fluorine-containing gas, for example, and CF
4, C
3F
8, C
4F
8, CH
2H
2Deng, etching gas is C in the present embodiment
4F
8, CH
2H
2Mist.
Sidewall and top with the described T-shape opening of hydrofluoric acid clean that dilutes, removal when forming described " T " opening attached to the polymer (S320) of described open bottom and sidewall, described polymer has stoped next step etching to described first dielectric layer, wet-cleaned by this step, can remove described polymer, guarantee carrying out smoothly of time road etching technics.
Remove first dielectric layer (S330) of described open bottom and sidewall with dry plasma.The etching gas of dry plasma described in the present embodiment is CHF
3In the present embodiment by before described first dielectric layer of etching, removing the polymer cover on described first dielectric layer with wet-cleaned, guaranteed the etching of described first dielectric layer is carried out smoothly, and can shorten etch period, reduced when described first dielectric layer of etching etching gas to the damage at described projection top, and help to form bottom profile opening preferably, improved control ability and process window to technology.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1, a kind of manufacture method of self-aligned contact hole comprises:
The semiconductor substrate is provided, on the described semiconductor-based end, has two grids at least;
Form etching barrier layer along described gate surface, form dielectric layer on described etching barrier layer, the top of described dielectric layer is higher than described top portions of gates;
Form the contact hole pattern of photoresist on described dielectric layer, and form the T-shape opening in the described dielectric layer by being etched in, the bottom of described opening is between described two grids;
Remove described photoresist;
With the sidewall and the bottom of the described opening of wet-cleaned, with the polymer that direct removal produces when the described dielectric layer of etching forms the T-shape opening, the cleaning fluid of described wet-cleaned is the hydrofluoric acid of dilution;
Etching is removed the etching barrier layer of described opening sidewalls and bottom.
2, the manufacture method of self-aligned contact hole as claimed in claim 1 is characterized in that: described etching barrier layer is a kind of in silicon nitride, the carborundum.
3, the manufacture method of self-aligned contact hole as claimed in claim 1 is characterized in that: described dielectric layer is a kind of or its combination in phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, black diamond, the spin-coating glass.
4, the manufacture method of self-aligned contact hole as claimed in claim 1 is characterized in that: use C
4F
8And CH
2H
2Mist described dielectric layer is carried out etching, and use Ar and CO as assist gas.
5, the manufacture method of self-aligned contact hole as claimed in claim 1 is characterized in that: use CHF
3Described etching barrier layer is carried out etching, and use Ar and O
2As assist gas.
6, a kind of manufacture method of self-aligned contact hole comprises:
The one semiconductor-based end that has two grids at least was provided, and described gate surface is formed with first dielectric layer in upper edge, the described semiconductor-based end, is formed with second dielectric layer on described first dielectric layer, and the top of described second dielectric layer is higher than described top portions of gates;
In described second dielectric layer, form the T-shape opening, and the bottom of described opening is between described two grids;
By the sidewall and the bottom of the described opening of wet-cleaned, with the polymer that direct removal produces when the described dielectric layer of etching forms the T-shape opening, the cleaning fluid of described wet-cleaned is the hydrofluoric acid of dilution;
Remove first dielectric layer of described open bottom.
7, the manufacture method of self-aligned contact hole as claimed in claim 6 is characterized in that: described first dielectric layer is a silicon nitride, a kind of in the carborundum.
8, the manufacture method of self-aligned contact hole as claimed in claim 6 is characterized in that: described second dielectric layer is a kind of or its combination in phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, black diamond, the spin-coating glass.
9, the manufacture method of self-aligned contact hole as claimed in claim 6 is characterized in that: the step that forms the T-shape opening in described second dielectric layer is as follows:
Spin coating photoresist layer and form contact hole pattern on described second dielectric layer;
Second dielectric layer to described first dielectric layer of the described contact hole pattern of etching bottom exposes;
Remove described photoresist layer by ashing.
10, a kind of manufacture method of autoregistration opening comprises:
The semiconductor substrate is provided, on the described semiconductor-based end, be formed with at least two projections, be formed with first dielectric layer on described projection surface, upper edge, the described semiconductor-based end, be formed with second dielectric layer on described first dielectric layer, the top of described second dielectric layer is higher than the top of described projection;
Form the T-shape opening in described second dielectric layer, the bottom of described opening is between described two projections;
By the sidewall and the bottom of the described opening of wet-cleaned, with the polymer that direct removal produces when the described dielectric layer of etching forms the T-shape opening, the cleaning fluid of described wet-cleaned is the hydrofluoric acid of dilution;
Remove first dielectric layer of described opening sidewalls and bottom.
11, the manufacture method of autoregistration opening as claimed in claim 10 is characterized in that: described projection is transistorized grid, and described first dielectric layer is a silicon nitride, and described second dielectric layer is a low dielectric constant insulating material.
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|---|---|---|---|
| CN200610119142A CN100576509C (en) | 2006-12-05 | 2006-12-05 | The manufacture method of self-aligned contact hole |
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| CN101651103B (en) * | 2008-08-14 | 2012-05-16 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor device |
| CN102097360B (en) * | 2009-12-10 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | The method of etching connection hole |
| CN102446815B (en) * | 2010-10-14 | 2016-03-16 | 中芯国际集成电路制造(上海)有限公司 | Form the method for interconnection channel and through hole and form the method for interconnection structure |
| CN102468223A (en) * | 2010-11-16 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN103066011B (en) * | 2011-10-20 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN102723294B (en) | 2012-06-20 | 2015-04-22 | 上海华力微电子有限公司 | Method for detecting registration between contact hole and polycrystalline silicon gate |
| CN103681604B (en) * | 2012-09-07 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices with self-aligned contact hole and preparation method thereof |
| US10026838B2 (en) * | 2016-02-25 | 2018-07-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor and manufacturing method thereof |
| CN107665856B (en) * | 2016-07-29 | 2020-04-03 | 中微半导体设备(上海)股份有限公司 | Method for forming contact hole and plasma etching method |
| CN108511342B (en) * | 2017-02-24 | 2021-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN108597982A (en) * | 2018-01-12 | 2018-09-28 | 上海华虹宏力半导体制造有限公司 | Wafer processing method |
| CN113437066B (en) * | 2021-06-23 | 2024-04-12 | 福建省晋华集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
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