KR100942980B1 - METHOD FOR FABRICATION OF SELF ALIGN CONTACT HOLE OF SEMICONDUCTOR DEVICE USING ArF PHOTO LITHOGRAPHY - Google Patents

Abstract

The present invention can secure a vertical etching profile during the self-aligned contact etching process of a semiconductor device using a more advanced exposure source such as F ₂ or argon fluoride (ArF), and can secure a wide critical dimension at the bottom of the contact. To provide a method for forming a self-aligned contact hole of a semiconductor device using an argon fluoride exposure source, the present invention comprises the steps of forming a plurality of neighboring conductive patterns on the substrate; Depositing an insulating film on the conductive pattern; Forming a sacrificial film for a hard mask on the insulating film; Forming a photoresist pattern using an ArF exposure source to form contact holes between the conductive patterns on the hard mask sacrificial layer; Etching the hard mask sacrificial layer by using the photoresist pattern as an etching mask to form a sacrificial hard mask; Defining the contact hole forming region by etching a portion of the insulating layer under an etching condition in which an upper portion of the conductive pattern is exposed using the sacrificial hard mask as an etching mask; Removing the photoresist pattern; Cleaning to expand the opening of the defined contact hole; Forming an etch stop layer according to a profile in which a portion of the insulating layer is etched and cleaned; It provides a method of forming a self-aligned contact hole of a semiconductor device using an ArF exposure source comprising the step of forming a contact hole for exposing the substrate between the conductive pattern by removing the etch stop layer and the insulating film through the entire surface etching. .

ArF, contact hole, etch stop, sacrificial hard mask, SAC.

Description

METHOD FOR FABRICATION OF SELF ALIGN CONTACT HOLE OF SEMICONDUCTOR DEVICE USING ArF PHOTO LITHOGRAPHY}             

1A to 1D are cross-sectional views illustrating a SAC etching process of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10 substrate 11 field oxide film

12 gate insulating film 13 gate conductive film

14: insulating film for hard mask 15: first etching stop film

16: insulating film 17 ': sacrificial hard mask

21 ': second etch stop 23: contact hole

G: gate electrode pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a pattern of a semiconductor device, and more particularly, to a self-aligned contact of a semiconductor device using an argon fluoride (ArF) exposure source. ) Forming method.

Since the microfabrication technology that has supported the progress of semiconductor devices is a photolithography technology, it is no exaggeration to say that the improvement in resolution of the technology is directly connected to the future of high integration of semiconductor devices.

The photolithography process is, as is well known, by etching a layer to be etched through a process of forming a photoresist pattern and an etching process using the photoresist pattern as an etch mask. A process of forming a pattern or the like, wherein the photoresist pattern is a process of applying the photoresist on the etched layer, a process of selectively exposing the photoresist using a prepared exposure mask and a predetermined chemical solution, or Through a developing process to remove unexposed portions of the photoresist.

On the other hand, the critical dimension of the pattern that can be implemented by the photolithography process (hereinafter referred to as CD) depends on the wavelength of the light source used in the above exposure process. This is because the CD of the actual pattern is determined by the width of the photoresist pattern that can be realized through the exposure process.

Deep Ultra-violet (DUV) at 248nm (KrF Excimer Laser) through the early stepper that used 636nm (g-line) light source and 365nm (i-line) light source The 248nm DUV photolithography technology has been used for the development of products with 0.18µm design. However, in order to develop a product with a design of 0.15 μm or less, it is necessary to develop a new DUV photolithography technique having a wavelength of 193 nm (ArF Excimer Laser) or 157 nm (F ₂ Laser). However, even if a combination of various techniques for enhancing the resolution in the DUV photolithography technique is impossible to pattern less than 0.1㎛, the development of a photolithography technique having a new light source is actively progressing.

Currently, an exposure apparatus using an ArF (argon fluoride) laser (λ = 193 nm) is being developed to target patterns up to 0.11 mu m. DUV photolithography is superior in terms of performance and resolution compared to i-rays, but process control is not easy. These problems can be divided into optical causes due to short wavelengths and chemical causes due to the use of chemically amplified photoresists. If the wavelength is shortened, the CD shake phenomenon due to the stationary wave effect and the reflection of reflected light due to the substrate phase become worse. CD oscillation refers to a phenomenon in which the line thickness changes periodically as the degree of interference between incident light and reflected light changes depending on the slight thickness difference of the resist or the thickness difference of the substrate film. In the DUV process, chemically amplified photoresist must be used to improve sensitivity, and problems related to the reaction mechanism such as PED (Post Exposure Delay) stability and substrate dependence arise, which is a key task of F ₂ or ArF exposure technology. One is the development of photoresists for F ₂ or ArF. Although F ₂ or ArF is a chemically amplified type such as KrF, it is necessary to fundamentally improve the material. Particularly, development of ArF photoresist material is difficult because benzene rings cannot be used. Benzene rings have been used in photoresists for i-rays and KrF to ensure dry etching resistance. However, for example, when the benzene ring is used in the ArF photoresist, since the absorbance is large at 193 nm, which is the wavelength region of the ArF laser, the transparency is poor and the exposure to the lower portion of the photoresist is impossible. For this reason, research has been conducted on materials that can secure dry etching resistance without having a benzene ring, have good adhesion, and can be developed with 2.38% TMAH (Tetra Methyl Ammonium Hydroxide). To date, many companies and research institutes around the world have been publishing their research results, and the commercialized products are still in the form of polymers of COMA (CycloOlefin-Maleic Anhydride) or Acrylate series, or a mixture thereof. However, the photoresist has the benzene structure as described above.

Therefore, when the etching process is performed to form, for example, a gate electrode pattern, or the like through photolithography using an F ₂ or ArF exposure source, a stripe-shaped pattern may occur, or photoresist may aggregate during etching. (Cluster) Plastic deformation and weakness of the photoresist during etching cause it to drift to one side, which is mainly caused by the uneven thickness of the hard mask layer on the gate electrode pattern. Local mask loss of hard mask occurs.

In addition, the CD reduction of the etching opening after etching occurs due to the generation of the slope on the etching profile generated because the SAC etching process uses the selectivity between the nitride film and the oxide film.

In addition, in the case of using the ArF exposure technology, in the case of a device having a design rule of 100 nm or less, the bottom CD of the contact opening after etching is very small (50 nm or less), and considering the etching resistance of the ArF photoresist, Since the selectivity between the nitride film and the oxide film is low because the etching apparatus substrate temperature should be performed at a low temperature of 10 ° C. or lower, the hard mask and the sidewalls of the gate electrode are damaged when the plasma is etched compared to the process technology using the KrF exposure source. It occurs more severely, resulting in the loss of a portion of the sidewalls of the hardmask during subsequent chemical mechanical polishing (CMP) processes after subsequent plug material deposition, increasing the likelihood of SAC defects.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and a vertical etching profile during a self-aligned contact etching process of a semiconductor device using a more advanced exposure source such as F ₂ or argon fluoride (ArF). SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a self-aligning contact hole in a semiconductor device using an argon fluoride exposure source capable of securing a wide critical dimension at the bottom of a contact.

In order to achieve the above object, the present invention comprises the steps of forming a plurality of neighboring conductive patterns on the substrate; Depositing an insulating film on the conductive pattern; Forming a sacrificial film for a hard mask on the insulating film; Forming a photoresist pattern using an ArF exposure source to form contact holes between the conductive patterns on the hard mask sacrificial layer; Etching the hard mask sacrificial layer by using the photoresist pattern as an etching mask to form a sacrificial hard mask; Defining the contact hole forming region by etching a portion of the insulating layer under an etching condition in which an upper portion of the conductive pattern is exposed using the sacrificial hard mask as an etching mask; Removing the photoresist pattern; Cleaning to expand the opening of the defined contact hole; Forming an etch stop layer according to a profile in which a portion of the insulating layer is etched and cleaned; It provides a method of forming a self-aligned contact hole of a semiconductor device using an ArF exposure source comprising the step of forming a contact hole for exposing the substrate between the conductive pattern by removing the etch stop layer and the insulating film through the entire surface etching. .

In the present invention, when the hard mask of the gate electrode pattern is exposed during the SAC etching of the semiconductor device using the ArF exposure source, the etching is first stopped by the end point (Rnd Of Point; EOP). The wet scrubbing removes the polymer and expands the CD. Subsequently, an etch stop film having poor step coverage is deposited along the etch profile in which the opening is extended, and a SAC etching process is performed.

Therefore, since the contact opening is advantageously extended and the etch stop film has poor step coverage, the over-hang structure is deposited on the gate electrode pattern to minimize the loss of the hard mask on the gate electrode pattern. have.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1A to 1D are cross-sectional views illustrating a SAC etching process of a semiconductor device according to an embodiment of the present invention.

1A shows a process cross section in which a photoresist pattern for SAC etching is formed.

Looking at the process in detail, the field oxide film 11 is formed on the substrate 10 on which various elements for forming a semiconductor device are formed through a LOCOS or STI process to separate the active region and the device isolation region.

A plurality of conductive film patterns adjacent to the active region, for example, a gate electrode pattern are formed to deposit an oxide-based gate insulating film 12, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, a tungsten silicide, etc. A metal conduction layer or polysilicon or the like, or a combination of the gate conduction layer 13 is deposited, and then the nitride layer-based hard mask insulation layer 14 is deposited.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed on the hard mask insulating layer 14, and the hard mask insulating layer 14 is etched using the photoresist pattern for forming a gate electrode pattern as an etch mask. The gate electrode pattern is defined.

A photoresist strip process is performed to remove the photoresist pattern, followed by a cleaning process.

Subsequently, the gate conductive film 13 and the gate insulating film 12 are etched using the hard mask insulating film 14 as an etch mask, thereby forming the hard mask insulating film 14 / gate conductive film 13 / gate insulating film 12. A gate electrode pattern G having a stacked structure is formed.

Subsequently, the nitride etch-based first etch stop layer 15 is thinly deposited along the entire profile in which the gate electrode pattern G is formed. The reason for using the nitride-based material as the material of the first etch stop layer 15 is to obtain an etching selectivity with an oxide film mainly used as the insulating layer 16 for interlayer insulation during the SAC etching process for the subsequent plug formation. It is also possible to prevent the etching loss of the gate electrode pattern (G).

Here, a process of forming an impurity bonding layer (not shown) such as a source / drain through an ion implantation process using an ion implantation mask (not shown) between the gate electrode patterns is omitted.

Subsequently, an oxide-based insulating film 16 such as a BOSG (Boro Phospho Silicate Glass) film is formed to sufficiently cover the gate electrode pattern G and the upper portion of the substrate 10.

Here, the insulating film 16 may include, for example, a phossilicate glass (PSG) film or a borosilicate glass (BSG) film in addition to the above-described BPSG film. Entails.

In addition, an HDP (High Density Plasma) oxide film or an APL (Advanced Planarization Layer) film may be used.

Subsequently, a hard mask sacrificial film 17 having an etching selectivity with an oxide film-based insulating film 16 is deposited on the insulating film 16.

The hard mask sacrificial layer 17 may be formed on the chlorine-based gas used in the etching process using the photoresist pattern as an etching mask to overcome the weak etching resistance to the fluorine-based gas of the ArF photoresist pattern during the subsequent etching of the ArF photoresist pattern. Use a material with some degree of etch rate. The most suitable as such a material is a polysilicon film, and besides, a film containing Ti such as a Ti film or a TiN film, a film containing tungsten, a film containing tungsten such as tungsten or tungsten silicide, a nitride film or an oxynitride film can be used. Can be.

Here, the thickness of the photoresist is required to form a fine pattern in the photolithography process of the highly integrated semiconductor device using the ArF exposure technique, and the target to be etched due to the high integration is gradually increased. Therefore, the resolution can be improved as the thickness of the photoresist decreases, but since the characteristics as the etching mask are weakened, it is used to compensate for this.                     

Subsequently, when the exposure for forming the pattern is performed on the hard mask sacrificial layer 17, the light reflectivity of the lower portion, that is, the hard mask sacrificial layer 17 is increased, thereby preventing unwanted reflections from being formed and forming a hard pattern. An antireflection film ARC is formed for the purpose of improving adhesion between the mask sacrificial film 17 and the subsequent ArF photoresist.

Here, it is preferable that the antireflection film (not shown) uses an organic material similar to the photoresist and its etching characteristics.

Next, a contact plug is formed to electrically connect the substrate 10 between the gate electrode pattern G, specifically, an impurity bonding layer such as a source / drain on the surface of the substrate 10 and an element to be formed thereon by a subsequent process. For this purpose, a photoresist pattern 18, which is a photoresist pattern that is a cell contact open mask, is formed.

Hereinafter, a detailed process of forming the photoresist pattern 18 will be described.

F ₂ exposure distance or ArF coated with a photoresist of the exposure distance to an appropriate thickness by a method such as spin coating, and then, F ₂ exposure light source or the ArF define the contact hole width is formed through an exposure light source and the SAC etching on top of the anti-reflective film A predetermined portion of the photoresist is selectively exposed using a predetermined reticle (not shown), and the portion exposed or not exposed by the exposure process is left through a developing process, and then a post-cleaning process is performed. The photoresist pattern 18 is formed by removing the etching residues.

Subsequently, the antireflective layer is etched through a selective etching process using the photoresist pattern 18 as an etching mask. At this time, in order to minimize the loss of the photoresist pattern 18, Cl ₂ , BCl ₃ , CCl ₄ or Etching process using plasma using chlorine-based gas such as HCl, or when using CF-based gas, gas with low C / F ratio, such as CF ₄ , C ₂ F ₂ , CHF ₃ and CH ₂ F ₂ The etching process is performed using a plasma using any one gas selected from the group consisting of.

This is because the CD should be easily controlled during the anti-reflection film etching, so that the etching may be performed under conditions that hardly generate polymer.

Subsequently, the sacrificial hard mask 17 ′ is formed by etching the hard mask sacrificial film 17 using the photoresist pattern 18 and the anti-reflection film as an etching mask.

Hereinafter, the etching process of the sacrificial film 17 for hard masks will be described in detail.

When the hard mask sacrificial film 17 includes tungsten (W) such as a W film, a WSix film, or a WN film, a plasma using a mixed gas of SF ₆ / N ₂ is used, in which case SF ₆ / N ₂ It is preferable to use those whose mixing ratio is 0.10 to 0.60.

When the hard mask sacrificial film 17 is a thin film containing titanium (Ti), such as a polysilicon film or a Ti film, a TiN film, a TiSix film, a TiAlN film or a TiSiN film, chlorine-based gas, in particular, Cl ₂ Each gas is used, and oxygen (O ₂ ) or CF gas is added to control the etching profile.

When the hard mask sacrificial film 17 is a nitride film series, a CF series gas is used.

Subsequently, at least the photoresist pattern 18 and the anti-reflection film are mostly removed during the etching process, but a part thereof may remain, so that a separate photoresist strip process for removing the photoresist pattern 18 and the anti-reflection film may be performed. If not performed, the remaining photoresist pattern 18 and the anti-reflection film layer may serve as an etching mask, and thus, the SAC process may be performed by etching the insulating film 16 using the sacrificial hard mask 17 'as an etching mask. Proceed.

In this case, when the etching process is performed at a point where the hard mask 14 of the gate electrode pattern G is almost exposed, the first etch stop layer 15 is partially etched, as shown in FIG. 1B. The etch rate of the oxide insulating layer 16 between the gate electrode patterns G is higher than that of the first etch stop layer 15 of the nitride layer, since the etch rate of the CF gas used in the SAC etching is higher. 14) It is etched to the bottom.

Subsequently, a photoresist strip process is performed to remove the remaining photoresist pattern 18 and the anti-reflection film.

Since the photoresist strip process mainly uses O ₂ gas, it is advantageous in terms of process simplification to use an organic anti-reflection film in order to remove the anti-reflection film in this process.

Chemicals such as HF or BOE (Buffered Oxide Etchant) are used to extend the openings of the contact regions, and the polymer 20 generated during SAC etching is removed.

BOE is used as a dilute solution of 100: 1 to 300: 1, and the washing process is preferably performed for 5 seconds to 100 seconds.                     

Reference numeral 19 denotes a part of the insulating film 16 removed when the opening is expanded.

Next, as shown in FIG. 1C, the second etch stop layer 21 is deposited along the profile in which the insulating layer 16 is etched to the upper portion of the hard mask 14 and the opening is extended by the SAC process.

FIG. 1C illustrates a process cross section in which the second etch stop layer 21 is formed, and the second etch stop layer 21 may be formed of a nitride oxide series such as a silicon oxide layer or a silicon oxynitride layer in consideration of an etching selectivity with respect to the oxide layer. In this case, a deposition method such as physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD) may be used. By depositing the second etch stop layer 21, as shown by reference numeral 22, an over-hang structure may be provided at a portion where the etch loss is greatest during the etching process.

Subsequently, the SAC process is performed to form contact holes 23 exposing the surface of the substrate 10 between the gate electrode patterns G. FIG. 1D shows a process cross section in which the contact hole 23 is formed.

Specifically, the second etching stop layer 21, the insulating layer 16, and the first etching stop layer 15 are etched by performing the entire surface etching using the CF-based gas as the stock angular gas to form a substrate between the gate electrode patterns G. Let (10) be exposed. In this case, even when the entire surface is etched, the second etch stop layer 21 is thickly deposited on the gate electrode pattern G, so that the loss of the hard mask 14 may be prevented.                     

In FIG. 1D, a portion of the second etch stop layer 21 ′ remains on the gate electrode pattern G. Referring to FIG.

According to the present invention as described above, by applying a hard mask sacrificial film 17 such as a polysilicon film under the ArF photoresist pattern, the weak etching resistance of the ArF photoresist pattern can be overcome during subsequent SAC etching. .
In addition, the present invention, after the first etching stop on the top of the hard mask during the SAC process using a photolithography process such as ArF, widening the opening through the cleaning process, and then using the etch stop layer in a deposition method of poor step coverage After thin deposition, the remaining SAC etching process is performed. Accordingly, the present invention has been found to prevent the attack of the gate electrode pattern according to the SAC etching to which the ArF photolithography process is applied, and to prevent the inclination in the etching profile to maximize the contact opening.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent the reduction of the inclination profile and the opening during the self-aligned contact etching process using an ArF or F ₂ exposure source, and ultimately, the excellent effect of improving the yield of semiconductor elements can be expected. .

Claims (6)

Forming a plurality of neighboring conductive patterns on the substrate; Depositing an insulating film on the conductive pattern; Forming a polysilicon film for a hard mask on the insulating film; Forming a photoresist pattern using an ArF exposure source to form contact holes between the conductive patterns on the hardmask polysilicon layer; Etching the polysilicon layer for hard mask using the photoresist pattern as an etch mask to form a sacrificial hard mask; Defining the contact hole forming region by etching a portion of the insulating layer under an etching condition in which an upper portion of the conductive pattern is exposed using the sacrificial hard mask as an etching mask; Removing the photoresist pattern; Cleaning to expand the opening of the defined contact hole; Forming an etch stop layer along the profile of the cleaned entire structure; Forming a contact hole exposing the substrate between the conductive patterns by removing the etch stop layer and the insulating layer through surface etching; Self-aligning contact hole formation method of a semiconductor device using an ArF exposure source comprising a. The method of claim 1, The etch stop layer is a nitride film-based self-aligned contact hole forming method of a semiconductor device using an ArF exposure source. The method of claim 1, In the forming of the etch stop layer, a method for forming a self-aligned contact hole of a semiconductor device using an ArF exposure source, characterized in that using the plasma chemical vapor deposition method or physical vapor deposition method. The method of claim 1, The insulating film is a method of forming a self-aligned contact hole of a semiconductor device using an ArF exposure source, characterized in that the oxide film series. The method of claim 4, wherein In the cleaning step, a method of forming a self-aligned contact hole of a semiconductor device using an ArF exposure source, characterized in that performed for 5 seconds to 100 seconds using HF or BOE. The method of claim 1, And the conductive pattern is a gate electrode pattern.

Images