KR20040082873A - METHOD FOR FABRICATION OF CONTACT HOLE OF SEMICONDUCTOR DEVICE USING ArF PHOTO LITHOGRAPHY - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device by an ArF photolithography process is provided to improve yield of the semiconductor device, by preventing the upper part of a contact hole from being broadened, by avoiding a reduction of the area of the bottom of a contact and by minimizing a variation of a pattern and a loss of a lower structure in using an ArF exposure technology. CONSTITUTION: An insulation layer and an ARC(anti-reflective coating) are sequentially formed on a conductive layer. A photolithography process using an ArF exposure source is performed on the ARC to form a photoresist pattern. The ARC and the insulation layer are partially etched to define a pattern formation region by using the photoresist pattern as an etch mask and using Ar/CF4 plasma. The remaining insulation layer is etched to form a contact hole exposing the conductive layer by using plasma including Ar/CH2F2. The polymer generated in etching the ARC and the insulation layer is eliminated by using plasma including Ar/O2 without destroying vacuum.

Description

A method for forming a contact hole in a semiconductor device using an argon fluoride photolithography process {METHOD FOR FABRICATION OF CONTACT HOLE OF SEMICONDUCTOR DEVICE USING ArF PHOTO LITHOGRAPHY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, argon fluoride (hereinafter referred to as ArF), which prevents widening of the upper part of the contact hole and reduction of the area of the bottom of the contact, and improves the process margin for misalignment during contact formation. And a method for forming a bit line contact hole in a semiconductor device using an exposure source.

In general, a semiconductor device includes a plurality of semiconductor devices therein. As semiconductor devices become highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of semiconductor devices, for example, transistors and capacitors. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of the semiconductor devices formed inside the cell is gradually decreasing. In fact, the minimum line width of the recent semiconductor DRAM device is formed to 0.115㎛ or less. Therefore, many difficulties have arisen in the manufacturing process of the semiconductor devices forming the cell.

For example, the alignment margin between the bit line contact hole and the bit line is further insufficient so that the bit line contact hole does not completely overlap the bit line when the bit line is etched, thereby exposing a part of the bit line contact hole.

1 is a plan view schematically illustrating a conductive film pattern including a word line and a bit line.

Referring to FIG. 1, a plurality of gate electrodes, for example, word lines (W / L) are disposed in one direction, and a plurality of bit lines (B / L) are disposed in a direction crossing the word lines (W / L). have. The bit line B / L is connected to an active region (not shown) of the substrate through a landing plug contact (LPC) process and a bit line contact (BLC) formed thereon. The contact pads are additionally used (some contact pads are used between the LPC and the BLC depending on the process), and storage node contacts (SNCs) are formed at the same time for the formation of subsequent capacitors during the LPC process.

On the other hand, for example, in 4G DRAM, the size of the bit line B / L is about 10% to 30% smaller than the bit line contact hole in the mask layout. As a result, when misalignment occurs during the contact mask, the lower metal layer used as the barrier film is lost in the bit line etching step due to the limitation of the resolution, and the surface of the polysilicon layer under the barrier film is damaged, resulting in contact resistance. Defects occur so that the semiconductor device does not operate normally.

Hereinafter, a brief description will be given of a conventional process of forming a contact hole for forming a bit line (B / L) contact plug.

2A and 2B are cross-sectional views illustrating a bit line contact hole forming process of a semiconductor device according to the prior art.

2A shows a cross section in which a photoresist pattern 29 for forming a bit line contact pad is formed.

Looking at the formation process in detail, a field oxide film (not shown) is formed on the substrate 20 on which various elements for forming a semiconductor device are formed through a LOCOS or STI process to distinguish an active region and a device isolation region.

A plurality of conductive film patterns adjacent to the active region, for example, a gate electrode pattern, are formed to deposit an oxide-based gate insulating film 22, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, a tungsten silicide, and the like thereon. The metal silicide, polysilicon, or the like is deposited alone or in combination to deposit the gate conductive film 23, and then a nitride film-based hard mask insulating film is deposited.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then a hard mask insulating film 24, a gate conductive film 23, and a gate insulating film 22 are selectively formed using the gate electrode pattern as an etching mask. By etching, a gate electrode pattern forming a stack structure of the gate insulating film 22 / gate conductive film 23 / hard mask insulating film 24 is formed.

The hard mask insulating film 24 preferably uses a nitride film series such as a silicon nitride film or a silicon oxynitride film.

Subsequently, a thin nitride stop film 25a is deposited along the entire profile of the gate electrode pattern. The reason for using the nitride film-based material as the material of the etch stop film 25a is to obtain an etch selectivity with an oxide film, which is an interlayer insulating film, in the SAC etching process for the subsequent plug formation, and also the loss of etching of the gate electrode pattern. It is to prevent.

Here, a specific process of forming an impurity bonding layer 21 such as a source / drain through an ion implantation process using an ion implantation mask (not shown) between the gate electrode patterns is omitted.

Subsequently, an oxide-based first insulating film 26 such as a BPSG film is formed to sufficiently cover the gate electrode pattern and the upper portion of the substrate 20.

Here, the first insulating layer 26 may include, for example, a phospho-silicate glass (PSG) film or a boro-silicate glass (BSG) film, in addition to the above-described BPSG film. The process is involved.

Next, the cell contact is opened to form a contact plug for electrically connecting the substrate 20 between the gate electrode patterns, specifically, the impurity bonding layer 21 on the surface of the substrate 20 and the device to be formed thereon by a subsequent process. After forming a mask (not shown), a contact hole for opening the impurity bonding layer 21 between the gate electrode patterns by selectively etching the first insulating layer 26 using the cell contact open mask as an etch mask (not shown) ).

By the SAC etching process, the etch stop layer 25a has an inclined profile in the region that is etched and opened, and remains on the sidewall of the gate electrode pattern in the form of a spacer 25b.

Subsequently, a conductive material such as polysilicon or tungsten (W) is deposited to contact the open and exposed impurity bonding layer 21 to sufficiently fill the contact hole, and then a planarization process such as CMP is performed.

On the other hand, when etching the above-described first insulating film 26, fluorine-based plasma, such as C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F ₈ or C used in a normal SAC process CxFy (x, y is 1 to 10) such as ₅ F _{10 is used} as a stock angle gas, and a gas for generating polymer during SAC process, that is, a gas such as CH ₂ F ₂ , C ₃ HF ₅ or CHF ₃ In this case, an inert gas such as He, Ne, Ar, or Xe is used as a carrier gas.

Here, the cell contact open mask may use a hole type, a bar type, a tee type, or the like.

Subsequently, a second insulating layer 28 is deposited on the entire surface where the plug 27 is formed, and then a photoresist pattern 29 for forming a bit line contact pad is formed on the second insulating layer 28.

Subsequently, the second insulating layer 28 is selectively etched using the photoresist pattern 29 as an etch mask to form an open portion 30 that exposes the plug 27, that is, a bit line contact hole.

On the other hand, as the integration degree of the semiconductor device increases, the critical dimension thereof decreases, and as the vertical arrangement of the device increases, the aspect ratio increases. As a result, the thickness of the second insulating layer 28 is increased.

The etching target increases when the open portion 30 is formed due to the increase in the thickness of the second insulating layer 28. As a result, the width W1 of the upper portion of the open portion 30 is relatively larger than the width W2 of the bottom surface. It becomes bigger.

The difference in width between the top and bottom of the open part 30 is caused by the inclined etching profile 31 due to the increase in the thickness of the second insulating layer 28.

The decrease in the width at the bottom of the open portion 30 eventually reduces the contact area between the bit line contact pads and the plug 27 to increase the contact resistance, which in turn increases the cell resistance and thus increases the performance and yield of the semiconductor device. Dropped.

Therefore, matters to be considered in the process of forming the aforementioned open portion, for example, the bit line contact hole, are as follows.

One). Pattern widening at the top of the bitline contact holes should be prevented during SAC etching.

This is because when the critical dimension (hereinafter referred to as CD) in the upper portion of the contact hole is widened, the inclination shape of the etching profile is increased.

2). In order to prevent an increase in contact resistance, a sufficient amount of CD on the bottom of the contact should be secured.

3). Even if some misalignment occurs when forming the photoresist pattern for forming the bit line contact, a SAC fail after the SAC etching process should not occur. In other words, a certain process margin must be secured.

In addition, since the microfabrication technology that has supported the progress of semiconductor devices is a photolithography technology, it is no exaggeration to say that the improvement in resolution of the technology is directly connected to the future of high integration of semiconductor devices.

As is well known, the photolithography process includes a process of forming a photoresist pattern and a process of etching a layer to be etched through an etching process using the photoresist pattern as an etch mask to form a pattern having a desired shape such as a contact hole. Wherein the photoresist pattern includes a process of applying a photoresist on the etched layer, a process of exposing the photoresist using a prepared exposure mask, and a portion of the photoresist exposed or not exposed with a predetermined chemical solution; Through the development process.

On the other hand, the critical dimension of the pattern that can be implemented by the photolithography process (hereinafter referred to as CD) depends on the wavelength of the light source used in the above exposure process. This is because the CD of the actual pattern is determined by the width of the photoresist pattern that can be realized through the exposure process.

The wavelength of the light source used in the initial stepper adopting the “step and repeat” exposure method is from 436 nm (g-line) to 365 nm (i-line) and is now 248 nm (KrF Excimer Laser) wavelength. It mainly uses stepper or scanner type exposure equipment using DUV (Deep Ultra-violet). The 248 nm DUV photolithography initially produced a number of problems, such as time delay effects and substrate dependence. However, in order to develop a product having a design of 0.15 μm or less, it is necessary to develop a technology with a new DUV photolithography technique having a wavelength of 193 nm (ArF Excimer Laser). However, even if a combination of various techniques for enhancing the resolution in the DUV photolithography technique is impossible to pattern less than 0.1㎛, the development of a photolithography technique having a new light source is actively progressing.

Currently, an equipment using an ArF laser (λ = 193 nm) as a light source is being developed for a pattern up to 0.11 μm. DUV photolithography is superior in terms of performance and resolution compared to i-rays, but process control is not easy. These problems can be divided into optical causes due to short wavelengths and chemical causes due to the use of chemically amplified resists. If the wavelength is shortened, the CD shake phenomenon due to the stationary wave effect and the reflection of reflected light due to the substrate phase become worse. CD oscillation refers to a phenomenon in which the line thickness changes periodically as the degree of interference between incident light and reflected light changes depending on the slight thickness difference of the resist or the thickness difference of the substrate film. In the DUV process, a chemically amplified photoresist has to be used to improve sensitivity, and problems related to the reaction mechanism include PED (Post Exposure Delay) stability and substrate dependence. Development of a photoresist for ArF. ArF is a chemically amplified type such as KrF, but the material needs to be fundamentally improved. ArF photoresist material development is difficult because benzene rings cannot be used. Benzene rings have been used in photoresists for i-rays and KrF to ensure dry etching resistance. However, when the benzene ring is used in the ArF photoresist, since the absorbance is large at 193 nm, which is the wavelength region of the ArF laser, the transparency is poor and the exposure to the lower portion of the photoresist is impossible. For this reason, the research of the material which can ensure dry etching resistance, does not have a benzene ring, and has good adhesive force and can develop in 2.38% TMAH is progressing. To date, many companies and research institutes in the world have announced their research results, and the commercially available ones are in the form of polymers of COMA (CycloOlefin-Maleic Anhydride) or Acrylate system, or a mixture thereof. However, the photoresist has the benzene structure as described above.

Therefore, when the etching process is performed to form a line pattern such as a gate electrode or a bit line through photolithography using an ArF exposure source, a stripe-shaped pattern may occur, or photoresist may aggregate during etching. (Cluster) Plastic deformation and weakness of the photoresist during etching cause it to drift to one side. This is mainly a fluorine-based gas, which is an etching gas for hard masks used to prevent etching loss of line patterns. This is because it reacts with the ArF photoresist such as acrylate and the like, and causes deformation of the photoresist itself.

Therefore, it is an urgent task to compensate for the weak durability of the ArF photoresist and the weak physical properties of the fluorine-based gas.

3 is a cross-sectional SEM photograph showing the loss of a word line hard mask when forming a bit line contact.

Referring to FIG. 3, it can be seen that a loss of a word line hard mask occurs as shown in an 'L' in an etching process for forming a bit line contact (BLC) using an ArF exposure source.

Therefore, in forming the bit line contact hole of the semiconductor device using the ArF exposure source, in addition to the three conditions described above, the weak etching resistance of the photoresist for ArF can be compensated, that is, the fourth pattern which can prevent pattern deformation in the etching process. The condition will be added.

The present invention has been proposed to solve the above problems of the prior art, it is possible to prevent the widening of the upper contact hole and the reduction of the area of the bottom of the contact, to prevent the loss of the word line hard mask, and to the etching process It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device using an ArF exposure source capable of preventing pattern deformation.

1 is a plan view schematically showing a conductive film pattern including a word line and a bit line.

2A and 2B are cross-sectional views illustrating a bit line contact hole forming process of a semiconductor device according to the prior art.

Figure 3 is a cross-sectional SEM photograph showing the loss of the word line hard mask when forming the bit line contacts.

4A through 4E are cross-sectional views illustrating a process of forming a bit line contact hole in a semiconductor device using an ArF exposure source according to an embodiment of the present invention.

5 is a plan view of an SEM including the bitline contact holes formed by the process of the present invention described above.

6 is a cross-sectional SEM photograph of a bit line metal film deposited on the bit line contact hole of FIG. 5.

Explanation of symbols on the main parts of the drawings

40 substrate 41 impurity bonding layer

42: gate insulating film 43: gate conductive film

44: hard mask insulating film 45a: etching stop film

45b: spacer 46: first insulating film

47: plug 48: second insulating film

53: bit line contact hole

In order to achieve the above object, the present invention comprises the steps of sequentially forming an insulating film and an organic antireflection film on the conductive layer; Forming a photoresist pattern on the anti-reflection film by performing a photolithography process using an ArF exposure source; Etching a portion of the anti-reflection film and the insulating layer using an Ar / CF ₄ plasma as an etch mask to define a pattern formation region; Etching the remaining insulating film using a plasma including Ar / CH ₂ F ₂ to form a contact hole exposing the conductive layer; And removing a polymer component generated in the anti-reflection film and the insulating film etching step by using a plasma including Ar / O ₂ without vacuum destruction.

The present invention is carried out in three steps by etching the anti-reflection film and the oxide-based interlayer insulating film during the formation of a contact hole (for example, a bit line contact hole) during the manufacturing process of a highly integrated semiconductor device using an ArF exposure source.

That is, in the first step, by using Ar / CF ₄ plasma, 2/5 to 4/5 of the anti-reflection film and the insulating film (the minimum thickness of the insulating film deposited on the upper end of the word line hard mask as an etching target) are etched. Minimize the loss of upper CD and deformation of ArF photoresist pattern by using O ₂ in anti-reflective film etching. At this time, since it was confirmed in the experimental results for the present invention that the effect of the pattern damage is the greatest among the variables affecting the plasma etching process, the object of the present invention is achieved through the etching process conditions excluding the use of O ₂ gas. This is possible.

In the second step, the remaining conductive layer is removed by using Ar / CH ₂ F ₂ / C ₄ F ₆ (C ₄ F ₈ , C ₅ F ₈ ) plasma to expose the lower conductive layer (plug), and then in the third step In the process, the Ar / O ₂ plasma is used to remove the polymer component generated during the etching process without vacuum breaking.

Accordingly, in the bit line contact hole forming process of the semiconductor device using the ArF exposure source, it is possible to prevent the widening of the upper portion of the contact hole and the reduction of the area of the contact bottom, and to prevent the loss of the word line hard mask. In addition, the deformation of the ArF photoresist pattern according to the etching process can be prevented.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4A to 4E are cross-sectional views illustrating a bit line contact hole forming process of a semiconductor device using an ArF exposure source according to an embodiment of the present invention.

4A shows a cross section in which a plug 47 in contact with the impurity bonding layer 41 of the substrate 40 is formed.

Referring to the cross-sectional forming process of FIG. 4A, a field oxide film (not shown) is formed on the substrate 40 on which various elements for forming a semiconductor device are formed through a LOCOS or STI process to separate active and device isolation regions. do.

A plurality of conductive film patterns adjacent to the active region, for example, a gate electrode pattern, are formed to deposit an oxide-based gate insulating film 42, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, a tungsten silicide, and the like thereon. The metal silicide, polysilicon, or the like is deposited alone or in combination to deposit the gate conductive film 43, and then a nitride-based hard mask insulating film 44 is deposited.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then the gate electrode pattern is selectively etched using the hard mask insulating film, the gate conductive film 43 and the gate insulating film 42 as an etch mask. A gate electrode pattern forming a stack (lamination) structure of the insulating film 42 / gate conductive film 43 / hard mask insulating film 44 is formed.

As the hard mask insulating film 44, it is preferable to use a nitride film series such as a silicon nitride film or a silicon oxynitride film having an etching selectivity with respect to the oxide film.

Subsequently, a thin nitride stop layer 45a is deposited along the entire profile of the gate electrode pattern. The reason for using the nitride film-based material as the material of the etch stop film 45a is that the etching selectivity with the oxide film mainly used as the insulating film for interlayer insulation during the SAC etching process for the subsequent plug formation can be obtained, and the gate This is to prevent the etching loss of the electrode pattern.

Here, a specific process of forming an impurity bonding layer 41 such as a source / drain through an ion implantation process using an ion implantation mask (not shown) between the gate electrode patterns is omitted.

Subsequently, an oxide-based first insulating layer 46 is formed to sufficiently cover the gate electrode pattern and the upper portion of the substrate 40 and for interlayer insulation.

The first insulating layer 46 may include, for example, a BOSG (Boro Phospho Silicate Glass) film, a PSG (Phospho Silicate Glass) film, or a BSG (Boro Silicate Glass) film. The process of heat-processing and flow is accompanied.

In addition, an HDP (High Density Plasma) oxide film, a Tetra Ethyl Ortho Silicate (TEOS) film, or an Advanced Planarization Layer (APL) film may be used as the first insulating film 46.

Next, the cell contact is opened to form a contact plug for electrically connecting the substrate 40 between the gate electrode patterns, specifically, the impurity bonding layer 41 on the surface of the substrate 40 and an element to be formed thereon by a subsequent process. After forming a photoresist pattern (not shown) that is a mask, a contact hole for selectively opening the impurity bonding layer 41 between the gate electrode patterns by selectively etching the first insulating layer 46 using the photoresist pattern as an etching mask ( Not shown).

By the SAC etching process, the etch stop layer 45a has an inclined profile in the contact hole 48 forming region where the first insulating layer 46 is etched and opened, and the gate electrode pattern is formed in the form of a spacer 45b. Remains on the sidewalls.

When etching the above-described first insulating film 46, a fluorine-based plasma used in a conventional SAC process, for example, C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F ₈ or C ₅ F _10, etc., and a CxFy (x, y is 1 to 10), the respective gas stock, gas for generating a SAC process during polymer herein i.e., CH ₂ F _2, the addition of gas, such as C ₃ HF _5, or CHF ₃ In this case, an inert gas such as He, Ne, Ar, or Xe is used as a carrier gas.

Here, the cell contact open mask may have various forms such as hole-type, bar-type, or tee-type.

Subsequently, a photoresist strip process is performed to remove the photoresist pattern. Meanwhile, an organic anti-reflection film (Organic ARC) is used between the photoresist pattern and the first insulating layer 46 to prevent diffuse reflection, but the drawings are omitted for simplicity.

Subsequently, a conductive material film is formed by depositing a conductive material such as polysilicon or tungsten (W) so as to contact the open and exposed impurity bonding layer 41 and sufficiently fill the contact hole.

Subsequently, a planarization process such as CMP or full surface etching is performed to remove the conductive material layer to be planarized to form a plurality of isolated plugs 47.

At this time, the first insulating film 46 is removed so that the hard mask insulating film 44 is exposed, and the plug 47 allows the hard mask insulating film 44 and the first insulating film 46 to have substantially the same height.

Subsequently, as shown in FIG. 4B, the second insulating film 48 is deposited on the entire surface where the plug 47 is formed.

The second insulating film 48 uses a BPSG film, an HTO film, an MTO film, an HDP oxide film, a TEOS film, or an APL film.

To prevent diffuse reflection during exposure and to improve adhesion to the photoresist, an antireflection film 49 is coated on the second insulating film 48, and then a photoresist pattern for forming bit line contact holes on the antireflection film 49 ( 50).

Specifically, an ArF photoresist is applied on the antireflection film 49 to a predetermined thickness, and then a predetermined reticle (not shown) for defining an ArF exposure source (not shown) and the width of the contact hole pattern are shown. Selectively exposing a predetermined portion of the photoresist by using, to leave the exposed or unexposed portion through the exposure process through the development process, and then remove the etching residues through a post-cleaning process, etc. 50).

Here, the anti-reflection film 49 uses an organic series, the photoresist for ArF includes the aforementioned COMA or acrylate form, and the photoresist pattern 50 may have various shapes such as circular, bar or tee. Do.

Next, as shown in FIG. 4C, the anti-reflection film 49 is etched using the photoresist pattern 50 as an etch mask to define a pattern region for forming a bit line contact hole as shown by reference numeral '51'.

Subsequently, as shown in FIG. 4D, the oxide-based second insulating film 48 is etched to etch 2/5 to 4/5 of the second insulating film 48 as indicated by reference numeral 52.

The etching condition of 2/5 to 4/5 of the second insulating film 48 is to etch the second insulating film 48 deposited at the upper end of the hard mask insulating film 44 of the gate electrode, which is the minimum deposition thickness of the second insulating film 48. This is possible when targeting.

The etching process of the anti-reflection film 49 and the second insulating film 48 of FIGS. 4C and 4D is performed continuously, and a plasma including CF ₄ / Ar gas is used.

Therefore, the loss of the anti-radiation film 49 and the photoresist pattern 50 due to O ₂ can be minimized by eliminating the use of O ₂ used in conventional organic anti-reflection film etching. You can get it.

In addition, the pressure of the chamber is maintained at 20 mTorr to 60 mTorr so that the polymer hardly occurs, and at this time, the power of 1200 W to 1800 W can be used to prevent the reduction of the CD at the upper end of the contact scheduled region 52.

At this time, Ar is preferably 100SCCM to 500SCCM, and CF ₄ is preferably 50SCCM to 150SCCM.

Subsequently, the remaining second insulating layer 48 is removed using a combination of etching gases that generate a polymer to minimize the loss of the hard mask insulating layer 44, and then the polymer component generated in the etching process of the second insulating layer 48 is removed. An etching process using a plasma containing O ₂ for removal is performed.

Specifically, the combination of etching gas to remove the second insulating film remaining 48 Ar / C _4, and _{F 8 / CH 2 F 2,} C 4 F 8 in addition to use the C ₄ F ₆ or C ₅ F _8, and At this time, the pressure of the chamber is maintained at 20 mTorr to 60 mTorr, and a power of 1200 W to 1800 W is used.

Ar is preferably 100SCCM to 500SCCM, C ₄ F ₈ is preferably 10SCCM to 20SCCM, and CH ₂ F ₂ is preferably 2SCCM to 10SCCM.

In the etching process for removing the polymer, it is preferable to maintain the pressure of the chamber at 20 mTorr to 60 mTorr, use a power of 100 W to 500 W, Ar to 50 SCCM to 200 SCCM, and O ₂ to 100 SCCM to 300 SCCM, respectively.

Subsequently, the photoresist strip process and the cleaning process are performed. As shown in FIG. 4E, the process of forming the bit line contact hole 53 exposing the surface of the plug 47 is completed.

On the other hand, since the O ₂ plasma is used in the process of removing the polymer described above, by controlling the etching process time, the photoresist pattern 50 and the anti-reflection film 49 can be removed at this time, so that a separate photoresist strip process is performed. Can be omitted.

FIG. 5 is a SEM plan view including a bit line contact hole formed by the above-described process of the present invention, and FIG. 6 is a cross-sectional SEM photograph of a bit line metal film deposited on the bit line contact hole of FIG. 5.

Referring to FIG. 5, it can be seen that the deformation of the CD of the bit line contact hole hardly occurs (pattern deformation), and the phenomenon of CD widening at the upper end of the contact hole and reduction of CD at the bottom of the contact hole are minimized. .

Referring to FIG. 6, the diffusion preventing metal film 54 and the bit line metal film 55 are stacked on the entire surface where the bit line contact hole 53 is formed, and the 'X' is shown in the process of forming the bit line contact 530. It can be seen that almost no loss of gate hard mask occurs.

According to the present invention, the etching process is performed in three steps by etching the oxide-based second insulating layer when forming the bit line contact hole of the semiconductor device, thereby preventing the change of the CD in the upper and lower portions of the contact hole and modifying the pattern. By minimizing the loss and at the same time to prevent the loss of the gate hard mask has been found through the embodiment.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the present invention can be applied not only to the bit line contact hole forming process described in the above-described embodiment of the present invention but also to the via hole forming process for forming the storage node contact hole or the metal wiring.

As described above, the present invention can prevent the widening of the upper portion of the contact hole and the reduction of the area of the bottom of the contact, and in particular, the ArF exposure technique can minimize the deformation of the pattern and the loss of the underlying structure, thereby ultimately the semiconductor. Excellent effect can be expected to improve the yield of the device.

Claims (9)

Sequentially forming an insulating film and an organic antireflection film on the conductive layer; Forming a photoresist pattern on the anti-reflection film by performing a photolithography process using an ArF exposure source; Etching a portion of the anti-reflection film and the insulating film using an Ar / CF ₄ plasma as an etching mask to define a pattern formation region; Etching the remaining insulating film using a plasma including Ar / CH ₂ F ₂ to form a contact hole exposing the conductive layer; And Removing the polymer component generated in the anti-reflection film and the insulating film etching step by using a plasma containing Ar / O ₂ without vacuum destruction Contact hole formation method of a semiconductor device using an ArF exposure source comprising a. The method of claim 1, In defining the pattern forming region, Contact of the semiconductor device using an ArF exposure source, characterized in that the Ar gas is used 100SCCM to 500 SCCM, the CF ₄ gas 50SCCM to 150SCCM, the chamber pressure is maintained at 20mTorr to 60mTorr and using a power of 1200W to 1800W How to form a hole. The method of claim 1, In the forming of the contact hole, A method for forming a contact hole in a semiconductor device using an ArF exposure source, further comprising any one of C ₄ F ₆ , C ₄ F _8, or C ₅ F ₈ gas in addition to the Ar and CH ₂ F ₂ gases. The method of claim 3, wherein 100SCCM to 500 SCCM for the Ar gas, 2SCCM to 10SCCM for the CH ₂ F ₂ gas, 20CCM to 20SCCM for the gas of any one of the C ₄ F ₆ , C ₄ F ₈ or C ₅ F ₈ gas, and the chamber pressure The method for forming a contact hole in a semiconductor device using an ArF exposure source, characterized by using a power of 1200W to 1800W while maintaining 20mTorr to 60mTorr. The method of claim 1, In the step of removing the polymer component, Contacting a semiconductor device using an ArF exposure source, wherein the Ar gas is used at 50 SCCM to 200 SCCM, and the O ₂ gas is used at 100 SCCM to 300 SCCM, the chamber pressure is maintained at 20 mTorr to 60 mTorr, and 100 W to 500 W of power is used. How to form a hole. The method according to any one of claims 1 to 5, The conductive layer is a contact hole forming method of a semiconductor device using an ArF exposure source, characterized in that the plug is in contact with the substrate between the gate electrode. The method of claim 6, wherein And forming the contact hole as a bit line contact hole. The method of claim 1, Removing the polymer component, and simultaneously removing the photoresist pattern and the anti-reflective film. The method of claim 1, And removing the photoresist pattern and the anti-reflective film after the removing of the polymer component.