CN108597982A - Wafer processing method - Google Patents
Wafer processing method Download PDFInfo
- Publication number
- CN108597982A CN108597982A CN201810029245.5A CN201810029245A CN108597982A CN 108597982 A CN108597982 A CN 108597982A CN 201810029245 A CN201810029245 A CN 201810029245A CN 108597982 A CN108597982 A CN 108597982A
- Authority
- CN
- China
- Prior art keywords
- etching
- processing method
- wafer
- groove
- wafer processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000004140 cleaning Methods 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 47
- 238000002161 passivation Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000012360 testing method Methods 0.000 claims description 6
- 239000000523 sample Substances 0.000 claims description 5
- 229910018503 SF6 Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 3
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 3
- 239000004341 Octafluorocyclobutane Substances 0.000 claims description 2
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 claims description 2
- 235000019407 octafluorocyclobutane Nutrition 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000000926 separation method Methods 0.000 abstract description 12
- 239000013618 particulate matter Substances 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
The present invention provides a kind of wafer processing method, and the wafer processing method includes;Sacrificial layer is formed in the front of pending wafer;First etching is carried out to the pending wafer after the formation sacrificial layer and forms first groove;Carry out cleaning procedure;Second etching is carried out to the pending wafer after first etching and forms second groove, second etching is deep silicon etching technique, slot bottom of the second groove in the first groove.In wafer processing method provided by the invention, the generation of particulate matter in follow-up second etching can be reduced by cleaning procedure, and make sacrificial layer consumption in the second etching process to expose chip;Simultaneously, each chip on wafer is split by the first groove formed by the first etching to come, the second groove formed in first groove by deep silicon etching technique again, realize that the separation of chip completes the separation of chip by the smaller groove of this method formation width on the basis of second groove, to improve the area utilization of wafer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of wafer processing methods.
Background technology
Semiconductor fabrication needs carry out a variety of different physics on semi-conductor silicon chip and chemical technology forms device
Then structure forms the wafer that can be cut into multiple individual chips (die).Multiple chips are split into conduct from wafer
More important technique in backend flow, usually can be used the mode of laser or blade cutting crystal wafer.
But in the prior art in the mode of cutting crystal wafer, need to reserve certain machining area, example for laser or blade
Such as, laser needs the width of reserved 40um or more that could complete to cut, and the blade of blade then needs the width of 50um or more
Cutting can be completed, to be unlikely to be damaged to chip and more smoothly realize separation.Since the size of wafer itself is opposite
Determining, wafer needs reserved machining area often to occupy many areas, to reduce utilization rate, makes in single-wafer
Therefore the quantity of chip is reduced.
Therefore, the problem of how providing a kind of wafer processing method to improve crystal round utilization ratio be those skilled in the art urgently
A technical problem to be solved.
Invention content
The purpose of the present invention is to provide a kind of wafer processing method, solve the problems, such as that the area utilization of wafer is not high.
To solve the above-mentioned problems, the present invention provides a kind of wafer processing method, and the wafer processing method includes：It is waiting for
The front for handling wafer forms sacrificial layer；First etching is carried out to the pending wafer after the formation sacrificial layer and forms the first ditch
Slot；Carry out cleaning procedure；Pending wafer progress second after first etching is etched and forms second groove, described second
Etching is deep silicon etching technique, slot bottom of the second groove in the first groove.
Optionally, in the wafer processing method, the material of the sacrificial layer is silica.
Optionally, in the wafer processing method, the thickness of the sacrificial layer is
Optionally, in the wafer processing method, first etching is that interlayer etches, and the interlayer etching includes carving
Lose the passivation layer and inter-level dielectric on the sacrificial layer and the pending wafer.
Optionally, in the wafer processing method, the width of the first groove is less than or equal to 10um, second ditch
The depth of slot is 130um~170um.
Optionally, in the wafer processing method, second etching includes being adopted as the octafluoro ring fourth of passivation gas
Alkane and sulfur hexafluoride for etching gas.
Optionally, in the wafer processing method, second etching includes：The sacrificial layer is removed.
Optionally, in the wafer processing method, the cleaning procedure includes photoresist ashing and wet-cleaning.
Optionally, in the wafer processing method, further include：Before forming the sacrificial layer, in pending wafer
Front be passivated a layer etching technics.
Optionally, in the wafer processing method, the material of the passivation layer is silicon nitride.
Optionally, in the wafer processing method, further include：After second etching, pending wafer is carried out
Probe test.
Optionally, in the wafer processing method, further include：After second etching, to the back of the body of pending wafer
Face is ground technique, and the grinding technics is ground to second groove.
In wafer processing method provided by the invention, it is formed with sacrificial layer in the front of pending wafer, passes through cleaner
Skill can reduce the generation of particulate matter in follow-up second etching, and can make sacrificial layer consumption in the second etching process to exposure
Go out chip；Meanwhile each chip on wafer being split by the first groove that the first etching is formed and is come, then carved by deep silicon
The second groove that etching technique is formed in first groove preferably realizes the separation of chip on the basis of second groove, due to
Etching technics, which can reach, occupies smaller width, compared with the prior art, by the smaller groove of this method formation width come complete
At the separation of chip, to improve the area utilization of wafer, and then production efficiency is improved.
Description of the drawings
Fig. 1 is the flow chart of the wafer processing method of the embodiment of the present invention；
Fig. 2-Fig. 4 be the embodiment of the present invention wafer processing method in pending wafer diagrammatic cross-section.
Specific implementation mode
In order to keep objects, features and advantages of the present invention more obvious and easy to understand, attached drawing is please referred to.It should be clear that this explanation
Structure, ratio, size etc. depicted in book institute accompanying drawings, only to coordinate the revealed content of specification, for being familiar with this
The personage of technology understands and reads, and is not limited to the enforceable qualifications of the present invention, therefore does not have technical essence meaning
Justice, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing the effect of present invention can be generated and institute
Under the purpose that can reach, should all still it fall in the range of disclosed technology contents obtain and can cover.
As shown in Figure 1, a kind of wafer processing method provided by the invention, the wafer processing method include：
Step S10, sacrificial layer is formed in the front of pending wafer；
Step S20, the first etching is carried out to the pending wafer after the formation sacrificial layer and forms first groove；
Step S30, cleaning procedure is carried out；
Step S40, the pending wafer progress second after first etching is etched and forms second groove, described second
Etching is deep silicon etching technique, slot bottom of the second groove in first flute.
Introduce each step in wafer processing method in more detail below in conjunction with the accompanying drawings.
First, as shown in Fig. 2, the front in pending wafer 10 forms sacrificial layer 20, sacrificial layer 20 can be at subsequent place
It being removed during reason, pending wafer 10 typically refers to formed the semi-finished product wafer of the chip (die) with standalone feature,
The wafer for separating each chip is needed, the front of pending wafer 10 refers to the one side far from substrate.It is understood that
The purpose of method is how to be split to pending wafer, and the i.e. pending wafer in the part being partitioned into is not wanted
It asks and limits, for convenience of illustrating, in the accompanying drawings only using two chips as example.
The material of selection for sacrificial layer 20, the sacrificial layer 20 is silica, and silica chemistry property is stablized, had
Certain protective effect can be formed in the front of pending wafer by modes such as chemical vapor depositions.
Optionally, the thickness of the sacrificial layer 20 isSacrificial layer 20 influences follow-up if too thick
Other processing steps, sacrificial layer 20 influence its effect if too thin, the purpose of the present invention may be implemented within this range.
Then, as shown in figure 3, carrying out the first etching to the pending wafer 10 after the formation sacrificial layer 20 forms first
Groove 30 comes to which each chip on pending wafer 10 to be split, i.e., keeps chip respectively independent by first groove 30
It comes.
In the present embodiment, first etching is that interlayer etches, interlayer etching include etch the sacrificial layer with
And passivation layer and inter-level dielectric on the pending wafer can be carved to preferably independently open chip separation by interlayer
Separating for inter-level dielectric, for example various K values conducting mediums of inter-level dielectric or the dielectric layer for playing the different roles such as isolation are realized in erosion, from
And the separation between convenient follow-up each chip.
In the present embodiment, the wafer processing method further includes：Before forming the sacrificial layer 20, in pending crystalline substance
The front of circle 10 is passivated a layer etching technics, and the hard contact (Pad) etc. of exposure can will be needed by passivation layer etching technics
Region is exposed, and meets subsequent technique needs.
Optionally, the material of the passivation layer 40 is silicon nitride, and silicon nitride physicochemical properties are stablized, can preferably be played
Protective effect can be formed in crystal column surface by modes such as chemical vapor depositions.
Then, as shown in figure 4, the pending wafer 10 after the first etching described to progress carries out the second etching and forms second
Groove 50, it is described second etching be deep silicon etching technique, can be performed etching on a silicon substrate by deep silicon etching technique to be formed compared with
Deep groove, the second groove 50 is the base in first groove 30 in the slot bottom of the first groove 30, i.e. second groove 50
The enterprising step of plinth carries out.
From size relationship, the width of the first groove 30 is less than or equal to 10um, when the width of first groove 30 is smaller,
The area that can then re-use is bigger, and the depth of the second groove 50 is 130um~170um, passes through the second of certain depth
Groove 50 can preferably realize that each chip is separated from wafer, cannot be preferably real when the depth of second groove 50 is too small
It now detaches and chip may be damaged in separation process, when the depth of second groove 50 is too big, increase complex process journey
Inconveniences, the above-mentioned depth such as degree can be achieved the object of the present invention preferably.
Optionally, second etching includes being adopted as the octafluorocyclobutane (C of passivation gas4F8) and be etching gas
Sulfur hexafluoride (SF6), it can be carried out by the alternate repetition of passivation gas and etching gas.Since etching technics easy tos produce particle
Object, in the present invention, cleaning treatment is carried out on the basis of forming sacrificial layer can be reduced in follow-up process since particulate matter generates.
In the present embodiment, second etching includes：The sacrificial layer is removed, it can be with core by the consumption of sacrificial layer
Piece is exposed, and can all dispose the residue on sacrificial layer.Certainly, in actual processing procedure, the major part of sacrificial layer
It is removed, remaining fraction will not have an impact, and it is preferably to select all to remove.In the present embodiment, the cleaning
Technique includes that optical cement ashing and wet-cleaning, wet-cleaning can be used containing hydrogen peroxide (H2O2), ammonium hydroxide (NH4) and sulphur OH
Acid (H2SO4) solution cleaned, the acid solution of hydrogen oxide and hydrogen chloride can also be used, or hydrogen oxide and hydrogen-oxygen can be used
The alkaline solution for changing ammonium, is applicable to the needs of different product, and the residue of the first etching generation can be removed in cleaning procedure
Deng making the edge of first groove not allow to be also easy to produce particulate matter.
For the ease of product test, the wafer processing method further includes：After second etching, to pending wafer
Probe test (CP, Chip Probe) is carried out, after completing the first etching and the second etching and after related process, is detached in chip
The good ring that electrical testing determines chip is carried out by probe test before.
In the present embodiment, the wafer processing method further includes：After second etching, to the back of the body of pending wafer
Face is ground technique, and the grinding technics is ground to second groove 50, so that each chip is realized separation, compared to existing technology
Laser and blade cutting mode are less prone to the problems such as chip damages in last chip separation process, improve production yield.
In wafer processing method provided by the invention, it is formed with sacrificial layer in the front of pending wafer, passes through cleaner
Skill can reduce the generation of particulate matter in follow-up second etching, and make sacrificial layer consumption in the second etching process to expose
Chip；Meanwhile each chip on wafer being split by the first groove that the first etching is formed and is come, then pass through deep silicon etching
The second groove that technique is formed in first groove preferably realizes the separation of chip on the basis of second groove, due to carving
Etching technique can reach occupies smaller width, compared with the prior art, etching technics can the smaller groove of formation width complete
The separation of chip to improve the area utilization of wafer, and then improves production efficiency.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (12)
1. a kind of wafer processing method, which is characterized in that the wafer processing method includes：
Sacrificial layer is formed in the front of pending wafer；
First etching is carried out to the pending wafer after the formation sacrificial layer and forms first groove；
Carry out cleaning procedure；
Second etching is carried out to the pending wafer after first etching and forms second groove, second etching is carved for deep silicon
Etching technique, slot bottom of the second groove in the first groove.
2. wafer processing method as described in claim 1, which is characterized in that the material of the sacrificial layer is silica.
3. wafer processing method as claimed in claim 2, which is characterized in that the thickness of the sacrificial layer is
4. wafer processing method as described in claim 1, which is characterized in that first etching is that interlayer etches, the layer
Between etching include etching the sacrificial layer and the pending wafer on passivation layer and inter-level dielectric.
5. the wafer processing method as described in any one of claim 1-4, which is characterized in that the width of the first groove
Less than or equal to 10um, the depth of the second groove is 130um~170um.
6. the wafer processing method as described in any one of claim 1-4, which is characterized in that second etching includes adopting
With for passivation gas octafluorocyclobutane and be etching gas sulfur hexafluoride.
7. the wafer processing method as described in any one of claim 1-4, which is characterized in that it is described second etching include：
The sacrificial layer is removed.
8. the wafer processing method as described in any one of claim 1-4, which is characterized in that the cleaning procedure includes light
Photoresist is ashed and wet-cleaning.
9. the wafer processing method as described in any one of claim 1-4, which is characterized in that the wafer processing method is also
Including：Before forming the sacrificial layer, a layer etching technics is passivated in the front of pending wafer.
10. wafer processing method as claimed in claim 8, which is characterized in that the material of the passivation layer is silicon nitride.
11. the wafer processing method as described in any one of claim 1-4, which is characterized in that the wafer processing method
Further include：After second etching, probe test is carried out to pending wafer.
12. the wafer processing method as described in any one of claim 1-4, which is characterized in that the wafer processing method
Further include：After second etching, technique is ground to the back side of pending wafer, the grinding technics is ground to second
Groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810029245.5A CN108597982A (en) | 2018-01-12 | 2018-01-12 | Wafer processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810029245.5A CN108597982A (en) | 2018-01-12 | 2018-01-12 | Wafer processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108597982A true CN108597982A (en) | 2018-09-28 |
Family
ID=63608196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810029245.5A Pending CN108597982A (en) | 2018-01-12 | 2018-01-12 | Wafer processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108597982A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785686A (en) * | 2019-04-03 | 2020-10-16 | 华邦电子股份有限公司 | Method and die for dicing wafers |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101197319A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Production method of self-aligning contact hole |
| CN101459180A (en) * | 2007-11-12 | 2009-06-17 | 英飞凌科技股份公司 | Wafer and a method of dicing a wafer |
| CN102403257A (en) * | 2010-09-14 | 2012-04-04 | 上海华虹Nec电子有限公司 | Method for Improving the Etched Boundary Morphology of Deep Trench of Super Junction Devices |
| CN104143522A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | A method for forming shallow grooves |
| CN104979187A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for dividing wafer |
-
2018
- 2018-01-12 CN CN201810029245.5A patent/CN108597982A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101197319A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Production method of self-aligning contact hole |
| CN101459180A (en) * | 2007-11-12 | 2009-06-17 | 英飞凌科技股份公司 | Wafer and a method of dicing a wafer |
| CN102403257A (en) * | 2010-09-14 | 2012-04-04 | 上海华虹Nec电子有限公司 | Method for Improving the Etched Boundary Morphology of Deep Trench of Super Junction Devices |
| CN104143522A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | A method for forming shallow grooves |
| CN104979187A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for dividing wafer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785686A (en) * | 2019-04-03 | 2020-10-16 | 华邦电子股份有限公司 | Method and die for dicing wafers |
| CN111785686B (en) * | 2019-04-03 | 2023-08-15 | 华邦电子股份有限公司 | Wafer cutting method and grain |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105359256B (en) | Laser Scribing and Plasma Etching for High Die Rupture Strength and Smooth Sidewalls | |
| TWI469211B (en) | Fabrication of a silicon structure and deep silicon etch with profile control | |
| KR100749735B1 (en) | Cantilever type probe manufacturing method and probe card manufacturing method using the same | |
| KR101615914B1 (en) | Reducing damage to low-k materials during photoresist stripping | |
| CN104347477B (en) | The forming method of semiconductor structure | |
| US11688639B2 (en) | Semiconductor device and method | |
| CN105826251A (en) | Cutting method | |
| CN113013155A (en) | Method and system for adjusting plasma cutting rate | |
| KR100686763B1 (en) | Focus ring, plasma etching apparatus and plasma etching method | |
| CN104143526B (en) | Through-silicon-via construction manufacturing method | |
| CN106684031A (en) | Manufacturing method of semiconductor structure | |
| TWI601185B (en) | A semiconductor wafer cleaning tank and a method of manufacturing a bonded wafer | |
| CN108597982A (en) | Wafer processing method | |
| CN105097432B (en) | Wafer processing method | |
| JP2021507540A (en) | Selective etching to reduce cone formation in shallow trench isolation | |
| US9659874B2 (en) | Method of forming deep trench and deep trench isolation structure | |
| CN101866876B (en) | Process for manufacturing contact hole | |
| CN108257864A (en) | Wafer processing method | |
| CN101625999A (en) | Manufacturing method of SONOS storage | |
| US6872630B1 (en) | Using V-groove etching method to reduce alignment mark asymmetric damage in integrated circuit process | |
| CN105742183B (en) | The forming method of semiconductor structure | |
| CN115295409A (en) | Wafer scribing method | |
| CN105336585A (en) | Etching method and formation method of interconnection structure | |
| US7084054B2 (en) | Method for making an opening for electrical contact by etch back profile control | |
| CN107799408B (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180928 |
|
| RJ01 | Rejection of invention patent application after publication |