CN115295409A - Wafer scribing method - Google Patents
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- CN115295409A CN115295409A CN202210857760.9A CN202210857760A CN115295409A CN 115295409 A CN115295409 A CN 115295409A CN 202210857760 A CN202210857760 A CN 202210857760A CN 115295409 A CN115295409 A CN 115295409A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Dicing (AREA)
Abstract
The embodiment of the disclosure provides a wafer scribing method, which comprises the following steps: providing a wafer, wherein the surface of the wafer is provided with a plurality of chip areas and scribing channels positioned between the chip areas; etching the wafer along the thickness direction of the wafer in the scribing channel to form a groove; and scribing the wafer along the groove to obtain a plurality of separated chips.
Description
Technical Field
The disclosure relates to the field of semiconductor manufacturing, in particular to a wafer scribing method.
Background
Wafers are basic materials for manufacturing semiconductor devices and are widely used in various electronic devices. A wafer usually contains a plurality of chips, and in order to obtain a single chip, the whole wafer needs to be diced. The process of dicing the entire wafer into individual chips by chip size is called wafer dicing.
In the conventional wafer dicing, a blade or a laser cutting method is used to cut the entire wafer from top to bottom in a dicing lane of the wafer, thereby obtaining a single chip. In the cutting process, stress damage is easily caused to the wafer, and the situation of chipping or flying occurs, so that the chip is damaged, and the yield of the chip is reduced. Although the damage to the chip during dicing can be reduced by increasing the width of the scribe line, it inevitably occupies the chip area. Moreover, the traditional wafer scribing method has strict requirements on the performance of the blade or the laser and has higher cost.
Disclosure of Invention
In view of this, an embodiment of the present disclosure provides a wafer dicing method, including:
providing a wafer, wherein the surface of the wafer is provided with a plurality of chip areas and scribing channels positioned between the chip areas;
etching the wafer along the thickness direction of the wafer in the scribing channel to form a groove;
and scribing the wafer along the groove to obtain a plurality of separated chips.
In some embodiments, the etching the wafer along the thickness direction of the wafer at the scribe lane to form a trench includes:
and etching the wafer along the thickness direction of the wafer in the scribing channel by adopting a silicon through hole process to form a groove.
In some embodiments, the etching the wafer along the thickness direction of the wafer in the scribe lane by using a through silicon via process to form a trench includes:
carrying out photoetching treatment on the surface of the wafer to form a patterned photoresist layer;
etching the wafer based on the pattern corresponding to the photoresist layer to form the groove; and the pattern corresponding to the photoresist layer is positioned in the scribing channel.
In some embodiments, the etching the wafer includes:
and etching the wafer by using dry etching and/or wet etching.
In some embodiments, the wafer dicing method further comprises:
and removing the photoresist layer after etching the wafer.
In some embodiments, before the dicing the wafer along the trench, the method further comprises:
and thinning the back surface of the wafer, wherein the back surface of the wafer is the other surface for forming the groove.
In some embodiments, the depth of the trench is less than or equal to 75% of the wafer thickness.
In some embodiments, the width of the trench is less than or equal to the width of the scribe lane.
In some embodiments, the wafer comprises:
a substrate and a device forming layer on the substrate; the depth of the trench is greater than or equal to the thickness of the device forming layer.
In some embodiments, the device formation layer located at the chip region is used to form a chip.
The wafer scribing method provided by the embodiment of the disclosure comprises the following steps: providing a wafer, wherein the surface of the wafer is provided with a plurality of chip areas and scribing channels positioned between the chip areas; etching the wafer along the thickness direction of the wafer in the scribing channel to form a groove; and scribing the wafer along the groove to obtain a plurality of separated chips. Therefore, the wafer is etched, the groove is formed in the scribing channel position of the wafer, and the groove is cut in the groove by combining the traditional method, so that the damage to the chip during cutting can be reduced, and the yield of the chip is improved; meanwhile, the area of the wafer chip area is not occupied.
Drawings
Fig. 1 is a schematic flow chart of a wafer dicing method according to an embodiment of the disclosure;
fig. 2 is a partial top view of a wafer having chip areas and scribe lanes provided in an embodiment of the present disclosure;
fig. 3 is a partial top view of a wafer having chip areas and scribe lanes provided in an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional view of a trench according to an embodiment of the disclosure;
fig. 5 is a schematic cross-sectional view of a wafer with a device formation layer according to an embodiment of the disclosure;
fig. 6 is a schematic cross-sectional view of a trench according to an embodiment of the present disclosure;
fig. 7 is a schematic cross-sectional view of a wafer coated with a photoresist according to an embodiment of the disclosure.
Detailed Description
To facilitate an understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the associated drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In some embodiments, some technical features that are well known in the art are not described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment may be described herein, and well-known functions and constructions may not be described in detail.
In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily expressly described, again depending at least in part on the context.
Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be set forth in the following description in order to explain the technical aspects of the present disclosure. The following detailed description of the preferred embodiments of the disclosure, however, the disclosure can be practiced otherwise than as specifically described.
As shown in fig. 1, an embodiment of the present disclosure provides a wafer dicing method, including:
step S101, providing a wafer, wherein the surface of the wafer is provided with a plurality of chip areas and scribing channels positioned among the chip areas;
step S102, etching the wafer along the thickness direction of the wafer in the scribing way to form a groove;
and S103, scribing the wafer along the grooves to obtain a plurality of separated chips.
The wafer may be a wafer on which a plurality of chips arranged in an array are formed, or may be a wafer die or a wafer on which an epitaxial layer is grown.
The substrate of the wafer may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, siGe, siGeC, siC, gaAs, inAs, inP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included. The epitaxial layer of the wafer may include silicon oxide, silicon nitride, and the like, and is not particularly limited herein.
The chip area herein is used to form various chips, such as memory chips, processor chips, and the like. In the process involved in the embodiments of the present disclosure, the chips in the chip area are bare chips without package processing. After the dicing operation in the embodiment of the present disclosure is performed, the chip regions are separated, so that the chips on the same wafer are separated into independent dies. Then, the chip products such as the memory chip, the processor chip and the like can be obtained by packaging.
In the embodiment of the present disclosure, scribe lines are provided between chip regions of a wafer, and the scribe lines may be positions to be scribed that are determined in a process of manufacturing chips. In the chip manufacturing process, the chip region may be processed to finally form a chip in the chip region, and of course, some structures or film layers may also be formed on the scribe line simultaneously in the chip manufacturing process. But these structures or film layers on the dicing streets do not affect the devices in the chip area so dicing can be performed on the streets during the final dicing process.
In some embodiments, as shown in fig. 2, a scribe lane 102 may be included between two adjacent chip regions 101, the width of the scribe lane 102 is W1, the scribe lane 102 is a boundary of the two chip regions 101, and the chip regions 101 on both sides of the scribe lane 102 are separated by a dicing process. In other embodiments, as shown in fig. 3, two parallel scribe lanes 103 may be provided between two chip regions 101, and a certain scribe region may be provided between the two scribe lanes 103. After dicing, not only the two chip regions 101 are separated, but also independent dicing regions are separated. The scribe area can be used to form some test structures during the manufacturing process and for testing during the manufacturing process. After dicing, these test structures are no longer needed and can be removed with the dicing operation.
In the embodiment of the present disclosure, before scribing the wafer, an etching process is first used to form a trench on the scribe line 102. The etching process may include dry etching or wet etching, etc.
The etching process can accurately position the position of the to-be-scribed channel 102 on the wafer, and the width and the depth of the etched groove are convenient to control. For example, the width of the scribe lane 102 is W1, and the thickness of the wafer is H1. In some embodiments, the etching may be performed at the position of the scribe line 102 by controlling the etching process parameters, so as to form a trench 104 with a width W2 and a depth H2, as shown in fig. 4. Here, the width W2 of the trench 104 may be less than or equal to the width W1 of the scribe lane 102; the depth H2 of the trench 104 may be less than the thickness H1 of the wafer.
In some embodiments, as shown in fig. 5, the wafer comprises: the wafer comprises a substrate 100 and a device forming layer 110 positioned on the substrate 100; the depth of the trench 104 is greater than or equal to the thickness of the device formation layer 110.
In some embodiments, the device formation layer 110 located in the chip region 101 is used to form a chip.
The device formation layer 110 may include various devices for constituting the above chip region 101, and may further include various film layers, for example, a protective layer for protecting a chip structure. Of course, the device formation layer 110 may cover the scribe area on the scribe lane 102 or between two scribe lanes 103, and may include some devices or film layers. The device formation layer 110 referred to herein is only a structure that generally describes a certain thickness in a wafer and may include various device structures for constituting chips, and is not limited to the actual specific structure of the chips included in the wafer.
In the embodiment of the present disclosure, the depth of the trench formed by the etching may be greater than the thickness of the device formation layer 110. As shown in fig. 6, the wafer includes a substrate 100 and a device forming layer 110 on the substrate 100, the device forming layer 110 has a thickness H3, the depth H2 of the trench 104 is greater than H3 but less than the thickness H1 of the wafer, and the device forming layer 110 is etched through. Therefore, when the wafer is scribed, the wafer has good mechanical stress, the conditions of wafer breakage and flying during the process of cutting the wafer are reduced, and the performance of the chip is reduced due to damage to a chip device layer during cutting.
In some embodiments, the depth H2 of the trench 104 is less than or equal to 75% of the wafer thickness H1, and may be greater than the thickness H3 of the device formation layer 110 described above. Namely, H3 is not less than H2 is not less than 75% multiplied by H1. Therefore, on one hand, the stress of the wafer is uniform during subsequent scribing, the situation of wafer breakage and flying is not easy to occur, and the possibility of damage to the chip is reduced. On the other hand, the condition that the wafer is damaged or other damages are caused in the etching process can be reduced.
In some embodiments, the width W2 of the trench 104 is less than or equal to the width W1 of the scribe lane 102, i.e., W2 ≦ W1. Therefore, the condition that the scribing position deviates to damage the chip can be reduced, and because the precision of the etching process is higher, an excessively wide scribing channel is not needed, the utilization rate of the wafer area can be improved, the cost is reduced, and the product yield is improved.
In some embodiments, a through-silicon via etching method may be used to etch the scribe lines 102 to form trenches 104 with controllable width and depth. The etching process may include dry etching or wet etching, etc.
The through silicon via technology is a technology for realizing interconnection between chips by making vertical conduction between the chips and between a wafer and the wafer, and the core of the through silicon via technology is to process through holes on the wafer. By using the through-silicon-via technology, etching is performed on the scribe lines 102, and the width and depth of the trenches 104 formed by etching can be more accurately controlled.
In some embodiments, etching the wafer along the thickness direction of the wafer in the scribe lane 102 by using a through silicon via process to form a trench 104 includes:
carrying out photoetching treatment on the surface of the wafer to form a patterned photoresist layer;
etching the wafer based on the pattern corresponding to the photoresist layer to form the trench 104; wherein, the pattern corresponding to the photoresist layer is located in the scribe line 102.
The photolithography process may be to coat a photoresist layer on the surface of the wafer, and then form a patterned photoresist layer through exposure and development. In the embodiment of the disclosure, as shown in fig. 7, the pattern corresponding to the photoresist layer 120 is located at the position of the scribe lane 102 of the wafer, the photoresist pattern is used as a mask to etch the position of the scribe lane 102, but the position including the chip region 101 outside the scribe lane 102 is not etched, and the trench 104 having a width W2 and a depth H2 is formed by controlling the etching process parameters.
In some embodiments, the through silicon via etching process may be a deep silicon etching process using a plasma dry etching process. Firstly, carrying out photoetching treatment on the surface of a wafer, and as shown in fig. 7, forming a patterned photoresist layer 120, wherein a pattern corresponding to the photoresist layer 120 is located at the position of a scribing street 102 of the wafer; and then, etching the position of the scribing channel 102 by using a deep silicon etching machine by taking the photoresist pattern as a mask, and forming a groove 104 with the width of W2 and the depth of H2 by controlling the etching process parameters. Compared with the general etching process, the deep silicon etching process is mainly different in that the etching depth is far greater than that of the general silicon etching process. The etching depth of a general silicon etching process is usually less than 1 μm, while the etching depth of a through silicon via etching process is tens of micrometers or even hundreds of micrometers, and has a large aspect ratio. Therefore, by adopting the etching method of the deep silicon etching process, the trench 104 with a larger depth-to-width ratio can be formed, i.e. the depth H2 of the trench 104 is larger than several tens of times of W2, so as to obtain a better trench 104 morphology.
In some embodiments, the through silicon via etching process may be a wet etching method. The wet etching process adopts etching liquid to etch the etching object, and the etching liquid has a corrosion effect on the etching object. Firstly, carrying out photoetching treatment on the surface of a wafer to form a patterned photoresist layer 120, wherein the pattern corresponding to the photoresist layer 120 is positioned at the position of a scribing channel 102 of the wafer; then, a solution capable of corroding the wafer, such as sulfuric acid, nitric acid, hydrofluoric acid, potassium hydroxide, and the like, may be selected as an etching solution, and based on the pattern corresponding to the photoresist layer 120, a wet etching device is used to etch the position of the scribe streets 102 in the wet etching groove by using the etching solution, or the wet etching device may be used to etch the position by spraying, and the trench 104 having a width W2 and a depth H2 is formed by controlling the etching process parameters. Compared with a dry etching process, the wet etching process has the advantages of low damage to the surface, good repeatability, simple operation and high etching rate.
In some embodiments, the wafer dicing method further comprises: after the wafer is etched, the photoresist layer 120 is removed.
The photoresist serves as a mask material to copy and transfer patterns in the etching process, and once the etching process is completed, the photoresist is completely removed.
During the etching process, the surface of the wafer is subjected to a photolithography process to form a patterned photoresist layer 120, and the photoresist layer 120 covers the chip region 101 on the surface of the wafer. After the etching is finished, the photoresist on the surface of the wafer 120 may be removed by exposing the photoresist to a plasma atmosphere, such as oxygen plasma, and by the reaction between the active ions in the plasma atmosphere and the photoresist, the bombardment of the plasma may remove the photoresist, thereby obtaining a clean wafer.
In some embodiments, before the dicing the wafer along the trench 104, the method further comprises: and thinning the back surface of the wafer, wherein the back surface of the wafer is the other surface for forming the groove 104.
The back thinning of the wafer is to carry out thinning processes such as grinding, chemical mechanical polishing, plasma etching and the like on the back base material of the wafer which is manufactured with the finished functions, and remove the material with certain thickness on the back of the wafer to enable the material to reach the required thickness. The thinned chip at least has the following advantages: (1) The heat diffusion efficiency is improved, and the thin chip is more favorable for heat dissipation; (2) The packaging volume of the chip is reduced, microelectronic products are increasingly developed towards light, thin, short and small, and the reduction of the packaging volume of the chip is a necessary way to adapt to the development trend; (3) The mechanical property is improved, the mechanical property of the thinned chip is obviously improved, the thinner the silicon chip is, the better the flexibility is, and the smaller the stress caused by external force impact is; (4) The scribing processing amount is reduced, and the wafer is cut after being thinned, so that the processing amount during scribing can be reduced, and the incidence rate of edge breakage of the wafer is reduced.
After removing the photoresist on the surface of the wafer, adhering a clean wafer to the thin film, then adsorbing the thin film and the wafer to the porous ceramic wafer bearing table by utilizing vacuum, and grinding the wafer by using a grinding machine to obtain the wafer with the required thickness; and scribing the thinned wafer to obtain a plurality of separated chips. The back surface of the wafer is thinned, so that the chip obtained after scribing meets the requirements of a subsequent packaging process, the physical strength, the heat dissipation performance, the size and the like of the chip.
It should be noted that the features disclosed in several method or apparatus embodiments provided in the embodiments of the present disclosure may be combined arbitrarily to obtain a new method embodiment or apparatus embodiment without conflict.
The above description is only a specific implementation of the embodiments of the present disclosure, but the scope of the embodiments of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the embodiments of the present disclosure, and all the changes or substitutions should be covered by the scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A method of wafer dicing, the method comprising:
providing a wafer, wherein the surface of the wafer is provided with a plurality of chip areas and scribing channels positioned between the chip areas;
etching the wafer along the thickness direction of the wafer in the scribing channel to form a groove;
and scribing the wafer along the groove to obtain a plurality of separated chips.
2. The method of claim 1, wherein the etching the wafer along the thickness direction of the wafer at the scribe lanes to form trenches comprises:
and etching the wafer along the thickness direction of the wafer in the scribing channel by adopting a silicon through hole process to form a groove.
3. The method of claim 2, wherein the etching the wafer along the thickness direction of the wafer at the scribe lane to form a trench using a through silicon via process comprises:
carrying out photoetching treatment on the surface of the wafer to form a patterned photoresist layer;
etching the wafer based on the pattern corresponding to the photoresist layer to form the groove; and the pattern corresponding to the photoresist layer is positioned in the scribing channel.
4. The method of claim 3, wherein said etching said wafer comprises:
and etching the wafer by using dry etching and/or wet etching.
5. The method of claim 3, wherein the method further comprises:
and removing the photoresist layer after etching the wafer.
6. The method of claim 1, wherein prior to said dicing said wafer along said trenches, said method further comprises:
and thinning the back surface of the wafer, wherein the back surface of the wafer is the other surface for forming the groove.
7. The method of claim 1, wherein the depth of the trench is less than or equal to 75% of the wafer thickness.
8. The method of claim 1, wherein a width of the trench is less than or equal to a width of the scribe lane.
9. The method of claim 1, wherein the wafer comprises:
a substrate and a device forming layer on the substrate; the depth of the trench is greater than or equal to the thickness of the device forming layer.
10. The method of claim 9, wherein the device formation layer at the chip region is used to form a chip.
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| CN202210857760.9A CN115295409A (en) | 2022-07-20 | 2022-07-20 | Wafer scribing method |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070074937A (en) * | 2006-01-11 | 2007-07-18 | 삼성전자주식회사 | Method for dicing semiconductor wafer using trench along scribe lane |
| CN102097287A (en) * | 2009-12-15 | 2011-06-15 | 北大方正集团有限公司 | Method for monitoring chip groove depth and wafer |
| CN106252388A (en) * | 2016-04-08 | 2016-12-21 | 苏州能讯高能半导体有限公司 | Semiconductor crystal wafer and manufacture method thereof |
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| CN109449084A (en) * | 2018-09-27 | 2019-03-08 | 全球能源互联网研究院有限公司 | A kind of dicing method and semiconductor devices of power chip |
| CN110208905A (en) * | 2019-05-24 | 2019-09-06 | 宁波东立创芯光电科技有限公司 | For improving the scribing etching of optical chip cut quality and the production method and optical chip of optical chip |
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2022
- 2022-07-20 CN CN202210857760.9A patent/CN115295409A/en active Pending
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| KR20070074937A (en) * | 2006-01-11 | 2007-07-18 | 삼성전자주식회사 | Method for dicing semiconductor wafer using trench along scribe lane |
| CN102097287A (en) * | 2009-12-15 | 2011-06-15 | 北大方正集团有限公司 | Method for monitoring chip groove depth and wafer |
| CN106252388A (en) * | 2016-04-08 | 2016-12-21 | 苏州能讯高能半导体有限公司 | Semiconductor crystal wafer and manufacture method thereof |
| CN109216272A (en) * | 2018-09-04 | 2019-01-15 | 盛世瑶兰（深圳）科技有限公司 | A kind of crystal circle structure and its processing method |
| CN109449084A (en) * | 2018-09-27 | 2019-03-08 | 全球能源互联网研究院有限公司 | A kind of dicing method and semiconductor devices of power chip |
| CN110208905A (en) * | 2019-05-24 | 2019-09-06 | 宁波东立创芯光电科技有限公司 | For improving the scribing etching of optical chip cut quality and the production method and optical chip of optical chip |
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