CN101908474B - Method for manufacturing gate on wafer - Google Patents

Method for manufacturing gate on wafer Download PDF

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Publication number
CN101908474B
CN101908474B CN2009100859974A CN200910085997A CN101908474B CN 101908474 B CN101908474 B CN 101908474B CN 2009100859974 A CN2009100859974 A CN 2009100859974A CN 200910085997 A CN200910085997 A CN 200910085997A CN 101908474 B CN101908474 B CN 101908474B
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layer
etching
nonnitrogenous
coating
amorphous state
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CN101908474A (en
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游宽结
张文广
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Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

The invention discloses a method for manufacturing a gate on a wafer. After depositing a gate oxide layer, a polycrystalline silicon layer, an amorphous carbon layer, a nonnitrogenous anti-reflection layer and a photoresist layer on a wafer substrate in turn, the method also comprises the following steps of: etching the nonnitrogenous anti-reflection layer according to the pattern of the photoresist layer, and removing the photoresist layer after the pattern on the nonnitrogenous anti-reflection layer is formed; etching the amorphous carbon layer according to the pattern of the nonnitrogenous anti-reflection layer, and forming a pattern on the amorphous carbon layer; and etching the polycrystalline silicon layer and the gate oxide layer in turn for ashing according to the pattern of the amorphous carbon layer, and obtaining the gate on the wafer substrate. The gate manufactured by the method can accord with the preset pattern.

Description

On wafer, make the method for grid
Technical field
The present invention relates to semiconductor fabrication techniques, particularly a kind of method of on wafer, making grid.
Background technology
In the semi-conductor industry development of last decade, the development of photoetching technique plays decisive role.In integrated circuit (IC, the Intergrated Circuit) technology of semi-conductor industry, the development of photoetching technique plays most effect to the cost savings of each wafer.Along with the stable raising of photoetching technique, the wavelength of optical signal that the exposure in the photoetching is adopted is shorter and shorter, and on this basis, the raising of the lithographic technique of IC depends on camera lens and the technological development of developing material of carrying out photoetching.But the characteristic size of As IC (CD) is reduced into 45 nanometers or littler, and IC gets into submicron-scale, realizes that in IC photoetching technique becomes challenge, particularly adopts photoetching technique on the wafer of IC, to make grid.
Along with the CD of wafer dwindles; Grid live width on the wafer substrate also diminishes; Thereby when the grid that lithographic line width diminishes; The thickness of the photoresist layer that is adopted (PR) also need reduce, otherwise the final shape that on wafer, forms grid of influence can appear decaying in PR in exposure process and follow-up etching process.But the PR that thickness reduces is in etching process, and with respect to the polysilicon layer as grid, etching selection ratio also can correspondingly reduce, and needs high etching selection Bizet can form the grid of predesignating shape when making grid.Therefore, the PR that thickness reduces can cause the effect of etching grid bad, the gate shapes that influence is finally made on wafer.
To sum up, in order to solve above-mentioned contradiction, proposed between the polysilicon layer of PR and wafer substrate; Increase amorphous carbon (AC, Amorphous Carbon) layer, this AC layer is compared with PR; Harder, in exposure process and subsequent process, can not occur decaying, and with respect to the polysilicon layer as grid; Improve etching selection ratio, guarantee that in etching process the thickness of PR is thinner.
In conjunction with the sectional structure chart of the prior art manufacturing grid on wafer shown in Fig. 1 a～1d, specify the process of prior art manufacturing grid on wafer.
Step 1 behind deposition gate oxide 101 and polysilicon layer 102 on the wafer substrate 100, deposits AC layer 103, nonnitrogenous anti-reflecting layer (NFARL, Nitrogen Free Anti-ReflectiveLayer) 104 and PR105, shown in Fig. 1 a more successively.
In this step, the thickness of polysilicon layer 102 is that 1900 Izods are right; AC layer 103 can be constructed the hard figure of constructing than PR105 in the subsequent etching process, improve the CD control and the etching performance of grid, and general thickness is that 2000 Izods are right; NFARL 104 prevents the light reflection at exposure process, and thickness is that 750 Izods are right; The thickness of PR105 is that 2500 Izods are right.
In this step, the AC layer can adopt chemical vapor deposition (CVD) method deposition to obtain, and NFARL also can adopt the CVD method to obtain, and perhaps adopts plasma reinforced chemical vapour deposition (PECVD) method to obtain.
Step 2, after the structure shown in Fig. 1 a made public, with figure transfer to PR105, shown in Fig. 1 b.
In this step, the shape of figure is exactly the final gate shapes that on wafer substrate 100, forms.
Step 3 according to the figure on PR105, is carried out etching to NFARL 104, AC layer 103, polysilicon layer 102 and gate oxide 101 successively, on wafer substrate 100, obtains gate shapes, shown in Fig. 1 c.
In this step, the process of concrete etching N FARL 104, AC layer 103, polysilicon layer 102 and gate oxide 101 can adopt industrywide standard to carry out, such as adopting hydrogen fluoride HF to carry out etching, and no longer tired here stating.
This step has adopted a lithographic technique that multilayer has been carried out etching, wherein NFARL 104 is carried out etching with AC layer 103 and adopts dry etching, and polysilicon layer 102 and gate oxide 101 are adopted dry etching, can certainly adopt wet etching.
Step 4 is carried out cineration step to the structure shown in Fig. 1 c, removes PR105, NFARL 104 and AC layer 103, on wafer substrate 100, forms grid, shown in Fig. 1 d.
In the ashing flow process, wafer substrate 100 is heated, and PR105 on the wafer substrate 100 and AC layer 103 are exposed in oxygen plasma or the ozone and react simultaneously, are eliminated.Here it should be noted that its main component is a silica, so in podzolic process, can not be removed because NFARL104 is an inorganic matter.
After carrying out step 4; This method also comprises cleaning step, can adopt wet-cleaned, such as such as adopting sulfuric acid; The mixed liquor of hydrogen peroxide and deionized water cleans etc., remove formed top portions of gates and wafer substrate 100 surfaces after the ashing residue.
Adopt this process on wafer substrate 100, to make grid, but but there is defective in the grid of manufacturing.This be because: because NFARL 104 is inorganic anti-reflective coatings; Material is an inorganic matter; When carrying out ashing and follow-up cleaning step be difficult to be eliminated, and AC layer 103 is respectively organic matter layer with PR105, so in the podzolic process process, be prone to be eliminated.Like this, the NFARL 104 that can't remove has just dropped on wafer substrate 100 formed top portions of gates, the grid sectional structure chart of manufacturing as shown in Figure 2.Can find out in the drawings, do not dropped on the top portions of gates by the NFARL 104 of ashing.The grid that this manufacturing obtains can bring problem: on the one hand; Because there is a strong possibility can not vertically drop on wafer substrate 100 formed top portions of gates for the NFARL 104 that can't remove; Cause between the grid of manufacturing on the wafer and grid in top interconnect, short circuit appears in the semiconductor device that finally can cause making; On the other hand; After having made grid on the wafer; Also to make metal interconnecting layer or/and dielectric layer on the upper strata; But because the NFARL 104 that can't remove drops on wafer substrate 100 formed top portions of gates, cause top portions of gates uneven, at the metal interconnecting layer of making the upper strata or/and encounter difficulties during dielectric layer and maybe can't make.
To sum up, adopt the method for prior art, can't on wafer, make the grid that meets preset figure.
Summary of the invention
In view of this, the present invention provides a kind of method of on wafer, making grid, adopts the grid of this method manufacturing can meet preset figure.
For achieving the above object, the technical scheme of the embodiment of the invention specifically is achieved in that
A kind of method of on wafer, making grid deposits gate oxide, polysilicon layer, amorphous state carbon-coating, nonnitrogenous anti-reflecting layer and photoresist layer successively on wafer substrate, behind the patterning photoresist layer, it is characterized in that this method also comprises:
According to the figure of photoresist layer, the nonnitrogenous anti-reflecting layer of etching after nonnitrogenous anti-reflecting layer forms figure, is removed photoresist layer;
According to the figure of nonnitrogenous anti-reflecting layer, etching amorphous state carbon-coating forms figure at the amorphous state carbon-coating;
According to the figure of amorphous state carbon-coating, behind etch polysilicon layer and the gate oxide, carry out ashing successively, on wafer substrate, obtain grid.
Before etching amorphous state carbon-coating, this method also comprises:
According to the figure of nonnitrogenous anti-reflecting layer, continue the nonnitrogenous anti-reflecting layer of etching, open the amorphous state carbon-coating.
Said etching amorphous state carbon-coating is: etching amorphous state carbon-coating is opened polysilicon layer till the polysilicon layer.
The nonnitrogenous anti-reflecting layer of said etching adopts dry etching.
The gas that said dry etching adopts is fluorocarbons CF4, and mixes use with oxygen and nitrogen;
Perhaps be hydrogen fluoride HF.
Said etching amorphous state carbon-coating adopts dry etching.
Said etch polysilicon layer and gate oxide adopt dry etching.
Said ashing is:
Wafer substrate is heated, and is not etched away the AC layer simultaneously on the wafer substrate and is exposed to reaction removal in oxygen plasma or the ozone.
This method also comprises: adopt wet method that resulting top portions of gates and wafer substrate surface are cleaned.
Visible by technique scheme, when the present invention makes grid on wafer, adopt the multiple etching mode with the figure transfer of PR105 patterning gate oxide 101 and polysilicon layer 102, formation grid to wafer substrate 100.In the multiple etching process; It is difficult to by ashing and is difficult to removed NFARL104 layer at follow-up cleaning step be etched away; Finally by ashing and what clean only is to be prone to removed residue AC layer 103; Like this, just any material can not occur, make the grid of manufacturing meet preset figure at the final top portions of gates that forms.
Description of drawings
Fig. 1 a～1d is the sectional structure chart of prior art manufacturing grid on wafer;
Fig. 2 is the grid sectional structure chart of prior art manufacturing;
Fig. 3 a～3f is the sectional structure chart of the present invention's manufacturing grid on wafer;
Fig. 4 is a method flow diagram of on wafer, making grid;
Fig. 5 is the grid sectional structure chart of manufacturing of the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is done further explain.
Can find out from the method for prior art manufacturing grid on wafer; Cause manufacturing top portions of gates on the wafer substrate 100 NFARL104 former appears because: because after an etching forms gate shapes; When follow-up ashing and cleaning step, NFARL104 is difficult to be removed clean.For the grid in the wafer manufacturing can meet preset figure, the present invention adopts the multiple etching mode with the figure transfer of the PR105 patterning gate oxide 101 and polysilicon layer 102 to wafer substrate 100, forms grid.In the multiple etching process; It is difficult to be etched away by the NFARL104 layer of ashing and cleaning, finally by ashing and cleaning only be to be prone to removed residue AC layer 103, like this; Just any material can not occur at the final top portions of gates that forms, make the grid of manufacturing meet preset figure.
Adopt the present invention after making grid; There is not any material and level and smooth in top portions of gates; Therefore can not interconnect between grid and the grid, can not cause the final semiconductor device of making the situation of short circuit to occur, at the metal interconnecting layer of making the upper strata or/and can not encounter difficulties during dielectric layer yet.
In conjunction with the sectional structure chart of the present invention's manufacturing grid on wafer shown in Fig. 3 a～3f, adopt the method flow diagram of on wafer, making grid shown in Figure 4, specify method provided by the invention.The concrete steps of method flow diagram shown in Figure 4 are:
Step 401, behind deposition gate oxide 101 and polysilicon layer 102 on the wafer substrate 100, deposit AC layer 103, NFARL104 and PR105 more successively, make public then, figure transfer to PR105, is obtained the structure shown in Fig. 3 a.
In this step, the thickness of polysilicon layer 102 is that 1900 Izods are right; AC layer 103 can be constructed the hard figure of constructing than PR105 in the subsequent etching process, improve the CD control and the etching performance of grid, and general thickness is that 2000 Izods are right; NFARL104 prevents that at exposure process the light of AC layer 103 from reflecting, and thickness is that 750 Izods are right; The thickness of PR105 is that 2500 Izods are right.
In this step, NFARL104 adopts CVD or PECVD deposition, and AC layer 103 adopts the CVD deposition, and PR105 can adopt the mode of coating to carry out.
Step 402, according to the figure on PR105, NFARL 104 is carried out etching, obtain the structure shown in Fig. 3 b.
In this step, etching is not fully or fully, the lithographic method of employing is a dry etching to NFARL104, and etching gas can be fluorocarbons (CF 4), and mix use with oxygen and nitrogen, owing to comprise silica material among the NFARL104, use these gases can etch away this NFARL104 like this.
In this step, etching gas also can adopt hydrogen fluoride (HF) to carry out, and this hydrogen fluoride (HF) can etch away NFARL104.
Step 403, removal PR105 obtain the structure shown in Fig. 3 c.
In this step, the method for removing PR105 can adopt art methods to carry out, such as adopting wet method method of removaling or the employing dry plasma method of removing photoresist.
Step 404, according to the figure on the NFARL104 in the structure shown in the 3c, continue etching, up to AC layer 103, obtain the structure shown in Fig. 3 d.
In this step; NFARL104 is being carried out in the process of etching, still adopting the mode of step 402 to carry out dry etching, it is right that NTFARL104 thickness also is reduced to 530 Izods; The purpose of this step is opened the NTFARL104 layer exactly, exposes AC layer 103 according to the figure on the NFARL104.
When complete in step 402 pair NFARL104 etching, when having opened the AC layer, this step also can be omitted.
Step 405, according to the figure on the AC layer 103 in the structure shown in the 3d, continue etching, up to polysilicon layer 102, obtain the structure shown in Fig. 3 e.
In this step, adopt dry etching, etching can continue to reduce the thickness of NFARL, makes its thickness be reduced to the 120 Izods right side, and the purpose of this step is opened AC layer 104 exactly, according to figure exposed polysilicon layer 103.
In this step, during etching AC layer 103, also can change etching gas, such as etching gas is replaced by HF, make etching gas and 103 reaction of AC layer, etching AC layer.
Step 406, continue etch polysilicon layer 102 and gate oxide 101, obtain the structure shown in Fig. 3 f according to the figure on the AC layer 103 in the structure shown in the 3d.
In this step, carry out dry etching, passed through dry etching repeatedly, etched away NFARL104, and etching can make also the thickness of AC layer 103 reduce, be reduced to 1200 dusts.
In this step, can adopt existing three step process method that polysilicon layer 102 and gate oxide 101 are carried out dry etching, the main etching and the over etching of promptly preparatory etching, etching terminal.Etching gas can be CF 4, and mix use with oxygen and nitrogen.
Step 407, the structure shown in Fig. 3 f is carried out ashing treatment, remove AC layer 103, finally on the substrate 101 of wafer, obtain grid.
In the ashing flow process, wafer substrate 100 is heated, and the AC layer 103 on the wafer substrate 100 is exposed in oxygen plasma or the ozone and reacts simultaneously, and the carbon of AC layer 103 is inorganic matter, is easy to be eliminated.
After Fig. 4, can also comprise cleaning step, can adopt wet-cleaned, such as adopting sulfuric acid, the mixed liquor of hydrogen peroxide and deionized water cleans etc., removes the surperficial residue of formed top portions of gates and wafer substrate after the ashing 100.
Fig. 5 is the grid sectional structure chart of manufacturing of the present invention, can find out, there has not been the NFARL that is not eliminated in the formed top portions of gates of method that provides according to Fig. 4 of the present invention.
More than lift preferred embodiment; The object of the invention, technical scheme and advantage have been carried out further explain, and institute it should be understood that the above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification of being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (8)

1. a method of on wafer, making grid deposits gate oxide, polysilicon layer, amorphous state carbon-coating, nonnitrogenous anti-reflecting layer and photoresist layer successively on wafer substrate, behind the patterning photoresist layer, it is characterized in that this method also comprises:
According to the figure of photoresist layer, the nonnitrogenous anti-reflecting layer of etching after nonnitrogenous anti-reflecting layer forms figure, is removed photoresist layer;
According to the figure of nonnitrogenous anti-reflecting layer, continue the nonnitrogenous anti-reflecting layer of etching, open the amorphous state carbon-coating;
According to the figure of nonnitrogenous anti-reflecting layer, etching amorphous state carbon-coating forms figure at the amorphous state carbon-coating;
According to the figure of amorphous state carbon-coating, behind etch polysilicon layer and the gate oxide, carry out ashing successively, on wafer substrate, obtain grid.
2. the method for claim 1 is characterized in that, said etching amorphous state carbon-coating process is: etching amorphous state carbon-coating is opened polysilicon layer till the polysilicon layer.
3. the method for claim 1 is characterized in that, the nonnitrogenous anti-reflecting layer of said etching adopts dry etching.
4. method as claimed in claim 3 is characterized in that, the gas that said dry etching adopts is fluorocarbons CF 4, and mix use with oxygen and nitrogen;
Perhaps be hydrogen fluoride HF.
5. the method for claim 1 is characterized in that, said etching amorphous state carbon-coating adopts dry etching.
6. the method for claim 1 is characterized in that, said etch polysilicon layer and gate oxide adopt dry etching.
7. the method for claim 1 is characterized in that, said ashing is:
Wafer substrate is heated, and is not etched away the amorphous state carbon-coating simultaneously on the wafer substrate and is exposed to reaction removal in oxygen plasma or the ozone.
8. the method for claim 1 is characterized in that, this method also comprises: adopt wet method that resulting top portions of gates and wafer substrate surface are cleaned.
CN2009100859974A 2009-06-03 2009-06-03 Method for manufacturing gate on wafer Active CN101908474B (en)

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Publication number Priority date Publication date Assignee Title
CN107993922B (en) * 2017-11-30 2020-12-01 上海华力微电子有限公司 Method for preventing amorphous carbon film from peeling off caused by etching rework in control gate formation
CN110391175A (en) * 2018-04-16 2019-10-29 武汉新芯集成电路制造有限公司 A kind of preparation method of contact hole

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1961429A (en) * 2004-06-02 2007-05-09 德州仪器公司 Gate stack and gate stack etch sequence for metal gate integration
CN101290481A (en) * 2007-04-16 2008-10-22 应用材料公司 Etching process for controlling characteristic size shrinkage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1961429A (en) * 2004-06-02 2007-05-09 德州仪器公司 Gate stack and gate stack etch sequence for metal gate integration
CN101290481A (en) * 2007-04-16 2008-10-22 应用材料公司 Etching process for controlling characteristic size shrinkage

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