CN104241100A - Small-size graph making method - Google Patents
Small-size graph making method Download PDFInfo
- Publication number
- CN104241100A CN104241100A CN201410491203.5A CN201410491203A CN104241100A CN 104241100 A CN104241100 A CN 104241100A CN 201410491203 A CN201410491203 A CN 201410491203A CN 104241100 A CN104241100 A CN 104241100A
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- Prior art keywords
- small size
- silicon oxide
- manufacture method
- linear array
- silica
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a small-size graph making method. A layer of silicon oxide is grown on the surface of a wafer through a thermal oxidation method, then a layer of polycrystalline silicon settles, a layer of silicon nitride settles, a layer of silicon oxide settles, a polycrystalline silicon linear array graph is formed through a subsequent photoetching and etching process, and then exposure and etching are carried out on the polycrystalline silicon linear array graph through an LEC process. The small-size graph making method further comprises the steps that a hard mask layer on the polycrystalline silicon linear array graph is opened through a dry etching process, a layer of silicon oxide film settles through a low-temperature atomic layer deposition technology, finally, back etching is carried out on the silicon oxide film through the dry etching process, and then a small-size adjustable graph structure is formed.
Description
Technical field
The present invention relates to semiconductor manufacturing, particularly relate to the manufacture method of the small size figure in a kind of LEC technique.
Background technology
Along with process constantly reduces, particularly in 32 nanometers and following technology thereof, because grid width reduces further, to the ability of mask aligner and the requirement of photoetching process more and more higher.In order to reduce device critical dimensions further, improving its integrated level, there is various different solution in industry.
A solution of prior art is after utilizing existing ripe photoetching process to form linear array figure, apply one photoetching and etching technics and disconnect (i.e. Line End Cut technique along veritcal linearity array pattern steering handle linear array, be called for short LEC technique), finally form device that is independent and that repeat.
Fig. 1 is the schematic flow sheet of the manufacturing method thereof of the LEC art lithography exposure of prior art.Fig. 2 is the generalized section after the exposure of LEC art lithography.
In step slo, thermal oxidation method is adopted to grow one deck silica (SiO2) on wafer (Si) surface;
In step s 12, one deck polysilicon (Poly) is deposited;
In step S14, deposition one deck silicon nitride (SiN), forms the linear array pattern of polysilicon by follow-up photoetching and etching technics;
In step s 16, apply LEC technique expose the linear array pattern of polysilicon and etch.In more detail, first, utilize photoetching coating process to be coated with one deck Spun-on carbon oxide (SOC), make surface smooth; Subsequently, and the siliceous antireflecting coating of painting one deck (SHB, such as, Si-ARC); Finally, be coated with one deck photoresist (such as, ArF photoresist) and expose, the HTH formed as shown in Figure 2 is of a size of the figure of 55 nanometers.
Fig. 3 is that employing three layers of (Tri-layer) technology are etched SHB, SOC and SiN successively by dry etching and are parked in the generalized section on Poly; Fig. 4 is the generalized section that employing one step O2 cineration technics dispels the SOC on SiN.Fig. 5 etches Poly as barrier layer for utilizing SiN, the final generalized section forming head (Head To Head is called for short HTH) polysilicon structure that size is less to the end.
In order to improve device integration, after disconnecting linear array pattern by LEC technique, HTH size needs to accomplish 35 nanometers herein, but because photoetching is by board capabilities limits, HTH size in prior art after exposure is minimum is 55 nanometers, the requirement how reaching smaller szie (such as, 35 nanometers) becomes industry technical problem urgently to be resolved hurrily.
Summary of the invention
The technical problem to be solved in the present invention is the manufacture method providing a kind of small size figure, it can be applied in 32 nanometers and following technology thereof, to solve mask aligner ability not and photoetching and the problem such as etching technics window is not enough, reduction of device size simultaneously, improves semiconductor technology integrated level.
The manufacture method of the small size figure of one aspect of the present invention, first adopts thermal oxidation method to grow one deck silica at crystal column surface, then deposits one deck polysilicon, then deposit one deck silicon nitride, deposit one deck silica subsequently; The linear array pattern of polysilicon is formed by follow-up photoetching and etching technics, then apply LEC technique expose the linear array pattern of polysilicon and etch, wherein, the manufacture method of described small size figure also comprises: utilize dry etch process to open silicon oxide hardmask layer on described polycrystalline silicon linear array pattern; Utilize low temperature ald deposition techniques one deck silicon oxide film; Finally utilize dry etching to carry out back carving to described silicon oxide film, and then form small size and regulatable graphic structure.Wherein, hard mask layer on described polycrystalline silicon linear array pattern comprises described siliceous antireflecting coating, described Spun-on carbon oxide, described silica, and the thickness of the silicon oxide film of described employing low temperature ald deposition techniques is between 5 nanometer to 15 nanometers.
More preferably, described dry etch process comprises further: dispel the silicon oxide film on described silica, forms monox lateral wall; Utilize described monox lateral wall as silicon nitride described in barrier layer etch; Then utilize described silicon oxide film and silica as barrier layer etch polysilicon and rest on described bottom silica.Wherein, use CF4, CHF3 mist to dispel described silicon oxide film and silica, use CL2, SF6, CF4 mist to etch described polysilicon.
Compared with prior art, the present invention is based on the figure after photolithographic exposure in LEC technique, utilize low temperature ald technology and the dry etch process of industry comparative maturity, final formation head to the end between the distance structure that can freely regulate and control, drastically increase photoetching and etching technics window, thus solve photoetching and dry carving technology scarce capacity and process window comparatively minor issue in 32 nanometers and following technology thereof, further raising lithographic process window, reduce critical size, increase substantially the integrated level of device.
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is described in detail, to make characteristic of the present invention and advantage more obvious.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacturing method thereof of the LEC art lithography exposure of prior art;
Fig. 2 is the generalized section after the LEC art lithography exposure of prior art;
Fig. 3 to Fig. 5 is the generalized section in each step of LEC technique of prior art;
Figure 6 shows that the schematic flow sheet of the manufacture method of the small size figure of one embodiment of the invention;
Fig. 7 is to the generalized section in each step of manufacture method that Figure 10 shows that small size figure of the present invention.
Embodiment
Below will provide detailed description to embodiments of the invention.Although the present invention will carry out setting forth and illustrating in conjunction with some embodiments, it should be noted that the present invention is not merely confined to these execution modes.On the contrary, the amendment carry out the present invention or equivalent replacement, all should be encompassed in the middle of right of the present invention.
In addition, in order to better the present invention is described, in embodiment hereafter, give numerous details.It will be understood by those skilled in the art that do not have these details, the present invention can implement equally.In other example, known method, flow process, element and circuit are not described in detail, so that highlight purport of the present invention.
Fig. 6 is the schematic flow sheet of the manufacture method of the small size figure of one embodiment of the invention.As shown in the figure, the manufacture method of the small size figure of the present embodiment comprises the step identical with the manufacturing method thereof that the LEC art lithography of the prior art shown in Fig. 1 exposes, its difference is, after the step S16 of Fig. 1, the manufacture method of this small size figure also comprises:
Step S20, utilizes dry etch process to open hard mask layer on described polycrystalline silicon linear array pattern.Wherein, described hard mask layer comprises SiN.
Step S22, utilizes low temperature ald (Atomic Layer Deposition is called for short ALD) deposition techniques one deck ALD silica (ALD SiO2) film (please refer to Fig. 7).More particularly, by ALD technology accurately control ALD SiO2 film thickness (such as, making the thickness of described ALD SiO2 film between 5 nanometer to 15 nanometers), carry out the critical size after the exposure of free adjustment LEC technique with this.
Step S24, utilizes dry etch process to dispel ALD SiO2 film on SiO2, forms ALD SiO2 side wall (referring to Fig. 8).In one embodiment, use CF4, CHF3 mist dispels the ALD SiO2 film on SiO2.
Step S26, utilizes ALD SiO2 side wall as barrier layer etch SiN (referring to Fig. 9).In one embodiment, CF4, CHF3 mist etching SiN is used.
Step S28, utilizes ALD SiO2 and SiO2 as barrier layer etch Poly and rests on SiO2, forms small size and the graphic structure (referring to Figure 10) of controllable (such as, between 25 nanometer to 45 nanometers).In a preferred embodiment, CL2, SF6, CF4 mist is used to etch described polysilicon, the undersized graphic structure of final formation HTH.
Embodiment and accompanying drawing are only the conventional embodiment of the present invention above.Obviously, various supplement, amendment and replacement can be had under the prerequisite not departing from the present invention's spirit that claims define and invention scope.It should be appreciated by those skilled in the art that the present invention can change in form, structure, layout, ratio, material, element, assembly and other side under the prerequisite not deviating from invention criterion according to concrete environment and job requirement in actual applications to some extent.Therefore, be only illustrative rather than definitive thereof in the embodiment of this disclosure, the scope of the present invention is defined by appended claim and legal equivalents thereof, and is not limited thereto front description.
Claims (6)
1. a manufacture method for small size figure, first adopts thermal oxidation method to grow one deck silica at crystal column surface, then deposits one deck polysilicon, then deposit one deck silicon nitride, deposit one deck silica subsequently; Form the linear array pattern of polysilicon by follow-up photoetching and etching technics, then apply LEC technique and expose the linear array pattern of polysilicon and etch, it is characterized in that, the manufacture method of described small size figure also comprises:
Dry etch process is utilized to open silicon oxide hardmask layer on described polycrystalline silicon linear array pattern;
Utilize low temperature ald deposition techniques one deck silicon oxide film;
Finally utilize dry etching to carry out back carving to described silicon oxide film, and then form small size and regulatable graphic structure.
2. the manufacture method of small size figure according to claim 1, is characterized in that, the hard mask layer on described polycrystalline silicon linear array pattern comprises described siliceous antireflecting coating, described Spun-on carbon oxide, described silica.
3. the manufacture method of small size figure according to claim 1, is characterized in that, the thickness of the silicon oxide film of described employing low temperature ald deposition techniques is between 5 nanometer to 15 nanometers.
4. the manufacture method of small size figure according to claim 1, is characterized in that, described dry etch process comprises further:
Dispel described silicon oxide film, form monox lateral wall;
Utilize described monox lateral wall as silicon nitride described in barrier layer etch;
Utilize described silicon nitride film and silica as polysilicon described in barrier layer etch and rest on described bottom silica.
5. the manufacture method of small size figure according to claim 4, is characterized in that, uses CF4, CHF3 mist to dispel described silicon oxide film and silica.
6. the manufacture method of small size figure according to claim 4, is characterized in that, uses CL2, SF6, CF4 mist to etch described polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410491203.5A CN104241100A (en) | 2014-09-23 | 2014-09-23 | Small-size graph making method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410491203.5A CN104241100A (en) | 2014-09-23 | 2014-09-23 | Small-size graph making method |
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| CN104241100A true CN104241100A (en) | 2014-12-24 |
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| CN201410491203.5A Pending CN104241100A (en) | 2014-09-23 | 2014-09-23 | Small-size graph making method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143784A (en) * | 2018-08-15 | 2019-01-04 | 上海华力集成电路制造有限公司 | It include the wafer and its surface particles monitoring method of three layers of photoetching material on single substrate |
Citations (5)
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| CN101116177A (en) * | 2004-12-16 | 2008-01-30 | 兰姆研究有限公司 | Reduction of etch mask feature critical dimensions |
| CN101197262A (en) * | 2006-12-04 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Grids production method |
| CN102437092A (en) * | 2011-08-04 | 2012-05-02 | 上海华力微电子有限公司 | Semiconductor through hole forming method |
| US20120108068A1 (en) * | 2010-11-03 | 2012-05-03 | Texas Instruments Incorporated | Method for Patterning Sublithographic Features |
| CN103474337A (en) * | 2013-09-22 | 2013-12-25 | 上海华力微电子有限公司 | Method for manufacturing high-evenness grid electrode lines |
-
2014
- 2014-09-23 CN CN201410491203.5A patent/CN104241100A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101116177A (en) * | 2004-12-16 | 2008-01-30 | 兰姆研究有限公司 | Reduction of etch mask feature critical dimensions |
| CN101197262A (en) * | 2006-12-04 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Grids production method |
| US20120108068A1 (en) * | 2010-11-03 | 2012-05-03 | Texas Instruments Incorporated | Method for Patterning Sublithographic Features |
| CN102437092A (en) * | 2011-08-04 | 2012-05-02 | 上海华力微电子有限公司 | Semiconductor through hole forming method |
| CN103474337A (en) * | 2013-09-22 | 2013-12-25 | 上海华力微电子有限公司 | Method for manufacturing high-evenness grid electrode lines |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143784A (en) * | 2018-08-15 | 2019-01-04 | 上海华力集成电路制造有限公司 | It include the wafer and its surface particles monitoring method of three layers of photoetching material on single substrate |
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Application publication date: 20141224 |