KR100586177B1 - Method for pattern Formation of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method of forming a pattern of a semiconductor device, comprising the steps of: (a) forming a first etching barrier layer, an isotropic trimming layer, and a photoresist film on an object layer to be etched; (b) patterning the photoresist film; c) anisotropically etching the isotropic trimming layer using the patterned photoresist film as a mask, and etching the isotropic trimming layer until a predetermined line width is obtained by isotropic etching; and (d) removing the remaining photosensitive film and etching the patterned isotropic trimming layer. Provided is a method of forming a pattern of a semiconductor device in which a first etching barrier layer and a target layer are sequentially patterned using a mask.

Semiconductor device, trimming, pattern, photoresist

Description

Method for pattern formation of semiconductor device {Method for pattern Formation of Semiconductor Device}

1A is a diagram for describing a photoresist trimming technique according to the related art.

FIG. 1B is a view for explaining a problem of a conventional photoresist trimming technique.

2A to 2G are flowcharts illustrating a method of forming a pattern of a semiconductor device according to a first exemplary embodiment of the present invention.

3A to 3H are flowcharts illustrating a method of forming a pattern of a semiconductor device according to a second exemplary embodiment of the present invention.

The present invention relates to a method of forming a pattern of a semiconductor device.

As the line width becomes smaller in the semiconductor process, a problem of the pattern line width reduction technique (PR trimming technique) of the photosensitive film by conventional etching has emerged. This is the case when the photoresist is thin and the aspect ratio of the photoresist becomes large. In the former case, there is a difficulty in controlling CD by PR trimming and the utilization of residual PR as an etching mask. In this case, there is a technical limitation that CD nonuniformity occurs due to the change of the etching rate according to the density of the pattern.

A photoresist trimming technique according to the prior art will be described with reference to FIG. 1A. An etching barrier layer 2 serving as an organic or inorganic anti-reflection coating (ARC) and an etching barrier is formed on the target layer 1 to be etched. Then, the photoresist 3 is formed using photolithography. To form. Then, the photoresist is isotropically etched to reduce the CD, and then the thin etch mask film 2 is etched using the photoresist 3a as a mask, and then the target layer 1 is patterned using the mask, and the remaining photo is defined. The process is complete by removing the register.

However, when the line width of the photoresist pattern is reduced by the conventional photoresist trimming technique, the thickness of the photoresist and the etching resistance may be reduced, thereby effectively reducing the CD or controlling the CD width. It becomes difficult to do 1A illustrates this situation.

In addition, the conventional photoresist trimming technique shows that the pattern density dependence of the CD line width becomes very large due to the micro-loading phenomenon in the dense line pattern region and the isolated line pattern. 1B illustrates this situation.

In order to solve the above problems, an object of the present invention is to control the trimming rate through the etching gas chemistry, improve the etch selectivity between the mask and the isotropic trim layer to improve the process margin, the controllability It is to provide a method of forming a pattern of a semiconductor device to be excellent.

Another object of the present invention is to be able to configure a high-performance device or logic without improving lithography technology and exposure equipment, so that it is possible to develop a higher-performance product than can be realized with current exposure technology at low cost.

Yet another object of the present invention is to develop a high performance device and a product at low cost by enabling a simple etching process configuration and applying a plurality of mask layers to enable the formation of fine patterns beyond the limits of existing equipment without using high-cost advanced exposure equipment. To make it possible.

Another object of the present invention is not only to alleviate the micro-loading phenomenon, which is a problem in the prior art photoresist trimming process, but also to apply to the case where the PR thickness is thin and the etching resistance is poor. To make it possible.

As a technical means for achieving the above object, one aspect of the present invention comprises the steps of (a) forming a first etching barrier layer, an isotropic trimming layer and a photoresist film on the target layer to be etched, and (b) patterning the photoresist film (C) anisotropically etching the isotropic trimming layer using the patterned photosensitive film as a mask, and etching until the predetermined line width is obtained by isotropic etching, and (d) removing and patterning the remaining photosensitive film. Provided is a method of forming a pattern of a semiconductor device by sequentially patterning the first etch barrier layer and the target layer using the isotropic trimmed layer as an etch mask.

According to another aspect of the present invention, (a) forming a first etching barrier layer, an isotropic trimming layer, a second etching barrier layer and a photosensitive film on the target layer to be etched, (b) patterning the photosensitive film; c) etching the second etch barrier layer using the patterned photoresist mask and removing the remaining photoresist; (d) anisotropically etching the isotropic trim layer using the patterned second etch barrier layer as a mask; And etching until the line width is obtained by isotropic etching, and (e) patterning the first etching barrier layer and the target layer in sequence using the isotropic trimming layer as an etching mask. .

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; The present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention It is provided to inform you.

(First embodiment)

Hereinafter, a method of forming a pattern of a semiconductor device according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2G. 2A to 2G are flowcharts illustrating a method of forming a pattern of a semiconductor device according to a first exemplary embodiment of the present invention. In the present embodiment, a process of applying a plurality of etching barrier layers to a process of defining a gate electrode and forming a highly reliable fine pattern using an isotropic etching layer will be described as an example.

Referring to FIG. 2A, first, a gate insulating film 20 is formed on a silicon substrate 10, a silicon electrode 30 is sequentially formed, and then a first etch barrier layer 40 is formed. As the gate insulating film 20, a silicon nitride film, a silicon oxide film, a silicon nitride film, a high dielectric constant laminated film, a high dielectric constant film, or the like can be used, and various methods such as a thermal deposition method or a CVD / ALD can be formed, and 0.5 to 100 nm is suitable. Do. The role of the first etching barrier layer 40 should be high in etching selectivity during etching of the isotropic trimming layer 50 and the photoresist pattern 60, which are stacked on the upper part in a subsequent process, and isotropic trimming layer 50. ), The etching selectivity should be high when the first etching barrier layer 40 is etched. In addition, when etching the lower silicon electrode 30, the etching selectivity must be very high as an etching mask. In this embodiment, the silicon oxide film and the silicon nitride film are described as examples of the material.

Next, an isotropic trimming layer 50 is formed on the first etching barrier layer 40 at about 10 nm to about 200 nm. The role of the isotropic trimming layer 50 is a layer for controlling the line width after etching by using the photoresist as a mask. Since the line width adjustment step is not affected by the CD change of the PR, the line width can be reliably controlled. Can be.

In addition, when etching the first etching barrier layer 40 using the isotropic trimming layer 50 as a mask, the etching selectivity must be excellent (for example, 40 to 100). Otherwise, an appropriate thickness suitable for the etching selectivity is used. shall. In addition, since the edge edge roughness (LER) is not deteriorated to prevent deterioration of roughness of the interface during isotropic etching, it is necessary to have an amorphous film quality. In this embodiment, an amorphous silicon layer has been described as an example of the isotropic trimming layer 50. The photosensitive film pattern 60 is formed on the isotropic trimming layer 50.

For example, the isotropic trimming layer 50 may use an APF (Advanced Patterning Film), which is an organic film developed by Applied Materials. APF thin films have very high etch selectivity for silicon oxide and polysilicon and are easily removed from the oxygen plasma, eliminating the need for high-temperature phosphate solutions and excellent for 248nm and 193nm photolithography processes. It can be used as an anti-reflective coating film, and it can maintain chemical and mechanical stability even at high temperature above 600 ℃. In addition, it can be used as a hard mask due to the high etching selectivity even under extreme conditions where the photoresist thickness is 100 nm or less, and can be manufactured in AM plasma CVD equipment. This APF thin film is known to enable 50 nm pattern formation when used with a DUV lithography (ArF, λ = 193 nm) process.

Referring to FIG. 2B, a small amount of photoresist etching is performed to improve scum and roughness caused when the photoresist pattern is formed. The photoresist pattern 60 represented by the dotted line becomes the photoresist pattern 60a by photoresist etching.

Referring to FIG. 2C, after completion of the descum process, the first isotropic trimming layer pattern 50a is formed by anisotropically etching the first isotropic trimming layer 50 using the photoresist pattern 60a as a mask. The isotropic trimming layer 50 has an excellent etch selectivity with the lower first etch barrier layer 40, for example, about 10 to 200, preferably about 40 to 200, and is easy to remove. The organic or inorganic film that can be easily etched is not particularly limited, and various kinds are possible. Preferably, the silicon layer is a silicon layer. In particular, an isotropic silicon layer uses an amorphous silicon layer because LER is easily deteriorated due to grain boundry. It is preferable. Preferable film thickness is 10-300 nm.

Referring to FIG. 2D, the first isotropic trimming layer pattern 50a is secondarily isotropically etched using the photoresist pattern 60a as an etch mask. Trimming is mainly implemented in this isotropic etching step. When the isotropic trimming layer 50 is an amorphous silicon layer, etching is preferably performed using a Cl ₂ / O ₂ / HBr chemical gas. As the flow rate of O ₂ decreases in the Cl ₂ / HBr / O ₂ etching gas and the amount of HBr gas increases, the anisotropy increases, the etching rate decreases, and the etching selectivity increases. Increasing O ₂ and decreasing the flow rate of HBr isotropically etched to increase the etch rate but usually decrease the etch selectivity. In some cases, an optimal composition ratio of Cl ₂ / O ₂ / HBr exists, and may be different from the above description. In addition, it can be adjusted according to the process pressure, flow rate, plasma method, etc., and if fine adjustment is required, low etching rate and high etching selectivity are required, and when coarse control and high productivity are required, Cl ₂ / O ₂ gas is used. You can optimize your process. Subsequently, when the photosensitive film pattern 60a is removed using O ₂ plasma, the second isotropic trimming layer pattern 50b is completed.

In the isotropic etching of the amorphous silicon layer, the plasma source is easily isotropically etched as the yield of radicals is increased in the high density plasma generating apparatus capable of separating DC bias and plasma generation. Optimum conditions vary depending on the type of reactor and process conditions, and gas chemistry other than the previous example may be used.

2E to 2G, when the first etching barrier layer 40 is etched using the second isotropic trimming layer pattern 50b as a mask, and subsequently the anisotropic etching of the silicon electrode 30 is performed, the silicon electrode has a reduced line width. The pattern 30a can be obtained. Through such a process, good CD line width control can be ensured.

(Second embodiment)

Hereinafter, a second embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3H. 3A to 3H are flowcharts illustrating a method of patterning a semiconductor device according to a second exemplary embodiment of the present invention. In the case of the second embodiment, it will be described in detail with reference to the difference from the first embodiment for convenience of description.

Referring to FIG. 3A, first, a gate insulating layer 120 is formed on a silicon substrate 110, a silicon electrode 130 is sequentially formed, and then a first etching barrier layer 140 and an isotropic trimming layer 150 are formed. The second etching barrier layer 155 is formed. Compared with the first embodiment, the second etching barrier layer 155 is further formed on the isotropic trimming layer 150.

By stacking the second etching barrier layer 155 on the isotropic trimming layer 150, not only the micro-loading phenomenon can be alleviated, but also the precision of CD control can be improved. In this case, a silicon nitride film or a silicon oxide film may be used as the second etching barrier layer 155, and the second etching barrier layer 155 may be any film material that can be easily removed when the first etching barrier layer 140 is removed. . In this case, the second etching barrier layer 155 is formed on the isotropic trimming layer 150, and then the photoresist pattern 160 is formed on the second etching barrier layer 155.

Referring to FIG. 3B, a small amount of etching of the photoresist pattern 160 is performed. The photoresist pattern 160 represented by the dotted line becomes the photoresist pattern 160a by photoresist etching.

Referring to FIG. 3C, the second etching barrier layer 155 is etched using the photoresist pattern 160a as a mask to form a second etching barrier layer pattern 155a. As such, the aspect ratio of the pattern may be lowered by patterning the second etching barrier layer 155 and then removing the photoresist pattern 160a. In addition, when the isotropic trimming layer 150 is etched, the micro loading phenomenon hardly occurs because the consumption of the etched active species in the first and second etching barrier layers 140 and 155 is very small.

3D and 3E, the first isotropic trimming layer pattern 150a is formed by removing the photoresist pattern 160a and etching the isotropic trimming layer using the second etching barrier layer pattern 155a as an etching mask.

3F to 3H, the second isotropic trimming layer pattern 150b is formed by isotropically etching the trimming layer pattern 150a using the second etching barrier layer pattern 155a as an etching mask. This step is the same as described above in the first embodiment. After removing the second etch barrier layer pattern 155a, the first etch barrier layer 140 is etched using the second isotropic trimming layer pattern 150b as an etch mask to form the first etch barrier layer pattern 140a. Form. Thereafter, when the anisotropic etching of the silicon electrode 130 using the first etching barrier layer pattern 140a as an etching mask, the silicon electrode pattern 130a having a reduced line width may be obtained. Through this process, fine pattern formation can be performed by a method in which the CD line width control property is good and the micro-loading phenomenon is improved.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, it is possible to construct a high-performance device or logic without improving the lithography technology and the exposure equipment, so that it is possible to develop a higher-performance product than can be realized with low cost or current exposure technology, and in the photoresist process Not only can the micro-loading phenomenon, which is a problem, can be alleviated, but it can be applied even when the thickness of the photoresist is thin and the etching resistance is poor.

Claims (9)

In the pattern formation method of a semiconductor device for forming a highly reliable fine pattern of 100nm or less using an excimer laser, (a) forming a first etching barrier layer, an isotropic trimming layer, and a photoresist layer on the target layer to be etched; (b) patterning the photosensitive film; (c) anisotropically etching the isotropic trimming layer using the patterned photoresist as a mask, and subsequently etching until the predetermined line width is obtained by isotropic etching; and (d) removing the remaining photoresist and patterning the first etch barrier layer and the target layer in sequence using the patterned isotropic trimming layer as an etch mask. (a) forming a first etching barrier layer, an isotropic trimming layer, a second etching barrier layer, and a photoresist layer on the target layer to be etched; (b) patterning the photosensitive film; (c) etching the second etch barrier layer using the patterned photoresist as a mask and removing the remaining photoresist; (d) anisotropically etching the isotropic trimming layer using the patterned second etch barrier layer as a mask, and etching until the line width is obtained by isotropic etching; (e) patterning the first etch barrier layer and the target layer in sequence using the isotropic trim layer as an etch mask. The method according to claim 1 or 2, Method of forming patterns of a semiconductor device characterized in that after step (b), to improve the roughness of the photosensitive film and performing etching of O ₂ based plasma in order to remove the scum. The method according to claim 1 or 2, The isotropic trimming layer is a pattern forming method of a semiconductor device, characterized in that the organic or inorganic film capable of isotropic etching. The method of claim 4, wherein The isotropic trimming layer is formed of amorphous silicon, the pattern forming method of a semiconductor device, characterized in that formed in a thickness of 10 to 300nm. The method of claim 5, wherein The isotropic etching of the amorphous silicon layer is performed using a Cl ₂ / O ₂ / HBr chemical gas pattern forming method of a semiconductor device.  The method according to claim 1 or 2, The first etching barrier layer is a pattern of forming a semiconductor device, characterized in that to deposit a silicon nitride film or silicon oxide film thickness of 2nm ~ 100nm.  The method of claim 2, And the second etching barrier layer is a silicon nitride film or a silicon oxide film. The method according to claim 1 or 2, The target layer is a pattern forming method of a semiconductor device, characterized in that the double layer of the gate metal and the gate insulating film.

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