CN104064474B - The fin structure manufacture method of Dual graphing fin transistor - Google Patents
The fin structure manufacture method of Dual graphing fin transistor Download PDFInfo
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- CN104064474B CN104064474B CN201410339109.8A CN201410339109A CN104064474B CN 104064474 B CN104064474 B CN 104064474B CN 201410339109 A CN201410339109 A CN 201410339109A CN 104064474 B CN104064474 B CN 104064474B
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000009977 dual effect Effects 0.000 title claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 89
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 61
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 49
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims description 42
- 235000012239 silicon dioxide Nutrition 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000001312 dry etching Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000003384 imaging method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 168
- 239000012792 core layer Substances 0.000 description 13
- 239000007789 gas Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a kind of fin structure manufacture method of Dual graphing fin transistor; the second silicon nitride layer is protected using silica is deposited; the thickness loss of the second silicon nitride layer will not be caused when then removing nitrogen-free anti-reflecting layer at the top of the second amorphous carbon layer; avoid pattern caused by existing method and critical size control problem; so as to expand subsequent patterning process window; the control of the critical size and pattern of fin structure is more beneficial for, realizes the raising of device electric property index.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process technology field, more particularly to one kind are double using side wall autoregistration
The manufacture method of the fin structure of the graphical fin transistor of weight.
Background technology
Predicted according to international semiconductor technology path development blueprint, in order to follow Moore's Law and obtain required short ditch
Channel effect, improve the control to raceway groove of grid, it is proposed that new transistor arrangement, i.e. fin formula field effect transistor FinFET
(Fin Field Effect Transistor, abbreviation fin transistor).The formation of its active area fin is a great challenge
The technique of property, because in 22nm and following fin formula field effect transistor, the width of fin is so small about in 10~15nm or so
Dimension of picture has exceeded the resolution limit of current immersed photoetching machine, for this reason, it may be necessary to using side wall self-alignment type double picture
Shape technology is realized.I.e. first on the silicon chip that deposited various mask materials, liquid immersion lithography and etching skill are utilized
Art produces the core graphic (sacrificial core pattern) of a sacrifice, and atom is then utilized on this core graphic
Layer deposition techniques, one layer of spacer material is deposited, then side wall is formed using anisotropic dry etch, afterwards by the core of sacrifice
Figure removes, material is thus formed fin (FIN) mask graph that required pitch (pitch) halves, FIN hard masks here
Width be to be determined by the thickness of atomic deposition layer, be afterwards that protective layer continues etching and forms fin using this hard mask figure
The fin (FIN) of field-effect transistor.
Figure 1A to Fig. 1 H is the existing forming method using side wall self-alignment duplex pattern fin.Specifically：
First, as shown in Figure 1A, on the silicon substrate 101 of a semiconductor active device, two are deposited successively from bottom to top
Insulating layer of silicon oxide 102, silicon nitride layer 103, first layer amorphous carbon layer 104, silicon nitride etch stop layer 105, second layer amorphous
Carbon-coating 106 and nitrogen-free anti-reflecting layer 107.Wherein, silicon nitride layer 103 is the etch hardmask that final fin structure is formed.
Then, as shown in Figure 1B, in 107 layers of spun on top organic antireflection layer 108 and photoresist 109, then carry out
Carry out core layer (core layer) photoetching.
Then, as shown in Figure 1 C, etch to form the sacrificial of the second amorphous carbon layer 106 by the use of photoresist 109 as mask dry
Domestic animal core layer bargraphs, so far form amorphous carbon and sacrifice core graphic and its nitrogen-free anti-reflecting layer 107 at top.Shape herein
Into amorphous carbon sacrifice core pattern line because technique limitation can not form vertical sidewall profile, and close completely
There may be damaged caused by etching at the top of the second amorphous carbon layer 106 in the figure；This damage can cause follow-up side wall every
Change from pattern of the hard mask close to amorphous carbon one side, so as to influence follow-up graphic definition.
After corresponding cleaning, as shown in figure iD, core graphic and nitrogen-free anti-reflecting layer 107 are sacrificed in amorphous carbon
Top deposits one layer of silicon oxide film hard mask layer 110.
As referring to figure 1E, using the anisotropic dry etch silicon oxide film hard mask layer, and silicon nitride quarter is stopped at
The top of stop-layer 105 is lost to form monox lateral wall 110.
Afterwards, as shown in fig. 1F, removed and sacrificed at the top of core layer bargraphs using plasma dry etch process
Nitrogen-free anti-reflecting layer 107 so that the sacrifice core layer amorphous carbon of the lower section of nitrogen-free anti-reflecting layer 107 is exposed.In this step,
Because etching stop layer 105a is also exposed in plasma during removal nitrogen-free anti-reflecting layer 107 so that etching stop layer
105a has loss in this step.
As shown in Figure 1 G, removed with dry method degumming process and sacrifice core layer so that etching stop layer 105b below is sudden and violent
Expose.Now, etching stop layer 105a and 105b causes both thickness also by exposure to the time difference in plasma
Differ, the film thickness at etching stop layer 105a continues to be thinned, and the film thickness at etching stop layer 105b is still kept
Constant, both further amplify at difference in thickness, can cause after carrying out figure transmission using the hard mask lines of monox lateral wall 110,
The further amplification of varying topography inside and outside final side wall.
As shown in fig. 1H, dry etching is continued with using the hard mask of silicon dioxide side wall 110 as mask, is removed below
The silicon nitride layer 103 of silicon nitride etch stop layer 105, the first amorphous carbon layer 104 and bottommost, form the nitridation that pitch halves
The bargraphs of silicon hard mask 113, and etching stopping is above silicon dioxide insulating layer 102.
After completing necessary wet clean process, as shown in Figure 1 I, fin line top cut-out photoetching process is carried out, that is, is existed
The top spin coating photoetching flatness layer 114 of silicon nitride hard mask 113, photoetching anti-reflecting layer 115 and photoresist layer 116, and expose, show
Shadow forms the figure for needing to cut off.
As shown in figure iJ, it is with photoresist 116, photoetching anti-reflecting layer 115 and flatness layer 114 using dry etch process
Mask removes the silicon nitride lines for needing to cut off, and etching stopping is on silicon dioxide insulating layer 102.Removed photoresist afterwards using dry method
Technique removes the amorphous carbon hard mask of the top of silicon nitride hard mask 113, is fully exposed 113 layers of silicon nitride hard mask.
Afterwards, as shown in Fig. 1 K and Fig. 1 L, hard mask, etching silicon dioxide insulation are used as by the use of silicon nitride hard mask 113
Layer 102 and silicon substrate 101 are to form fin structure 117.
In summary, it is existing to be formed in the method for fin structure, there is following defect：
1. in core graphic APF etching processes are sacrificed, it is (close that core layer pattern is hardly formed the very high lines of perpendicularity
90 degree), because if core layer pattern side wall perpendicularity not enough can directly cause the madial wall of follow-up side wall hard mask along this core
Central layer sidewall shape forms an inclined angle (being less than 90 degree), while the side wall shape of an inverted trapezoidal is formed on the inside of side wall
Looks, this can cause in follow-up figure transmission, influence the control of the pattern of subsequent diagram and the critical size of subsequent diagram, such as
Inclined silicon nitride hard mask lines in Fig. 1 H.And fin shape and critical size are for the electrical property of fin formula field effect transistor
The definition of energy is most important.
2., it is necessary to remove this sacrifice core layer figure after monox lateral wall dry etching is completed, and this general sacrificial core
Due to patterned needs above central layer, there is one layer of nitrogen-free anti-reflecting layer (NFDARC) at the top of it, it is therefore, sacrificial in order to remove
Domestic animal core layer APF needs first to remove the nitrogen-free anti-reflecting layer at the top of it, while caused side wall hard mask figure can not be produced
Raw any negative effect, and the substrate film to being exposed produces minimum damage；If walked in side wall dry etching
Directly apply an over etching (OE) after rapid to remove nitrogen-free anti-reflecting layer, the loss of lower dielectric on the outside of side wall can be caused, led
After causing core layer to remove, the thickness of the dielectric substrate material below core layer origin-location did not had originally much larger than side wall outer lower side
By core layer covering position thickness, therefore, can cause when down carrying out figure transmission as mask using side wall pattern with
Critical size control problem, while it is also possible to be damaged to the height of side wall pattern or side wall.
The content of the invention
It is an object of the invention to make up above-mentioned the deficiencies in the prior art, there is provided a kind of Dual graphing fin transistor
Fin structure manufacture method, to avoid the loss of the etching stop layer when removing nitrogen-free anti-reflecting layer, and reduce due to sacrificial core
Influence of the central layer sidewall slope to subsequent diagram, so as to control the pattern of fin structure and critical size, improve the electrical property of device
Can index.
To achieve the above object, the present invention provides a kind of fin structure manufacture method of Dual graphing fin transistor, its
Comprise the following steps：
Step S01, there is provided semiconductor device substrate, and deposit the first silica successively from bottom to top over the substrate
Layer, the first silicon nitride layer, the first amorphous carbon layer, the second silicon nitride layer, the second amorphous carbon layer and anti-reflecting layer；
Step S02, the coating photoresist on top layer anti-reflecting layer, by exposure imaging technique, complete core sacrifice layer figure
Shape lithography step；
Step S03, using photoresist as mask etching anti-reflecting layer and the second amorphous carbon layer, formation has the second amorphous carbon
The core of layer and its top anti-reflective layer sacrifices layer pattern；
Step S04, sacrificed in the core and one layer of second silicon dioxide layer is deposited above layer pattern；
Step S05, etching removes the second silicon dioxide layer at the top of core sacrifice layer pattern, to expose the antireflection
Layer, and retain the second silicon dioxide layer that core sacrifices layer pattern both sides；
Step S06, etching remove the anti-reflecting layer at the top of core sacrifice layer pattern；
Step S07, etching remove second silicon dioxide layer；
Step S08, sacrificed in the core and one layer of the 3rd silicon dioxide layer is deposited above layer pattern；
Step S09, using the silicon dioxide layer of anisotropic etching the 3rd, expose that core is sacrificed in layer pattern second is non-
Brilliant carbon-coating, the silicon dioxide side wall that core sacrifices layer pattern is formed, afterwards, remove the second amorphous carbon in core sacrifice layer pattern
Layer；
Step S10, using the silicon dioxide side wall as mask etching second silicon nitride layer, the first amorphous carbon layer and
One silicon nitride layer, form bottom and be the hard mask lines of silicon nitride, and remove in the hard mask lines above the first silicon nitride layer
The first amorphous carbon layer；
Step S11, using the silicon nitride lines that the first silicon nitride layer in the hard mask lines is formed as mask etching this
One silicon dioxide layer and substrate, form fin structure.
Further, step S03 is dry etching, and step S05 is reversely to etch (etch using plasma dry
Back), step S06 is dry etching, and step S07 is wet etching, formed in step S09 silicon dioxide side wall be using it is each to
The plasma dry etch of the opposite sex, it be degumming process that core is removed in step S09 to sacrifice the second amorphous carbon layer in layer pattern, is walked
It is to utilize anisotropic plasma dry etch that hard mask lines are formed in rapid S10, and the second hard mask is removed in step S10
Amorphous carbon is degumming process above silicon nitride in lines, and step S11 is dry etching.
Further, step S06 also includes over etching, to remove the amorphous carbon layer of part second below anti-reflecting layer.
Further, the anti-reflecting layer includes lower floor's nitrogen-free anti-reflecting layer and upper strata anti-reflecting layer.
Further, step S04 is the silicon dioxide layer of spin coating second.
Further, step S05 etching gas medium is CF4Or CF4With Ar mixed gas.
Further, the CF4Flow be 50sccm~200sccm, the flow of the Ar is 50sccm~300sccm, is penetrated
Frequency source power is 200 watts~700 watts, is biased as 50 volts~400 volts, and air pressure is the millitorr of 5 millitorrs~12.
Further, the silicon nitride lines pitch in step S10 in hard mask lines halves.
Further, also include between step S10 and S11, step S101, it is hard to be coated with carbon successively on the silicon nitride lines
Mask layer, siliceous anti-reflecting layer and photoresist, by exposure imaging technique, the figure to be cut off is produced on a photoresist
Shape；Step S102, the silicon nitride lines for needing to cut off are removed using dry etching, and residual nitrogen is removed using dry method degumming process
Amorphous carbon above SiClx lines, expose silicon nitride lines.
Further, the anti-reflecting layer is nitrogen-free anti-reflecting layer.
The fin structure manufacture method of Dual graphing fin transistor provided by the invention, due to make use of deposit titanium dioxide
Silicon protects the second silicon nitride layer so that will not cause the second nitridation when removing nitrogen-free anti-reflecting layer at the top of the second amorphous carbon layer
The thickness loss of silicon layer, pattern caused by existing method and critical size control problem are avoided, so as to expand subsequent figure
Shape process window, the control of the critical size and pattern of fin structure is more beneficial for, realizes carrying for device electric property index
It is high.
Brief description of the drawings
For that can become apparent from understanding purpose, feature and advantage of the present invention, the preferable reality below with reference to accompanying drawing to the present invention
Example is applied to be described in detail, wherein：
Figure 1A-Fig. 1 L are each step schematic diagrams of existing double-pattern fin forming method；
Fig. 2 is the schematic flow sheet of the fin structure manufacture method of Dual graphing fin transistor of the present invention；
Fig. 3 A- Fig. 3 N are each step schematic diagrams of manufacture method of the present invention.
Embodiment
Please refer to Fig. 2, Fig. 3 A to Fig. 3 N, the fin structure manufacturer of the Dual graphing fin transistor of the present embodiment
Method, comprise the following steps：
Step S01, as shown in Figure 3A, there is provided semiconductor device substrate 201, and on the substrate 201 from bottom to top according to
The first silicon dioxide layer 202 of secondary deposit, the first silicon nitride layer 203, the first amorphous carbon layer 204, the second silicon nitride layer 205, second
Amorphous carbon layer 206 and nitrogen-free anti-reflecting layer 207.
Step S02, as shown in Figure 3 B, organic antireflection layer 208 is deposited on top layer nitrogen-free anti-reflecting layer 207, and having
Coating photoresist 209 on machine anti-reflecting layer 208, by exposure imaging technique, it is sacrificial that core to be prepared is produced on photoresist 209
The figure of domestic animal layer, complete core and sacrifice layer pattern lithography step.
Step S03, it is mask etching organic antireflection layer 208, nitrogen-free anti-reflecting layer with photoresist 209 as shown in Figure 3 C
207 and second amorphous carbon layer 206, ultimately form the core with the second amorphous carbon layer 206 and its top nitrogen-free anti-reflecting layer 207
The heart sacrifices layer pattern.
Wherein, this step is dry etching, can use this area conventional meanses, gas medium.
Step S04, as shown in Figure 3 D, sacrifice one layer of second silicon dioxide layer 210 of spin coating on layer pattern in core.This second
The thickness of silicon dioxide layer 210 just over the top of nitrogen-free anti-reflecting layer 207 to be preferred.
Step S05, as shown in FIGURE 3 E, etching remove the second silicon dioxide layer 210 at the top of core sacrifice layer pattern, with dew
Go out nitrogen-free anti-reflecting layer 207, and retain the second silicon dioxide layer 210 that core sacrifices layer pattern both sides.
Wherein, this step is reversely etches using plasma dry, the preferred CF of etching gas4Or CF4With Ar mixing
Gas, wherein, CF4Flow be 50sccm~200sccm, Ar flow is 50sccm~300sccm, and RF source power is
200 watts~700 watts, bias as 50 volts~400 volts, air pressure is the millitorr of 5 millitorrs~12.
Step S06, as illustrated in Figure 3 F, etching remove the nitrogen-free anti-reflecting layer 207 at the top of core sacrifice layer pattern.
Wherein, this step is dry etching, can use this area conventional meanses, gas.Wherein, step S06 is also preferably
Including over etching, to remove the amorphous carbon layer of part second below anti-reflecting layer.The second amorphous carbon layer atop part is removed because carving
Damaging layer caused by erosion, play a part of adjusting the second amorphous carbon layer height, expand its top critical size, avoid because vertical
Degree not enough causes the influence that critical size is too small at the top of it, is more beneficial for the transmission of subsequent diagram.
Step S07, as shown in Figure 3 G, etching remove the second silicon dioxide layer 210 of spin coating.
Wherein, this step is wet etching, can use this area conventional meanses, medium.This step is gone using wet etching
Except remaining spin-on silicon dioxide, higher etching selection ratio can be kept, core will not be caused to sacrifice second non-in layer pattern
Brilliant carbon-coating 206 and core sacrifice the loss of the second silicon nitride layer of layer pattern both sides 205, to ensure the pattern of subsequent diagram and pass
Key size.
Step S08, as shown in figure 3h, sacrificed in core and one layer of the 3rd silicon dioxide layer 211 is deposited above layer pattern.
Step S09, as shown in fig. 31, using the silicon dioxide layer 211 of anisotropic etching the 3rd, expose core sacrifice layer figure
The second amorphous carbon layer of shape 206, and the silicon dioxide side wall 218 that core sacrifices layer pattern is formed, afterwards, remove core sacrifice layer figure
The second amorphous carbon layer 206 in shape, that is, whole core are sacrificed layer pattern and are removed.
Wherein, it is to utilize anisotropic plasma dry etch that silicon dioxide side wall is formed in this step, can be used
This area conventional meanses, gas；It is degumming process to remove the second amorphous carbon layer of core sacrifice layer figure, can use this area routine hand
Section, gas medium.
Step S10, it is that the second silicon nitride layer of mask etching 205, first is non-with silicon dioxide side wall 218 as shown in figure 3j
The brilliant silicon nitride layer 203 of carbon-coating 204 and first, the hard mask lines that bottom is silicon nitride, silicon nitride top is amorphous carbon are formed,
And remove the first amorphous carbon layer in hard mask lines above the first silicon nitride layer.
Wherein, it is to utilize anisotropic plasma dry etch that hard mask lines are formed in this step, can use this
Field conventional meanses, gas；It is degumming process to remove silicon nitride top amorphous carbon in hard mask lines, and this area can be used conventional
Means, gas.
Wherein, the silicon nitride lines pitch in the hard mask lines formed after the completion of this step halves.
Step S11, as shown in fig.3m, the silicon nitride lines formed using the first silicon nitride layer in hard mask lines is masks
Etch the first silicon dioxide layer 202 and silicon substrate 201, form fin structure, two side walls 216 of the silicon groove 215 of the fin structure,
217 is symmetrical, and critical size is uniform.
Wherein, this step is dry etching, can use this area conventional meanses, gas.
In actual applications, it is necessary to carry out top Cutting process to fin line, also include between step S10 and S11, step
S101, as shown in Fig. 3 K, it is coated with carbon hard mask layer 212, siliceous anti-successively on the silicon nitride lines that the first silicon nitride layer is formed
Reflecting layer 213 and photoresist 214, by exposure imaging technique, the figure to be cut off is produced on photoresist 214；Step
Rapid S102, as shown in figure 3l, the silicon nitride lines for needing the first silicon nitride layer cut off to be formed, and profit are removed using dry etching
The amorphous carbon above remaining silicon nitride lines is removed with dry method degumming process, exposes silicon nitride lines.What final step S09 was formed
Fin structure is as shown in Fig. 3 N.
Claims (9)
1. a kind of fin structure manufacture method of Dual graphing fin transistor, it is characterised in that it comprises the following steps：
Step S01, there is provided semiconductor device substrate, and deposit successively from bottom to top over the substrate the first silicon dioxide layer,
First silicon nitride layer, the first amorphous carbon layer, the second silicon nitride layer, the second amorphous carbon layer and anti-reflecting layer；
Step S02, the coating photoresist on top layer anti-reflecting layer, by exposure imaging technique, complete core and sacrifice layer pattern light
Carve step；
Step S03, using photoresist as mask etching anti-reflecting layer and the second amorphous carbon layer, formed with the second amorphous carbon layer and
The core of its top anti-reflective layer sacrifices layer pattern；
Step S04, sacrificed in the core and one layer of second silicon dioxide layer is deposited above layer pattern；
Step S05, etching remove the second silicon dioxide layer at the top of core sacrifice layer pattern, to expose anti-reflecting layer, and protected
Core is stayed to sacrifice the second silicon dioxide layer of layer pattern both sides；
Step S06, etching remove the anti-reflecting layer at the top of core sacrifice layer pattern；
Step S07, etching remove second silicon dioxide layer；
Step S08, sacrificed in the core and one layer of the 3rd silicon dioxide layer is deposited above layer pattern；
Step S09, using the silicon dioxide layer of anisotropic etching the 3rd, expose the second amorphous carbon in core sacrifice layer pattern
Layer, the silicon dioxide side wall that core sacrifices layer pattern is formed, afterwards, remove the second amorphous carbon layer in core sacrifice layer pattern；
Step S10, using the silicon dioxide side wall as mask etching second silicon nitride layer, the first amorphous carbon layer and the first nitridation
Silicon layer, form bottom and be the hard mask lines of silicon nitride, and remove in the hard mask lines first above the first silicon nitride layer
Amorphous carbon layer；
Step S11, the silicon nitride lines formed using the first silicon nitride layer in the hard mask lines is mask etchings the one or two
Silicon oxide layer and substrate, form fin structure.
2. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterised in that：Step
S03 is dry etching, and for step S05 reversely to be etched using plasma dry, step S06 is dry etching, and step S07 is wet
Method etches, and it is to utilize anisotropic plasma dry etch that silicon dioxide side wall is formed in step S09, in step S09
It is degumming process to sacrifice the second amorphous carbon layer in layer pattern except core, formed in step S10 hard mask lines for utilization it is each to
The plasma dry etch of the opposite sex, removes in the second hard mask lines that amorphous carbon is work of removing photoresist above silicon nitride in step S10
Skill, step S11 are dry etching.
3. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：Step
S06 also includes over etching, to remove the amorphous carbon layer of part second below anti-reflecting layer.
4. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：This is anti-
Reflecting layer includes lower floor's nitrogen-free anti-reflecting layer and upper strata organic antireflection layer, and step S03 core, which is sacrificed at the top of layer pattern, is
Nitrogen-free anti-reflecting layer.
5. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：Step
S04 is the silicon dioxide layer of spin coating second.
6. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterised in that：Step
S05 etching gas medium is CF4Or CF4With Ar mixed gas.
7. the fin structure manufacture method of Dual graphing fin transistor according to claim 6, it is characterised in that：The CF4
Flow be 50sccm~200sccm, the flow of the Ar is 50sccm~300sccm, and RF source power is 200 watts~700 watts,
Bias as 50 volts~400 volts, air pressure is the millitorr of 5 millitorrs~12.
8. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterised in that：Step
Silicon nitride lines pitch in S10 in hard mask lines halves.
9. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterised in that：Step
Also include between S10 and S11, step S101, carbon hard mask is coated with successively on the silicon nitride lines that the first silicon nitride layer is formed
Layer, siliceous anti-reflecting layer and photoresist, by exposure imaging technique, produce the figure to be cut off on a photoresist；Step
Rapid S102, the silicon nitride lines for needing the first silicon nitride layer cut off to be formed are removed using dry etching, and removed photoresist using dry method
Technique removes the amorphous carbon above remaining silicon nitride lines, exposes silicon nitride lines.
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