KR20100004705A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

Info

Publication number
KR20100004705A
KR20100004705A KR1020080065023A KR20080065023A KR20100004705A KR 20100004705 A KR20100004705 A KR 20100004705A KR 1020080065023 A KR1020080065023 A KR 1020080065023A KR 20080065023 A KR20080065023 A KR 20080065023A KR 20100004705 A KR20100004705 A KR 20100004705A
Authority
KR
South Korea
Prior art keywords
layer
etching
amorphous carbon
pattern
buffer layer
Prior art date
Application number
KR1020080065023A
Other languages
Korean (ko)
Inventor
정진기
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080065023A priority Critical patent/KR20100004705A/en
Publication of KR20100004705A publication Critical patent/KR20100004705A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can remove the particle source during the self-aligned contact etching using the SPT process, the present invention is an etching layer, a first amorphous carbon on a substrate having a cell region and a peripheral region Stacking a layer, a hard mask layer and a buffer layer; Forming a second amorphous carbon pattern on the buffer layer; Forming a spacer on sidewalls of the second amorphous carbon pattern; Removing the second amorphous carbon pattern; Selectively etching the buffer layer of the cell region; Removing the spacers; Etching the hard mask layer using the buffer layer as an etch barrier; Removing the buffer layer; Etching the first amorphous carbon layer using the hard mask layer as an etch barrier; Removing the hard mask layer; And forming a pattern by etching the etched layer, and sequentially removing the upper layer during the etching of the lower layer, thereby preventing the problem of acting as a lifting shape or a particle source of the upper etch barriers at the time when the pattern is completed. By forming a hard mask with a material and a thickness that can be removed during self-aligned contact etching, there is an effect of preventing the problem of remaining as a particle source in a subsequent process.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device manufacturing method using a SPT (Spacer Patterning Technology) process.

The line width of the pattern is narrowed due to the high integration of the device, and in particular, it is difficult to pattern only the photoresist film due to the limitation of resolution of the exposure equipment at 40 nm or less.

In order to solve this problem, a DPT (Double Patterning Technology) process is applied, and in particular, a SPT (Spacer Patterning Technology) process using a spacer is applied.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a first amorphous carbon film 12, a first silicon oxynitride film 13, a polysilicon film 14, and a second amorphous carbon film 15 are formed on an etched layer 11 of an oxide film. And a second silicon oxynitride film 16 are stacked.

Subsequently, a photosensitive film pattern 17 is formed on the second silicon oxynitride film 16.

As shown in FIG. 1B, the second silicon oxynitride film 16 and the second amorphous carbon film 15A are etched using the photoresist pattern 17 as an etching barrier.

Next, an insulating film 18 is formed along the step on the entire structure including the second amorphous carbon film 15A. The insulating film 18 is for forming subsequent spacers, and may be formed of a nitride film.

As illustrated in FIG. 1C, the insulating layer 18 is etched to form spacers 18A on sidewalls of the second amorphous carbon film 15A (see FIG. 1B).

Next, the second amorphous carbon film 15 is removed.

Subsequently, the first silicon oxide fine oxide film 13A and the first amorphous carbon film 12A are etched using the spacer 18A as an etch barrier.

As described above, the prior art applies the SPT process to define a micro pattern that is difficult to define only by the photoresist pattern 17, and for this purpose, the first amorphous carbon film 12A and the first silicon oxynitride film on the etched layer 11. (13A) up to five layers of the polysilicon film 14A, the second amorphous carbon film 15A, and the second silicon oxynitride film 16A and the photosensitive film pattern 17 formed on the second silicon oxynitride film 16A. A total of six layers are formed. In addition, the spacer 18A is formed on the sidewall of the second amorphous carbon film 15A after the etching of the second amorphous carbon film 15A.

However, when the Self Aligned Contact Etch is performed using the films, the first amorphous carbon film 12A, the first silicon oxynitride film 13A, and the polysilicon film have a selectivity with respect to the oxide film. 14A and the spacer 18A are not lost and remain as they are. Accordingly, the first amorphous carbon film 12A, the first silicon oxynitride film 13A, the polysilicon film 14A, and the spacer are removed while the first amorphous carbon film 12A is removed in the strip process of the photoresist pattern used for self-aligned contact etching in a subsequent process. There is a problem that 18A falls down and functions as a particle source.

In addition, in the process of removing the nitride film spacer 18A, there is a problem in that the lifting of the upper polysilicon film 14A occurs while the first silicon oxynitride film 13A including the nitride film is removed. If the spacer 18A of the nitride film is not removed, unwanted etching may occur due to the spacer 18A formed on the peripheral region side.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device capable of removing particle sources during self-aligned contact etching using an SPT process.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of laminating an etching layer, a first amorphous carbon layer, a hard mask layer and a buffer layer on a substrate having a cell region and a peripheral region; Forming a second amorphous carbon pattern on the buffer layer; Forming a spacer on sidewalls of the second amorphous carbon pattern; Removing the second amorphous carbon pattern; Selectively etching the buffer layer of the cell region; Removing the spacers; Etching the hard mask layer using the buffer layer as an etch barrier; Removing the buffer layer; Etching the first amorphous carbon layer using the hard mask layer as an etch barrier; Removing the hard mask layer; And etching the etched layer to form a pattern.

In particular, the etched layer is characterized in that it comprises an oxide film.

In addition, the hard mask layer is characterized in that it comprises polysilicon.

In addition, the buffer layer is characterized in that it comprises an oxide film.

In addition, the spacer is characterized in that it comprises a nitride film.

In addition, the step of removing the spacer, characterized in that to proceed in the wet etching or dry etching.

In addition, the wet etching is characterized in that it proceeds using a solution containing phosphoric acid (H 3 PO 4 ).

In addition, the dry etching may be performed using a gas containing fluorine gas.

In addition, the dry etching may be performed without applying bias power.

The dry etching may be performed by applying a bias power of 1 kPa to 50 kPa.

In addition, the removing of the buffer layer may be performed by wet etching.

In addition, the wet etching is characterized in that the progress using HF or BOE (Buffered Oxide Etchant).

The pattern may also include a landing plug contact or a storage node contact.

Stacking an etched layer, a first amorphous carbon layer, a hard mask layer, and a buffer layer on a substrate having a cell region and a peripheral region according to a second embodiment of the present invention for achieving the above object; Forming a second amorphous carbon pattern on the buffer layer; Forming a spacer on sidewalls of the second amorphous carbon pattern; Removing the second amorphous carbon pattern; Selectively etching the buffer layer of the cell region; Removing the spacers; Etching the hard mask layer and the first amorphous carbon layer using the buffer layer as an etch barrier; And forming a pattern by performing self-aligned contact etching on the etched layer.

In particular, the etched layer is characterized in that it comprises an oxide film.

In addition, the polysilicon is included and has a thickness of 50 kPa to 300 kPa.

In addition, the buffer layer is formed of the same material as the layer to be etched, characterized in that it comprises an oxide film.

In addition, the spacer is characterized in that it comprises a nitride film.

In addition, the step of removing the spacer, characterized in that to proceed in the wet etching or dry etching.

In addition, the wet etching is characterized in that it proceeds using a solution containing phosphoric acid (H 3 PO 4 ).

In addition, the dry etching may be performed using a gas containing fluorine gas.

In addition, the dry etching may be performed without applying bias power.

The dry etching may be performed by applying a bias power of 1 kPa to 50 kPa.

The semiconductor device manufacturing method of the present invention described above has an effect of preventing the problem of acting as a particle source or a lifting phenomenon of the upper etching barriers at the time when the formation of the pattern is completed by sequentially removing the upper layer during the lower layer etching.

In addition, by forming a hard mask with a material and a thickness that can be removed during self-aligned contact etching, there is an effect of preventing the problem of remaining as a particle source in a subsequent process.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

The present invention relates to a method for manufacturing a semiconductor device using a SPT (Spacer Patterning Technology) process, in order to solve the problem that the film used as a hard mask in the SPT process remains as a particle source in the subsequent process, during the SPT process All the films used as masks are removed, and the lower layer is not affected by the subsequent photoresist pattern or spacer removal process, which will be described in detail with reference to FIGS. 2A to 2H.

(Example 1)

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, an etched layer 21 is formed on a semiconductor substrate (not shown) provided with a cell region and a peripheral region. In this case, the etched layer 21 may be an insulating film, and the insulating film may include an oxide film.

Subsequently, a first amorphous carbon layer 22, a hard mask layer 23, a buffer layer 24, a second amorphous carbon layer 25 and an antireflection layer 26 are stacked on the etched layer 21.

The first amorphous carbon layer 22 is used as a hard mask for etching the etched layer 21.

The hard mask layer 23 is intended to be used as a hard mask for improving the adhesion between the first amorphous carbon layer 22 and the subsequent layer and for etching the first amorphous carbon layer 22. The hard mask layer 23 may be formed of a material that is not damaged during a subsequent spacer removing process, and may include, for example, polysilicon.

The buffer layer 24 is formed of a material having a high selectivity upon subsequent spacer etching and a material that is not damaged when the spacer is removed. The buffer layer 24 may be formed of the same material as the layer to be etched. The buffer layer 24 may be formed of, for example, an oxide film.

The second amorphous carbon layer 25 is intended to be used as a sacrificial layer for forming subsequent spacers.

The anti-reflection film 26 serves as a hard mask for etching the second amorphous carbon layer 25, prevents the footing phenomenon between the second amorphous carbon layer 25 and the subsequent photoresist pattern, and plays an antireflection role when the photoresist pattern is formed. It is to. The antireflection film 26 may include, for example, a silicon oxynitride film 26.

Subsequently, a first photosensitive film pattern 27 is formed on the antireflection film 26. The first photoresist layer pattern 27 may be formed by coating a photoresist layer on the antireflection layer 26 and patterning the photoresist layer by exposure and development. The first photoresist layer pattern 27 is used to define a sacrificial layer pattern necessary for forming a spacer for a subsequent SPT process. The line width between the patterns may be wide to secure an exposure margin. In addition, the first photoresist layer pattern 27 may be formed in a line / spacer shape, and the ratio of line line width: spacer line width is 1: 2.5 to 3.5 in consideration of the final critical dimension target after final patterning. can do.

As shown in FIG. 2B, the anti-reflection film 26 (see FIG. 2A) is etched using the first photoresist pattern 27 (see FIG. 2A) as an etching barrier.

Subsequently, the second amorphous carbon layer 25 (see FIG. 2A) is etched using the first photoresist layer pattern 27 and the etched anti-reflection layer 26 as etch barriers. When the etching of the second amorphous carbon layer 25 is completed, all of the first photoresist layer pattern 27 may be lost, and all of the anti-reflection layer 26 may be lost, or may be partially remaining.

Thus, a second amorphous carbon pattern 25A having the same line width and spacing between the patterns as the first photoresist pattern 27 is formed.

Subsequently, an insulating film 28 for spacers is formed along the step on the entire structure including the second amorphous carbon pattern 25A. The spacer insulating film 28 is for forming a spacer for the SPT process, and may be formed of a material having a selectivity with respect to the buffer layer 24 of the oxide film quality. For example, the spacer insulating film 28 may include a nitride film. In addition, it is formed to have a high step coverage (Step coverage) to form a pattern of a uniform line width.

As illustrated in FIG. 2C, the spacer insulating layer 28 (see FIG. 2B) is etched to form the spacer 28A on the sidewall of the second amorphous carbon pattern 25A.

The spacer insulating layer 28 may proceed with full etching. The front surface etching proceeds to a target in which the upper portion of the second amorphous carbon pattern 25A and the buffer layer 24 are opened. In the case where the buffer layer 24 is an oxide film, the front surface etching increases the selectivity between the oxide film and the nitride film so that the spacer insulating film 28 is selectively etched without loss of the buffer layer 24. To this end, the front surface etching may be performed using a plasma of a gas combination containing CH 2 F 2 or CH 3 F.

As shown in FIG. 2D, the second amorphous carbon pattern 25A is removed. The second amorphous carbon pattern 25A may be removed using an oxygen plasma.

Accordingly, spacers 28A spaced apart from each other at predetermined intervals remain on the buffer layer 24.

As shown in FIG. 2E, the buffer layer 24 (see FIG. 2D) of the cell region is selectively etched. To this end, a second photoresist pattern 29 is formed on the entire structure including the spacer 28A and the buffer layer 24 to open the cell region.

The second photoresist layer pattern 29 is formed so that the peripheral region is protected so as to selectively etch only the cell region. To this end, the photoresist is coated to a thickness thicker than the height of the spacer 28A on the entire structure including the spacer 28A, and patterned so that the cell region is opened by exposure and development. The two photoresist pattern 29 may be formed.

The second photoresist pattern 29 that opens the cell region and covers the peripheral region is shown in FIG. 4.

4 is a plan view of a photoresist pattern in self-aligned contact etching.

As illustrated in FIG. 4, the photoresist pattern covering the peripheral area B may be identified while the cell area is opened based on the boundary A on the spacer formed in the line type.

Subsequently, the buffer layer 24A is etched using the spacer 28A and the second photoresist pattern 29 as an etch barrier. At this time, etching is performed under the condition that only the buffer layer 24A, which is an oxide film, is selectively etched.

As shown in FIG. 2F, the second photoresist layer pattern 29 (see FIG. 2E) is removed. The second photoresist layer pattern 29 may be removed by dry etching. Dry etching may, for example, proceed to an oxygen strip process.

Next, the spacer 28A (see FIG. 2E) is removed. The spacer 28A may be removed by dry or wet etching, and the removing process may be performed under the condition that the lower buffer layer 24A and the hard mask layer 23 are not lost.

When the spacer 28A is a nitride film, the buffer layer 24A is an oxide film, and the hard mask layer 23 (see FIG. 2E) is polysilicon, the removal process of the spacer 28A using wet etching is performed using phosphoric acid (H 3 PO 4). Can proceed to a solution containing).

In addition, the removal process of the spacer 28A using dry etching can be performed using the plasma of the gas combination containing fluorine (F). The fluorine-containing gas combination may include, for example, a mixed gas of CHF 3 , SF 6 and CF 4 . In the removal process of the spacer 28A using dry etching, a bias power toward a substrate (not shown) may be applied or may be applied in a range of 1 kV to 50 kV. In addition, the temperature of a board | substrate can be kept at least 50 degrees C or less (normal temperature-50 degreeC).

Top view after removing spacer 28A is shown in FIG. 5.

5 is a top view showing a pattern after removing the spacer.

As shown in FIG. 5, when only the cell region is selectively etched using the photoresist pattern, and the spacer is removed, the etching pattern remains only in the cell region without damaging the lower buffer layer and the hard mask layer. By removing the spacers, the buffer layer remains on the uppermost layer of the cell region and the peripheral region to form the same etching barrier.

Subsequently, the hard mask layer 23A is etched using the buffer layer 24A as an etch barrier. When the hard mask layer 23A is polysilicon, the hard mask layer 23A may be etched using a silicon etching gas.

As shown in FIG. 2G, the buffer layer 24A (see FIG. 2F) is removed. Removal of the buffer layer 24A may proceed by wet etching. In the wet etching, when the buffer layer 24A is an oxide film and the hard mask layer 23A is polysilicon, the hard mask layer 23A and the lower first amorphous carbon layer 22 are not damaged and only the buffer layer 24A is selectively selected. Proceed to the condition to be removed. To this end, the wet etching may be performed by using HF or BOE (Buffered Oxide Etchant).

Subsequently, the first amorphous carbon layer 22A is etched using the hard mask layer 23A as an etch barrier. The first amorphous carbon layer 22A may be etched using a mixed gas of O 2 and N 2 .

As shown in FIG. 2H, the hard mask layer 23A (see FIG. 2G) is removed. The hard mask layer 23A may be removed by wet or dry etching.

Subsequently, the pattern 21A is formed by etching the etched layer 21 (see FIG. 2G) using the first amorphous carbon layer 22A as an etch barrier. The pattern 21A may include a pattern to which self-aligned contact etching is applied, that is, a landing plug contact or a storage node contact.

In a subsequent process, the first amorphous carbon layer 22A may be removed using an oxygen plasma in the same manner as the second amorphous carbon layer in FIG. 2D.

As above, by applying a buffer layer to the bottom of the spacer, applying a self-aligned contact etching using the buffer layer after forming the spacer, by sequentially removing the upper layer when etching the lower layer, the upper etching barriers at the time when the formation of the pattern 21A is completed It is possible to prevent the lifting phenomenon or the problem of acting as a particle source.

(Example 2)

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, an etching target layer 31 is formed on a semiconductor substrate (not shown) having a cell region and a peripheral region. In this case, the etched layer 31 may be an insulating film and the insulating film may include an oxide film.

Subsequently, a first amorphous carbon layer 32, a hard mask layer 33, a buffer layer 34, a second amorphous carbon layer 35, and an antireflection layer 36 are stacked on the etched layer 31.

The first amorphous carbon layer 32 is used as a hard mask for etching the etching target layer 31.

The hard mask layer 33 is intended to be used as a hard mask for improving adhesion between the first amorphous carbon layer 32 and the subsequent layer and for etching the first amorphous carbon layer 32. The hard mask layer 33 may be formed of a material that is not damaged during a subsequent spacer removing process, and may include, for example, polysilicon. In addition, it may be formed to a thickness of 50 ~ 300Å so that all of the subsequent self-aligned contact etching is lost and removed. That is, all of the hard mask layer 33 is removed at the time when the self-aligned contact etching is completed so as not to remain as a particle source in a subsequent process.

The buffer layer 34 is formed of a material having a high selectivity during subsequent spacer etching and a material that is not damaged when the spacer is removed. The buffer layer 34 may be formed of the same material as the layer to be etched 31. This is because the buffer layer 34 is etched during self-aligned contact etching so that all of them are removed when the self-aligned contact etching is completed, so that they do not remain as a particle source in a subsequent process. The buffer layer 34 may be formed of, for example, an oxide film.

The second amorphous carbon layer 35 is intended to be used as a sacrificial layer for forming subsequent spacers.

The anti-reflection film 36 serves as a hard mask for etching the second amorphous carbon layer 35, prevents footing between the second amorphous carbon layer 35 and the subsequent photoresist pattern, and plays an antireflection role when the photoresist pattern is formed. It is to. The antireflection film 36 may include, for example, a silicon oxynitride film 36.

Subsequently, a first photoresist film pattern 37 is formed on the antireflection film 36. The first photoresist layer pattern 37 may be formed by coating a photoresist layer on the anti-reflection layer 36 and patterning the photoresist layer by exposure and development. The first photoresist layer pattern 37 is used to define a sacrificial layer pattern necessary for forming a spacer for a subsequent SPT process, and the line width between the patterns may be wide to secure an exposure margin. In addition, the first photoresist layer pattern 37 may be formed in a line / spacer shape, and the ratio of line line width: spacer line width is 1: 2.5 to 3.5 in consideration of the final critical dimension target after final patterning. can do.

As shown in FIG. 3B, the anti-reflection film 36 (see FIG. 3A) is etched using the first photoresist pattern 37 (see FIG. 3A) as an etching barrier.

Subsequently, the second amorphous carbon layer 35 (see FIG. 3A) is etched using the first photoresist pattern 37 and the etched anti-reflection film 36 as etch barriers. When the etching of the second amorphous carbon layer 35 is completed, all of the first photoresist layer pattern 37 may be lost, and all of the anti-reflection layer 36 may be lost, or may be partially remaining.

Accordingly, the second amorphous carbon pattern 35A having the same line width and spacing between the patterns as the first photoresist pattern 37 is formed.

Subsequently, an insulating film 38 for spacers is formed along the step on the entire structure including the second amorphous carbon pattern 35A. The spacer insulating film 38 is for forming a spacer for the SPT process, and may be formed of a material having a selectivity with respect to the buffer layer 34 of an oxide film quality. For example, the spacer insulating film 38 may include a nitride film. In addition, it is formed to have a high step coverage (Step coverage) to form a pattern of a uniform line width.

As shown in FIG. 3C, the spacer insulating layer 38 (refer to FIG. 3B) is etched to form the spacer 38A on the sidewall of the second amorphous carbon pattern 35A.

The insulating layer 38 for spacers may be formed by full surface etching. The front surface etching proceeds to a target in which the upper portion of the second amorphous carbon pattern 35A and the buffer layer 34 are opened. In the case where the buffer layer 34 is an oxide film, the entire surface etching is performed under such a condition that only the spacer insulating film 38 is selectively etched without losing the buffer layer 34 by increasing the selectivity between the oxide film and the nitride film. To this end, the front surface etching may be performed using a plasma of a gas combination containing CH 2 F 2 or CH 3 F.

As shown in FIG. 3D, the second amorphous carbon pattern 35A is removed. The second amorphous carbon pattern 35A may be removed using an oxygen plasma.

Accordingly, spacers 38A spaced apart from each other at a predetermined interval remain on the buffer layer 34.

As shown in FIG. 3E, the buffer layer 34 (see FIG. 3D) of the cell region is selectively etched. To this end, a second photoresist pattern 39 is formed on the entire structure including the spacer 38A and the buffer layer 34 to open the cell region.

The second photoresist pattern 39 is formed so as to protect the peripheral area in order to selectively etch only the cell area during the subsequent Self Aligned Contact Etch. To this end, the photoresist is coated to a thickness thicker than the height of the spacer 38A on the entire structure including the spacer 38A, and patterned so that the cell region is opened by exposure and development. The two photoresist pattern 39 may be formed.

A second photoresist pattern 39 that opens the cell region and covers the peripheral region is shown in FIG. 4.

4 is a plan view of a photoresist pattern in self-aligned contact etching.

As illustrated in FIG. 4, the photoresist pattern covering the peripheral area B may be identified while the cell area is opened based on the boundary A on the spacer formed in the line type.

Subsequently, the buffer layer 34A is etched using the spacer 38A and the second photoresist pattern 39 as an etch barrier. At this time, etching is performed under the condition that only the buffer layer 34A, which is an oxide film, is selectively etched.

As shown in FIG. 3F, the second photoresist layer pattern 39 (see FIG. 3E) is removed. The second photoresist pattern 39 may be removed by dry etching. Dry etching may, for example, proceed to an oxygen strip process.

Next, the spacer 38A (see FIG. 3E) is removed. The spacer 38A may be removed by dry or wet etching, and the removing process may be performed under the condition that the lower buffer layer 34A and the hard mask layer 33 are not lost.

When the spacer 38A is a nitride film, the buffer layer 34A is an oxide film, and the hard mask layer 33 (see FIG. 3E) is polysilicon, the removal process of the spacer 38A using wet etching is performed by phosphoric acid (H 3 PO 4). Can proceed to a solution containing).

In addition, the removal process of the spacer 38A using dry etching may be performed by using a plasma of a gas combination containing fluorine (F). The fluorine-containing gas combination may include, for example, a mixed gas of CHF 3 , SF 6 and CF 4 . In the removal process of the spacer 28A using dry etching, a bias power toward a substrate (not shown) may be applied or may be applied in a range of 1 kV to 50 kV. In addition, the temperature of a board | substrate can be kept at least 50 degrees C or less (normal temperature-50 degreeC).

Top view after removal of spacer 38A is shown in FIG. 5.

5 is a top view showing a pattern after removing the spacer.

As shown in FIG. 5, after the self-aligned contact etching is performed using the photoresist pattern to selectively etch only the cell region, when the spacer is removed, the etching pattern remains only in the cell region without damaging the lower buffer layer and the hard mask layer. I can see that. By removing the spacers, the buffer layer remains on the uppermost layer of the cell region and the peripheral region to form the same etching barrier.

Subsequently, the hard mask layer 33A is etched using the buffer layer 34A as an etch barrier. When the hard mask layer 33A is polysilicon, the hard mask layer 33A may be etched using a silicon etching gas.

As shown in FIG. 3G, the first amorphous carbon layer 32A is etched using the buffer layer 34A and the hard mask layer 33A as an etching barrier. The first amorphous carbon layer 32A may be etched using a mixed gas of O 2 and N 2 .

As shown in FIG. 3H, a pattern 31A is formed by performing self-aligned contact etching on the etched layer 31 (see FIG. 1G). The pattern 31A may include a pattern to which self-aligned contact etching is applied, that is, a landing plug contact or a storage node contact.

The self-aligned contact etching is performed under the conditions for etching the oxide film, and at the time when the self-aligned contact etching is completed, all of the buffer layers 34A formed of the oxide film as in the etching target layer 31 are removed. In addition, the hard mask layer 33A formed to a thin thickness of 50 kPa to 300 kPa is also removed at the time when the self-aligned contact etching is completed. Therefore, only the first amorphous carbon layer 32A remains on the pattern 31A when the self-aligned contact etching is completed.

In a subsequent process, the first amorphous carbon layer 32A may be removed using an oxygen plasma in the same manner as the second amorphous carbon layer in FIG. 3D.

As described above, the etching of the buffer layer 34A and the hard mask layer 33A is performed by removing the buffer layer 34A and the hard mask layer 33A without removing the buffer layer 34A and the hard mask layer 33A. The process step can be shortened rather than the step, thereby securing a process margin.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention;

4 is a plan view of the photosensitive film pattern during self-aligned contact etching,

Fig. 5 is a top view showing the pattern after removing the spacer.

* Explanation of symbols for the main parts of the drawings

21: etching layer 22: first amorphous carbon layer

23: hard mask layer 24: buffer layer

25: second amorphous carbon layer 26: antireflection layer

27: first photosensitive film pattern 28A: spacer

29: second photosensitive film pattern

Claims (24)

Stacking an etched layer, a first amorphous carbon layer, a hard mask layer, and a buffer layer on a substrate having a cell region and a peripheral region; Forming a second amorphous carbon pattern on the buffer layer; Forming a spacer on sidewalls of the second amorphous carbon pattern; Removing the second amorphous carbon pattern; Selectively etching the buffer layer of the cell region; Removing the spacers; Etching the hard mask layer using the buffer layer as an etch barrier; Removing the buffer layer; Etching the first amorphous carbon layer using the hard mask layer as an etch barrier; Removing the hard mask layer; And Forming a pattern by performing self-aligned contact etching on the etched layer A semiconductor device manufacturing method comprising a. The method of claim 1, The etching target layer includes an oxide film. The method of claim 1, The hard mask layer includes a polysilicon. The method of claim 1, And the buffer layer comprises an oxide film. The method of claim 1, And the spacer comprises a nitride film. The method of claim 5, Removing the spacers, A semiconductor device manufacturing method proceeding by wet etching or dry etching. The method of claim 6, The wet etching is performed using a solution containing phosphoric acid (H 3 PO 4 ). The method of claim 6, The dry etching is performed using a gas containing a fluorine gas. The method of claim 6, The dry etching is performed without applying bias power. The method of claim 6, And the dry etching is performed by applying a bias power of 1 kPa to 50 kPa. The method of claim 4, wherein Removing the buffer layer, A method of manufacturing a semiconductor device that proceeds by wet etching. The method of claim 11, The wet etching is a method of manufacturing a semiconductor device using HF or BOE (Buffered Oxide Etchant). The method of claim 1, And the pattern comprises a landing plug contact or a storage node contact. Stacking an etched layer, a first amorphous carbon layer, a hard mask layer, and a buffer layer on a substrate having a cell region and a peripheral region; Forming a second amorphous carbon pattern on the buffer layer; Forming a spacer on sidewalls of the second amorphous carbon pattern; Removing the second amorphous carbon pattern; Selectively etching the buffer layer of the cell region; Removing the spacers; Etching the hard mask layer and the first amorphous carbon layer using the buffer layer as an etch barrier; Forming a pattern by performing self-aligned contact etching on the etched layer A semiconductor device manufacturing method comprising a. The method of claim 14, The etching target layer includes an oxide film. The method of claim 14, The hard mask layer includes polysilicon and has a thickness of 50 kPa to 300 kPa. The method of claim 14, The buffer layer is formed of the same material as the etching layer, the semiconductor device manufacturing method comprising an oxide film. The method of claim 14, And the spacer comprises a nitride film. The method of claim 18, Removing the spacers, A semiconductor device manufacturing method proceeding by wet etching or dry etching. The method of claim 19, The wet etching is performed using a solution containing phosphoric acid (H 3 PO 4 ). The method of claim 19, The dry etching is performed using a gas containing a fluorine gas. The method of claim 19, The dry etching is performed without applying bias power. The method of claim 19, And the dry etching is performed by applying a bias power of 1 kPa to 50 kPa. The method of claim 14, And the pattern comprises a landing plug contact or a storage node contact.
KR1020080065023A 2008-07-04 2008-07-04 Method for fabricating semiconductor device KR20100004705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080065023A KR20100004705A (en) 2008-07-04 2008-07-04 Method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080065023A KR20100004705A (en) 2008-07-04 2008-07-04 Method for fabricating semiconductor device

Publications (1)

Publication Number Publication Date
KR20100004705A true KR20100004705A (en) 2010-01-13

Family

ID=41814252

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080065023A KR20100004705A (en) 2008-07-04 2008-07-04 Method for fabricating semiconductor device

Country Status (1)

Country Link
KR (1) KR20100004705A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208330A (en) * 2010-03-29 2011-10-05 海力士半导体有限公司 Method for forming fine pattern
CN113314408A (en) * 2021-04-23 2021-08-27 长江先进存储产业创新中心有限责任公司 Hard mask laminated structure and semiconductor device forming method
CN113517181A (en) * 2021-04-27 2021-10-19 长江先进存储产业创新中心有限责任公司 Hard mask laminated structure and semiconductor device forming method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208330A (en) * 2010-03-29 2011-10-05 海力士半导体有限公司 Method for forming fine pattern
KR101105431B1 (en) * 2010-03-29 2012-01-17 주식회사 하이닉스반도체 Method for fabricating fine pattern
US8574819B2 (en) 2010-03-29 2013-11-05 Hynix Semiconductor Inc. Method for forming fine pattern
TWI508131B (en) * 2010-03-29 2015-11-11 Hynix Semiconductor Inc Method for forming fine pattern
CN113314408A (en) * 2021-04-23 2021-08-27 长江先进存储产业创新中心有限责任公司 Hard mask laminated structure and semiconductor device forming method
CN113517181A (en) * 2021-04-27 2021-10-19 长江先进存储产业创新中心有限责任公司 Hard mask laminated structure and semiconductor device forming method

Similar Documents

Publication Publication Date Title
KR100858877B1 (en) Method for fabricating semiconductor device
KR101145335B1 (en) Method for fabricating contact hole in semiconductor device
KR101105431B1 (en) Method for fabricating fine pattern
KR100953049B1 (en) Flash memory device and manufacturing method thereof
KR20130070351A (en) Method for manufacturing semiconductor device with side contact
US6878612B2 (en) Self-aligned contact process for semiconductor device
US20090068842A1 (en) Method for forming micropatterns in semiconductor device
KR20120120729A (en) Method for manufacturing metal pattern in semiconductor device
KR100647001B1 (en) Method of forming a floating gate electrode in flash memory device
CN103390551A (en) Method for manufacturing semiconductor device patterned structure
KR20120120666A (en) Method for manufacturing semiconductor device with side contact
KR20100004705A (en) Method for fabricating semiconductor device
KR100831975B1 (en) Method for forming pattern in semiconductor device
KR20090044810A (en) Ion implantation mask and method for manufacturing ion implantation mask therefor
KR100924006B1 (en) Method for forming contact hole in semiconductor device
CN104064474B (en) The fin structure manufacture method of Dual graphing fin transistor
KR100612947B1 (en) Method for manufacturing semiconductor device with step gated asymmetry recess
CN115332060B (en) Manufacturing method of grid structure
CN115332061B (en) Manufacturing method of grid structure
KR100733459B1 (en) Method for manufacturing semiconductor device
CN107958868B (en) Method for manufacturing isolation structure
KR100549583B1 (en) Method for forming gate of semiconductor device
KR100490299B1 (en) Method of manufacturing flash memory device
KR100886641B1 (en) Method for fabricating capacitor in semiconductor device
TWI518743B (en) Method for fabricating patterned structure of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination