CN115332060B - Manufacturing method of grid structure - Google Patents

Manufacturing method of grid structure Download PDF

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CN115332060B
CN115332060B CN202211250269.6A CN202211250269A CN115332060B CN 115332060 B CN115332060 B CN 115332060B CN 202211250269 A CN202211250269 A CN 202211250269A CN 115332060 B CN115332060 B CN 115332060B
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layer
region
ono
etching
mask
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CN115332060A (en
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朱梦媚
尹记红
许宗能
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation

Abstract

The invention provides a manufacturing method of a grid structure. The manufacturing method comprises the following steps: providing a substrate, wherein the upper surface of the substrate comprises a plurality of first areas, a plurality of second areas and a third area, the first areas are elongated along a first direction and span a plurality of active areas, the second areas span the first areas, and the third areas are positioned between two adjacent first areas; forming a grid material layer and an ONO layer on the upper surface of the substrate, wherein the ONO layer comprises a first oxide layer, a nitride layer and a second oxide layer; etching to remove the second oxide layer and the nitride layer on the second area, and at least reserving the first oxide layer with partial thickness on the second area; etching to remove the ONO layer on the third area, wherein the first oxide layer on the second area is used as a sacrificial layer in the etching process; and etching the gate material layer by using at least the nitride layer remained on the first region as a mask to form a gate. Therefore, the manufacturing cost of the grid is low, and the problem that the etching process window of the organic bottom layer structure layer is narrow is avoided.

Description

Manufacturing method of grid structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a grid structure.
Background
At present, in the 40nm and below Technology nodes, the required resolution index applied to the key level lithography process exceeds the limit capability of the existing optical lithography platform, and the industry adopts various technical solutions to solve the technical problem, and according to the ITRS roadmap, the technical solutions of Double Patterning Technology (DPT for short), extreme ultraviolet Technology (EUV), direct writing for Electronics (EBL), and the like are all expected in the industry. The double patterning technology is to decompose and split a set of high-density circuit pattern into two or more sets of circuit patterns with lower density, then respectively manufacture photoetching plates, successively complete corresponding exposure and etching processes, and finally combine to form the high-density pattern required initially.
Fig. 1 is a Layout diagram (Layout) of a semiconductor structure. As shown in fig. 1, the semiconductor structure includes a substrate 100, an Active Area (AA) and an isolation area for isolating the active area are formed in the substrate 100, a first area 100a, a second area 100b and a third area 100c are formed on an upper surface of the substrate 100, the first area 100a spans a plurality of active areas, the second area 100b is located on the isolation area between the active areas and spans the first area 100a, an area between two adjacent first areas 100a is the third area 100c, a portion of the second area 100b overlaps the first area 100a, and the remaining portion of the second area 100b overlaps the third area 100 c. When a gate is formed on the substrate 100, a double patterning technique is used, which specifically includes the following steps S01 to S04.
Fig. 2 shows a plan view after an ONO layer is formed on a semiconductor structure, and fig. 3 shows a partial cross-sectional view taken along a point indicated by line BC in fig. 2.
In step S01, referring to fig. 2 and 3, a gate oxide layer 101, a polysilicon layer 102 and an ONO layer 103 are sequentially formed on a substrate 100, and a patterned first photoresist layer (not shown) is formed on the ONO layer 103.
In step S02, as shown in fig. 4, the ONO layer 103 on the third region 100c is etched and removed by using the first photoresist layer as a mask, and the ONO layer 103 on the first region 100a is remained, wherein the polysilicon layer 102 is not shown in fig. 4 for clarity of illustration.
Fig. 5 shows a partial cross-sectional view of the organic underlayer structural layer and the SHB layer formed on the substrate at a position indicated by line BC in fig. 4. Fig. 6 shows a partial cross-sectional view of the organic underlayer structural layer and the SHB layer after etching, taken along the line BC in fig. 4. Fig. 7 shows a partial cross-sectional view of the organic substructure layer and SHB layer formed on the substrate at the location indicated by line DE in fig. 4. Fig. 8 shows a partial cross-sectional view of the organic substructure layer and the SHB layer after etching, taken along the line DE in fig. 4.
Step S03, referring to fig. 5 and 7, sequentially forming an Organic bottom Layer 104 (ODL), an SHB (Si-O-based Hard Mask) Layer 105 and a patterned second photoresist Layer 106 on the substrate 100, where the second photoresist Layer 106 has an opening 107 corresponding to the second region 100 b; etching the SHB layer 105 and the organic bottom structure layer 104 downward using the second photoresist layer 106 as a mask, as shown in fig. 6, to expose the ONO layer 103 on the second region 100 b; since the organic underlying structure layer 104 on the third region 100c is thicker than the organic underlying structure layer 104 on the adjacent first region 100a, as shown by the dashed line box in fig. 8, a partial thickness of the organic underlying structure layer 104 remains at the overlapping position of the second region 100b and the third region 100 c; as shown in fig. 6 and 8, during the etching process of the SHB layer 105 and the organic underlying structural layer 104, the second photoresist layer 106 is worn away, and the SHB layer 105 located below the second photoresist layer 106 also loses a part of the thickness.
Step S04, continuously etching down to remove the ONO layer 103 on the second region 100b, so that the ONO layer 103 on the first region 100a is isolated, as shown in fig. 9, until the patterning process of the ONO layer 103 is completed, wherein in the process of removing the ONO layer 103 on the second region 100b, an organic bottom structure layer 104 remaining at an overlapping position of the second region 100b and the third region 100c protects a polysilicon layer therebelow, and the polysilicon layer is not shown in fig. 9; next, the polysilicon layer 102 is patterned using the ONO layer 103 as a mask, thereby forming a polysilicon gate.
In the process of forming the polysilicon gate, in step S03, if the remaining thickness of the organic bottom structure layer 104 is too thick in the dashed line frame shown in fig. 8, when the ONO layer 103 on the second region 100b is removed by etching in step S04, a polymer (polymer) is easily deposited on the sidewall of the organic bottom structure layer 104, which increases residue of the ONO layer, and further causes residue of a polysilicon layer to cause polysilicon gate bridging (Bridge); in step S03, if the remaining thickness of the organic bottom structure layer 104 in the dashed-line frame shown in fig. 8 is too thin, the ONO layer 103 on the second region 100b is removed by etching in step S04, which is likely to damage the polysilicon layer 102, as shown in fig. 10, and the gate oxide layer 101 below the polysilicon layer 102 is subsequently likely to be damaged by over-etching when the polysilicon layer 102 is etched, so that the probability of pitting (pitting) in the active region is increased, and the performance of the semiconductor device is affected. Therefore, in the process of forming the polysilicon gate, the etching process window of the organic bottom structure layer 104 is narrow, and the process stability is poor; in addition, the organic bottom structure layer and the SHB layer are used in the process of forming the polysilicon gate due to the high cost of the organic bottom structure layer and the SHB layer, so that the production cost is increased.
Disclosure of Invention
The invention provides a manufacturing method of a grid structure, which does not need to use an organic bottom layer structure layer and an SHB layer, and has lower manufacturing cost and larger process window.
In order to achieve the above object, the present invention provides a method for fabricating a gate structure. The manufacturing method of the grid structure comprises the following steps:
providing a substrate having an isolation region therein and a plurality of active regions defined by the isolation region; the upper surface of the substrate comprises a plurality of first regions elongated along a first direction, a plurality of second regions elongated along a second direction, and a third region located between two adjacent first regions, each first region spans a plurality of the active regions, each second region spans the first regions, part of each second region overlaps with the first region, and the rest overlaps with the third region;
forming a grid material layer and an ONO layer on the grid material layer on the upper surface of the substrate, wherein the ONO layer comprises a first oxide layer, a nitride layer and a second oxide layer which are stacked from bottom to top;
forming a patterned first mask layer on the ONO layer, etching and removing the second oxide layer and the nitride layer on each second area by taking the patterned first mask layer as a mask, and at least reserving the first oxide layer with partial thickness on the second area; removing the patterned first mask layer;
forming a second patterned mask layer, and removing the ONO layer on the third area by etching by taking the second patterned mask layer as a mask; in the process of removing the ONO layer on the third area by etching, the first oxide layer reserved on the second area is used as a grid material layer under the protection of a sacrificial layer, and when the upper surface of the grid material layer on the third area is exposed, the upper surface of the grid material layer on the second area is exposed;
and etching the gate material layer by taking the ONO layer remained on the first region as a mask to form a gate.
Optionally, the method for forming the patterned second mask layer includes: forming an amorphous carbon layer covering the ONO layer, a bottom anti-reflection layer covering the amorphous carbon layer, and a second photoresist layer covering the bottom anti-reflection layer; and exposing and developing the second photoresist layer to form a patterned second mask layer.
Optionally, the method for removing the ONO layer on the third region by etching includes: and etching the bottom anti-reflection layer, the amorphous carbon layer and the ONO layer on the third area by taking the patterned second mask layer as a mask until the upper surface of the grid material layer on the third area is exposed.
Optionally, by adjusting the thickness of the amorphous carbon layer and/or adjusting the etching condition during the process of removing the ONO layer on the third region by etching, the first oxide layer on the second region is removed when the upper surface of the gate material layer on the third region is exposed.
Optionally, the thickness of the amorphous carbon layer is 1000 angstroms to 1200 angstroms, and the thickness of the bottom anti-reflection layer is 300 angstroms to 450 angstroms.
Optionally, when the upper surface of the gate material layer on the third region is exposed, the first oxide layer remaining on the second region is removed, and the upper surface of the gate material layer on the second region is exposed, by using etching loss existing in the process of removing the ONO layer on the third region by etching.
Optionally, the first direction and the second direction are perpendicular to each other, and the active region is elongated along the second direction; the second region is located above the isolation region.
Optionally, before the gate material layer is formed on the upper surface of the substrate, a gate oxide layer is formed on the upper surface of the substrate.
Optionally, the thickness of the first oxide layer is 30 angstroms to 45 angstroms, the thickness of the nitride layer is 300 angstroms to 400 angstroms, and the thickness of the second oxide layer is 200 angstroms to 300 angstroms.
Optionally, the gate material layer includes a polysilicon layer.
In the manufacturing method, the ONO layer on the second area is etched at first, and at least partial thickness of the first ONO layer on the second area is reserved, and then the ONO layer on the third area is etched, so that the patterning of the ONO layer is completed, an organic bottom layer structure layer (namely ODL) and an SHB layer are not needed, and the manufacturing cost is reduced; when the ONO layer on the third area is etched, the first oxide layer reserved on the second area serves as the gate material layer under the protection of the sacrificial layer, so that the probability of damaging the gate material layer when the ONO layer on the third area is etched can be reduced, the problem that the etching process window of the organic bottom layer structure layer is narrow is avoided, the etching process windows of the second oxide layer and the nitride layer on the second area are relatively large, the etching process window of the subsequent gate material layer is also large, the probability of pitting corrosion of the active area is favorably reduced, the process stability is improved, and the production yield is improved.
Drawings
FIG. 1 is a layout diagram of a semiconductor structure.
Fig. 2 illustrates a plan view of a semiconductor structure after an ONO layer is formed thereon.
Fig. 3 shows a partial cross-sectional view taken along the line BC in fig. 2.
FIG. 4 is a plan view of the semiconductor structure after removal of the ONO layer over a third region.
Fig. 5 illustrates a partial cross-sectional view of the organic substructure layer and the SHB layer formed on the substrate at a location indicated by line BC in fig. 4.
Fig. 6 shows a partial cross-sectional view of the organic underlayer structural layer and the SHB layer after etching, taken along the line BC in fig. 4.
Fig. 7 shows a partial cross-sectional view of the organic substructure layer and SHB layer formed on the substrate at the location indicated by line DE in fig. 4.
Fig. 8 shows a partial cross-sectional view of the organic underlayer structural layer and the SHB layer after etching, taken along the line DE in fig. 4.
FIG. 9 is a plan view of the ONO layer removed from the second region.
Fig. 10 is a partial cross-sectional view after etching the polysilicon layer.
Fig. 11 is a flowchart of a method for fabricating a gate structure according to an embodiment of the invention.
FIG. 12 is a top plan view of a substrate in accordance with one embodiment of the present invention.
FIG. 13 is a top plan view of an ONO layer formed on a top surface of a substrate in accordance with an embodiment of the present invention.
FIG. 14 is a partial cross-sectional view of an ONO layer formed on a top surface of a substrate according to an embodiment of the invention.
FIG. 15 is a partial cross-sectional view of a patterned first mask layer formed over the ONO layer in accordance with an embodiment of the present invention.
FIG. 16 is a top plan view of the ONO layer partially etched away over the second region in accordance with an embodiment of the present invention.
Fig. 17 is a schematic partial cross-sectional view taken along line BC of fig. 16.
FIG. 18 is a top plan view of a patterned second mask layer formed on a substrate in accordance with one embodiment of the present invention.
Fig. 19 is a partial cross-sectional view taken along the line BC in fig. 18.
Fig. 20 is a partial cross-sectional view taken along the line DE of fig. 18.
Fig. 21 is a partial cross-sectional view of the ONO layer removed from the third region along line BC of fig. 18 in accordance with an embodiment of the present invention.
Fig. 22 is a partial cross-sectional view taken along line DE of fig. 18 after removal of the ONO layer over the third region in accordance with an embodiment of the present invention.
Fig. 23 is a partial cross-sectional view of the gate material layer etched at a location indicated by line BC in fig. 18 in accordance with an embodiment of the present invention.
Fig. 24 is a partial cross sectional view of a portion of the gate material layer after etching at a location along line DE of fig. 18 in accordance with an embodiment of the present invention.
Description of the reference numerals:
(fig. 1 to 10) 100-a substrate; 100 a-a first region; 100 b-a second region; 100 c-a third region; 101-a gate oxide layer; 102-a polysilicon layer; 103-ONO layer; 104-organic bottom structural layer; 105-SHB layer; 106-a second photoresist layer; 107-opening;
(fig. 12-24) 200-substrate; 200 a-a first region; 200 b-a second region; 200 c-a third region; 201-a gate oxide layer; 202-a layer of gate material; 203-ONO layer; 203 a-a first oxide layer; 203 b-a nitride layer; 203 c-a second oxide layer; 204-a patterned first mask layer; 205 — an amorphous carbon layer; 206-bottom antireflective layer; 207-patterned second mask layer.
Detailed Description
The following describes the method for fabricating a gate structure in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to increase a manufacturing process window and reduce production cost, the application provides a manufacturing method of a grid structure. Fig. 11 is a flowchart illustrating a method for fabricating a gate structure according to an embodiment of the invention. As shown in fig. 11, the method for manufacturing the gate structure includes:
s10, providing a substrate, wherein the substrate is provided with an isolation region and a plurality of active regions defined by the isolation region; the upper surface of the substrate comprises a plurality of first regions elongated along a first direction, a plurality of second regions elongated along a second direction, and a third region located between two adjacent first regions, each first region spans a plurality of the active regions, each second region spans the first regions, part of each second region overlaps with the first region, and the rest overlaps with the third region;
s20, forming a grid electrode material layer and an ONO layer positioned on the grid electrode material layer on the upper surface of the substrate, wherein the ONO layer comprises a first oxide layer, a nitride layer and a second oxide layer which are stacked from bottom to top;
s30, forming a patterned first mask layer on the ONO layer, etching and removing the second oxide layer and the nitride layer on each second area by taking the patterned first mask layer as a mask, and at least reserving the first oxide layer with partial thickness on the second area; removing the patterned first mask layer;
s40, forming a patterned second mask layer, and removing the ONO layer on the third area by etching by taking the patterned second mask layer as a mask; in the process of removing the ONO layer on the third region by etching, the first oxide layer remained on the second region is used as a gate material layer under the protection of the sacrificial layer, and when the upper surface of the gate material layer on the third region is exposed, the upper surface of the gate material layer on the second region is exposed;
and S50, etching the grid material layer by taking the ONO layer remained on the first area as a mask to form a grid.
Fig. 12 to 24 are schematic partial step diagrams of a method for fabricating a gate structure according to an embodiment of the invention, and the method for fabricating a gate structure of the present application is described below with reference to fig. 12 to 24.
FIG. 12 is a top plan view of a substrate in accordance with an embodiment of the present invention. As shown in fig. 12, the substrate 200 has therein isolation regions (i.e., empty regions between the active regions in fig. 12) and a plurality of active regions (AA) defined by the isolation regions; the upper surface of the substrate 200 includes a plurality of first regions 200a elongated in a first direction (e.g., a horizontal direction in fig. 12), a plurality of second regions 200b elongated in a second direction (e.g., a vertical direction in fig. 12), and a third region 200c located between two adjacent first regions 200a, each of the first regions 200a spanning a plurality of the active regions, each of the second regions 200b spanning the first regions 200a, a portion of each of the second regions 200b overlapping the first regions 200a, and the remaining portion overlapping the third regions 200c. It can also be said that the upper surface of the substrate 200 is divided into a first region 200a, a second region 200b, and a third region 200c.
As an example, the first direction may be perpendicular to the second direction, for example, the first direction is a horizontal direction of fig. 12, the second direction is a vertical direction of fig. 12, the active region (AA) is elongated along the second direction, and the second region 200b is located above the isolation region.
In this embodiment, the substrate 200 may be a silicon substrate. But not limited thereto, the substrate 200 may also be a Germanium substrate, a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like, and a certain doping particle may be implanted into the substrate 200 according to design requirements to change electrical parameters.
FIG. 13 is a top plan view of an ONO layer formed on a top surface of a substrate in accordance with an embodiment of the present invention. FIG. 14 is a partial cross-sectional view illustrating the formation of an ONO layer on the top surface of the substrate in accordance with one embodiment of the present invention. As shown in fig. 13 and 14, a gate material layer 202 and an ONO layer 203 on the gate material layer 202 are formed on an upper surface of the substrate 200.
In the present embodiment, the gate material layer 202 may be a polysilicon layer, but is not limited thereto. The gate material layer 202 may also be another metal gate material layer. As shown in fig. 14, the ONO layer 203 includes a first oxide layer 203a, a nitride layer 203b, and a second oxide layer 203c stacked in this order from bottom to top. The material of the first oxide layer 203a and the second oxide layer 203c may include silicon oxide. The material of the nitride layer 203b may include silicon nitride or silicon oxynitride.
The thickness of the gate material layer 202 may be 700-900 angstroms, such as 800 angstroms. The thickness of the first oxide layer 203a may be 30 to 45 angstroms, for example, 37 angstroms. The thickness of the nitride layer 203b may be 300 to 400 angstroms, for example 350 angstroms. The thickness of the second oxide layer 203c may be 200 angstroms to 300 angstroms, for example, 225 angstroms; the second oxide layer 203c may be formed by a chemical vapor deposition (PECVD) process using Tetraethylorthosilicate (TEOS).
Referring to fig. 14, before forming a gate material layer 202 on an upper surface of a substrate 200, a gate oxide layer 201 is formed on the upper surface of the substrate 200. The material of the gate oxide layer 201 may include silicon oxide. The gate oxide layer 201 may be formed by a thermal oxidation process, but is not limited thereto. The gate oxide layer 201 may also be formed by other methods known in the art.
FIG. 15 is a partial cross-sectional view of the ONO layer after a patterned first mask layer is formed thereon according to one embodiment of the present invention. As shown in fig. 15, a patterned first mask layer 204 is formed on the ONO layer 203. Specifically, the method for forming the patterned first mask layer 204 includes: a first photoresist layer is formed by coating photoresist on the ONO layer 203, and the first photoresist layer is exposed and developed to form a patterned first mask layer 204, wherein the patterned first mask layer 204 has an opening corresponding to the second region 200 b.
FIG. 16 is a top plan view of the ONO layer partially etched away from the second region in accordance with an embodiment of the present invention. Fig. 17 is a schematic partial cross-sectional view taken along line BC of fig. 16. As shown in fig. 16 and fig. 17, using the patterned first mask layer 204 as a mask, the second oxide layer 203c and the nitride layer 203b on each of the second regions 200b are etched and removed, and at least a part of the thickness of the first oxide layer 203a on the second regions 200b is remained, for example, the entire thickness of the first oxide layer 203a on the second regions 200b may be remained.
After removing the second oxide layer 203c and the nitride layer 203b on the second region 200b, as shown with reference to fig. 17, the patterned first mask layer 204 is removed. Specifically, an ashing process may be used to remove the patterned first mask layer 204.
FIG. 18 is a top plan view of a patterned second mask layer formed over a substrate in accordance with an embodiment of the present invention. Fig. 19 is a partial cross-sectional view taken along the line BC in fig. 18. Fig. 20 is a partial cross-sectional view taken along the line DE of fig. 18. As shown in fig. 18, 19 and 20, a patterned second mask layer 207 is formed on the substrate 200, the patterned second mask layer 207 covering the first region 200a and exposing the third region 200c.
Specifically, the method for forming the patterned second mask layer 207 may include: forming an amorphous carbon layer 205 covering the ONO layer 203, a bottom anti-reflective layer 206 covering the amorphous carbon layer 205, and a second photoresist layer covering the bottom anti-reflective layer 206; and exposing and developing the second photoresist layer to form a patterned second mask layer 207. The bottom anti-reflection layer 206 and the amorphous carbon layer 205 are disposed under the second photoresist layer, so that the reflection of light on the lower surface of the second photoresist layer during the exposure process can be reduced, and most of the exposed energy is absorbed by the second photoresist layer, which is helpful for improving the pattern precision of the patterned second mask layer 207. Amorphous carbon layer 205 may have a thickness of 1000 angstroms to 1200 angstroms, such as 1100 angstroms. The thickness of the bottom anti-reflective layer 206 may be 300 to 450 angstroms, such as 370 angstroms.
Referring to fig. 19 and 20, since the second oxide layer 203c and the nitride layer 203b on the second region 200b are removed such that there is a recess in the ONO layer 203, the amorphous carbon layer 205 fills the recess such that the thickness of the amorphous carbon layer 205 above the second region 200b is greater than the thickness of the amorphous carbon layer 205 above other regions adjacent to the second region 200 b.
After forming the patterned second mask layer 207, the ONO layer 203 on the third region 200c is etched and removed by using the patterned second mask layer 207 as a mask.
Fig. 21 is a partial cross-sectional view of the ONO layer removed from the third region along line BC of fig. 18 in accordance with an embodiment of the present invention. Fig. 22 is a partial cross-sectional view taken along line DE of fig. 18 after removal of the ONO layer over the third region in accordance with an embodiment of the present invention. Referring to fig. 18, 19, 20, 21 and 22, the method for removing the ONO layer 203 on the third region 200c by etching may include: and etching the bottom anti-reflection layer 206, the amorphous carbon layer 205 and the ONO layer 203 on the third region 200c by using the patterned second mask layer 207 as a mask until the upper surface of the gate material layer 202 on the third region 200c is exposed. In the process of removing the ONO layer 203 on the third region 200c by etching, the first oxide layer 203a remaining on the second region 200b serves as a sacrificial layer to protect the underlying gate material layer, and when the upper surface of the gate material layer on the third region 200c is exposed, the upper surface of the gate material layer on the second region 200b is exposed.
In the process of removing the ONO layer 203 on the third region 200c by etching, an etching loss may be caused to the patterned second mask layer 207, the bottom anti-reflection layer 206, and the amorphous carbon layer 205 on the first region 200a, and preferably, the etching loss existing in the process of removing the ONO layer 203 on the third region 200c by etching is utilized, so that when the upper surface of the gate material layer 202 on the third region 200c is exposed, the first oxide layer 203a remaining on the second region 200b is removed, and the upper surface of the gate material layer 202 on the second region 200b is exposed, so that after removing the ONO layer on the third region 200c, an additional etching process is not required to remove the first oxide layer 203a on the second region 200b, which is beneficial to simplifying a process flow and saving production cost, and can avoid damage to the surface of the gate material layer 202 caused by the additional etching process, and can avoid adverse effects of the additional etching process on the flatness of the surface of the gate material layer 202.
In this embodiment, the thickness of the amorphous carbon layer 205 and/or the etching condition during the process of removing the ONO layer in the third region 200c by etching may be adjusted, so that the first oxide layer 203a in the second region 200b is removed when the upper surface of the gate material layer 202 in the third region 200c is exposed, but is not limited thereto. The thickness of the patterned second mask layer 207 and the thickness of the bottom anti-reflection layer 206 may be adjusted to achieve the purpose that the first oxide layer 203a on the second region 200b is removed when the upper surface of the gate material layer 202 on the third region 200c is exposed.
It should be noted that, in the present embodiment, in the process of removing the ONO layer 203 on the third region 200c by etching to expose the upper surface of the gate material layer 202, the loss of the thickness of the second oxide layer 203c on the first region 200a may be accompanied while the first oxide layer 203a on the second region 200b is lost.
After removing the ONO layer 203 on the third region 200c and the first oxide layer 203a on the second region 200b, the gate material layer 202 is etched to form a gate, using the remaining ONO layer 203 on the first region 200a as a mask.
Fig. 23 is a partial cross-sectional view of the gate material layer etched at a location indicated by line BC in fig. 18 in accordance with an embodiment of the present invention. Fig. 24 is a partial cross sectional view of the gate material layer etched along line DE of fig. 18 in accordance with an embodiment of the present invention. At the end of etching the gate material layer 202, as shown in fig. 23, the gate material layer 202 on the second region 200b is removed, and the gate material layer 202 on the region where the first region 200a and the second region 200b do not overlap is remained as the gate. As shown in fig. 24, at the end of etching the gate material layer 202, the gate material layer 202 on the third region 200c is removed.
After the etching of the gate material layer 202 is finished, the remaining ONO layer is removed.
In the manufacturing method of the application, the ONO layer 203 on the second region 200b is etched firstly, and at least partial thickness of the first oxide layer 203a on the second region 200b is reserved, and then the ONO layer 203 on the third region 200c is etched, so that the patterning of the ONO layer 203 is completed, an organic bottom layer structure layer (namely ODL) and an SHB layer are not needed, and the manufacturing cost is reduced; when the ONO layer 203 on the third region 200c is etched, the first oxide layer 203a remaining on the second region 200b serves as a sacrificial layer to protect the gate material layer 202 below, so that the probability of damaging the gate material layer 202 when the ONO layer 203 of the third region 200c is etched can be reduced, the problem that the etching process window of the organic bottom layer structure layer is narrow is avoided, the etching process windows of the second oxide layer 203c and the nitride layer 203b on the second region 200b are relatively large, and the etching process window of the subsequent gate material layer 202 is also large, thereby being beneficial to reducing the probability of pitting of the active region, improving the stability of the process and improving the production yield.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims (10)

1. A method for manufacturing a gate structure, comprising:
providing a substrate having an isolation region therein and a plurality of active regions defined by the isolation region; the upper surface of the substrate comprises a plurality of first regions elongated along a first direction, a plurality of second regions elongated along a second direction, and a third region located between two adjacent first regions, each first region spans a plurality of the active regions, each second region spans the first regions, part of each second region overlaps with the first region, and the rest overlaps with the third region;
forming a grid material layer and an ONO layer on the grid material layer on the upper surface of the substrate, wherein the ONO layer comprises a first oxide layer, a nitride layer and a second oxide layer which are stacked from bottom to top;
forming a patterned first mask layer on the ONO layer, etching and removing the second oxide layer and the nitride layer on each second area by taking the patterned first mask layer as a mask, and at least reserving the first oxide layer with partial thickness on the second area; removing the patterned first mask layer;
forming a second patterned mask layer, and etching and removing the ONO layer on the third area by taking the second patterned mask layer as a mask; in the process of removing the ONO layer on the third region by etching, the first oxide layer remained on the second region is used as a gate material layer under the protection of the sacrificial layer, and when the upper surface of the gate material layer on the third region is exposed, the upper surface of the gate material layer on the second region is exposed; and
and etching the gate material layer by taking the ONO layer remained on the first area as a mask to form a gate.
2. The method of claim 1, wherein the step of forming the patterned second mask layer comprises:
forming an amorphous carbon layer covering the ONO layer, a bottom anti-reflection layer covering the amorphous carbon layer, and a second photoresist layer covering the bottom anti-reflection layer; and
and exposing and developing the second photoresist layer to form a patterned second mask layer.
3. The method of claim 2, wherein the etching to remove the ONO layer over the third region comprises:
and etching the bottom anti-reflection layer, the amorphous carbon layer and the ONO layer on the third area by taking the patterned second mask layer as a mask until the upper surface of the grid material layer on the third area is exposed.
4. The method of claim 3, wherein the first oxide layer on the second region is removed when the upper surface of the gate material layer on the third region is exposed by adjusting a thickness of the amorphous carbon layer and/or adjusting an etching condition during the process of removing the ONO layer on the third region by etching.
5. The method of claim 2, wherein the amorphous carbon layer has a thickness of 1000 to 1200 angstroms, and the bottom anti-reflective layer has a thickness of 300 to 450 angstroms.
6. The method according to claim 1, wherein an etching loss during the process of removing the ONO layer on the third region by etching is used, so that when the upper surface of the gate material layer on the third region is exposed, the first oxide layer remaining on the second region is removed to expose the upper surface of the gate material layer on the second region.
7. The method of claim 1, wherein the first direction and the second direction are perpendicular to each other, the active region being elongated along the second direction; the second region is located above the isolation region.
8. The method of claim 1 wherein a gate oxide layer is formed on the upper surface of the substrate prior to forming the layer of gate material on the upper surface of the substrate.
9. The method of claim 1, wherein the first oxide layer has a thickness of 30 to 45 angstroms, the nitride layer has a thickness of 300 to 400 angstroms, and the second oxide layer has a thickness of 200 to 300 angstroms.
10. The method of claim 1, wherein the layer of gate material comprises a layer of polysilicon.
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KR100542750B1 (en) * 2003-10-31 2006-01-11 삼성전자주식회사 Method for manufacturing semiconductor device
TWI252512B (en) * 2004-10-20 2006-04-01 Hynix Semiconductor Inc Semiconductor device and method of manufacturing the same

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US6635533B1 (en) * 2003-03-27 2003-10-21 Powerchip Semiconductor Corp. Method of fabricating flash memory
JP2006295180A (en) * 2005-04-09 2006-10-26 Samsung Electronics Co Ltd Field-effect transistor having perpendicular electrode and manufacturing method thereof
CN115084030A (en) * 2022-07-19 2022-09-20 合肥晶合集成电路股份有限公司 Forming method of high-voltage device and high-voltage device

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