CN115084030A - Forming method of high-voltage device and high-voltage device - Google Patents

Forming method of high-voltage device and high-voltage device Download PDF

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Publication number
CN115084030A
CN115084030A CN202210845012.9A CN202210845012A CN115084030A CN 115084030 A CN115084030 A CN 115084030A CN 202210845012 A CN202210845012 A CN 202210845012A CN 115084030 A CN115084030 A CN 115084030A
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layer
groove
hard mask
region
substrate
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CN115084030B (en
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齐栋洋
蔡君正
吴建兴
毛海州
李乐
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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Abstract

The invention provides a forming method of a high-voltage device and the high-voltage device, belonging to the field of semiconductor manufacturing process, wherein the forming method of the high-voltage device comprises the following steps: providing a substrate of a high-voltage element area, and sequentially forming a bottom oxide layer, a buffer layer, a hard mask layer and a graphical photoresist layer on the substrate; and etching the hard mask layer by a dry method by taking the patterned photoresist layer as a mask to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad oxide layer, the buffer layer and the hard mask layer, and the residual photoresist layer is removed, so that the etching rate of the buffer layer is minimum, the etching rate of the hard mask layer is maximum, and the high-voltage device is formed. According to the invention, the working effect of the etching stop layer is improved by adding the buffer layer, and the substrate is not exposed during dry etching through the etching stop action of the buffer layer and the bottom oxide layer, so that the defect of silicon loss generated in a pattern area during dry etching is solved, the failure problem of a high-voltage device is improved, and the yield is improved.

Description

Forming method of high-voltage device and high-voltage device
Technical Field
The invention relates to the field of semiconductor manufacturing processes, in particular to a high-voltage device and a forming method thereof.
Background
As shown in fig. 1, in the process of manufacturing the high voltage device, a thin underlying oxide layer 21 needs to be formed on a silicon substrate 10, a silicon nitride layer 22 and a patterned initial photoresist layer 30 are deposited on the underlying oxide layer 21, and in a dry etching process of the silicon nitride layer 22 with the patterned initial photoresist layer 30 as a mask, the silicon nitride layer 22 and the underlying oxide layer 21 exposed by the patterned initial photoresist layer 30 are all easily etched away, and the silicon substrate 10 is further etched by a certain depth, which causes a silicon loss defect a of the high voltage device, thereby easily causing a defect of the high voltage device, and affecting the yield of the high voltage device.
Disclosure of Invention
The invention aims to provide a method for forming a high-voltage device and the high-voltage device, which can solve the defect of silicon loss in a pattern area during dry etching.
In order to solve the above problems, the present invention provides a method for forming a high voltage device, comprising the steps of:
providing a substrate, wherein the substrate comprises a high-voltage element area, and a pad oxide layer, a buffer layer, a hard mask layer and a graphical photoresist layer are sequentially formed on the substrate of the high-voltage element area;
taking the patterned photoresist layer as a mask, etching the hard mask layer by a dry method to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad oxide layer, the buffer layer and the hard mask layer, and removing the residual photoresist layer;
wet etching the bottom of the first groove by taking the hard mask layer as a mask, and exposing the surface of the substrate to form a second groove, wherein the second groove is positioned below the first groove and is communicated with the first groove;
forming a high-voltage gate oxide layer in the first groove and the second groove;
and sequentially removing the hard mask layer and the buffer layer to form the high-voltage device.
Optionally, in the bottom oxide layer, the buffer layer, and the hard mask layer, an etching rate of the buffer layer is the smallest, and an etching rate of the hard mask layer is the largest.
Optionally, providing a substrate, where the substrate includes a high voltage device region, and sequentially forming a pad oxide layer, a buffer layer, a hard mask layer, and a patterned photoresist layer on the substrate in the high voltage device region specifically includes:
providing a substrate, wherein the substrate comprises a high-voltage element region, and the high-voltage element region comprises an HVNMOS region and an HVPMOS region;
forming a pad bottom oxide layer on the substrate of the high-voltage element region through a thermal growth process;
sequentially forming a buffer layer and a hard mask layer on the underlying oxide layer through a deposition process; and
and forming a photoresist layer on the hard mask layer, and forming a patterned photoresist layer through a photoetching process, wherein the patterned photoresist layer is provided with a first opening and a second opening, the first opening is positioned above the substrate of the HVNMOS region, and the second opening is positioned above the substrate of the HVPMOS region.
Optionally, the material of the underlying oxide layer is silicon oxide; the buffer layer is made of silicon carbonitride, and the hard mask layer is made of silicon nitride.
Optionally, the thickness of the buffer layer is 100 a ± 10 a, the thickness of the hard mask layer is 500 a ± 50 a, and the thickness of the underlying oxide layer is 55 a ± 5 a.
Further, with the patterned photoresist layer as a mask, dry etching the hard mask layer to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad bottom oxide layer, the buffer layer and the hard mask layer, and removing the remaining photoresist layer specifically comprises:
etching the hard mask layer by a dry method by taking the patterned photoresist layer as a mask, and stopping etching in the buffer layer, wherein the bottom of the first groove is positioned in the buffer layer; and
and removing the residual photoresist layer through an ashing process to expose the hard mask layer outside the first groove.
Further, with the patterned photoresist layer as a mask, dry etching the hard mask layer to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad bottom oxide layer, the buffer layer and the hard mask layer, and removing the remaining photoresist layer specifically comprises:
taking the patterned photoresist layer as a mask, etching the hard mask layer and the buffer layer by a dry method, and exposing the bottom oxide layer, wherein the bottom of the first groove is positioned on the surface of the bottom oxide layer or in the bottom oxide layer; and
and removing the residual photoresist layer through an ashing process to expose the hard mask layer outside the first groove.
Further, wet etching the bottom of the first groove with the hard mask layer as a mask to expose the surface of the substrate to form a second groove specifically includes:
and wet etching the buffer layer and the substrate oxide layer positioned at the bottom of the first groove by using the hard mask layer as a mask to expose the surface of the substrate so as to form a second groove.
Further, wet etching the bottom of the first groove with the hard mask layer as a mask to expose the surface of the substrate to form a second groove specifically includes:
and taking the hard mask layer as a mask, and etching the bottom oxide layer positioned at the bottom of the first groove by a wet method to expose the surface of the substrate so as to form a second groove.
Further, the first recess includes a first recess of the HVNMOS region and a first recess of the HVPMOS region, the second recess includes a second recess of the HVNMOS region and a second recess of the HVPMOS region, the first recess of the HVNMOS region is located above the second recess of the HVNMOS region, and the first recess of the HVNMOS region and the second recess of the HVNMOS region are in communication; the first groove of the HVPMOS region is located above the second groove of the HVPMOS region, and the first groove of the HVPMOS region and the second groove of the HVPMOS region are communicated.
Optionally, the forming of the high-voltage gate oxide layer in the first groove and the second groove specifically includes: and forming a high-voltage gate oxide layer in the second groove through a deposition process, wherein the high-voltage gate oxide layer fills the second groove and the first groove, and the thickness of the high-voltage gate oxide layer is greater than the total thickness of the bottom oxide layer, the first hard mask layer and the hard mask layer.
The invention also provides a high-voltage device prepared by the forming method of the high-voltage device.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a forming method of a high-voltage device and the high-voltage device, wherein the forming method of the high-voltage device comprises the following steps: providing a substrate, wherein the substrate comprises a high-voltage element area, and a substrate oxide layer, a buffer layer, a hard mask layer and a graphical photoresist layer are sequentially formed on the substrate of the high-voltage element area; taking the patterned photoresist layer as a mask, etching the hard mask layer by a dry method to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad oxide layer, the buffer layer and the hard mask layer, and removing the residual photoresist layer; wet etching the bottom of the first groove by taking the hard mask layer as a mask, and exposing the surface of the substrate to form a second groove, wherein the second groove is positioned below the first groove and is communicated with the first groove; forming a high-voltage gate oxide layer in the first groove and the second groove; and sequentially removing the hard mask layer and the buffer layer to form the high-voltage device. The invention improves the working effect of the etching stop layer by adding the buffer layer, and simultaneously, the substrate is not exposed during the dry etching by the etching stop action of the buffer layer and the bottom oxide layer, thereby solving the silicon loss defect generated in the pattern area during the dry etching, improving the failure problem of a high-voltage device and improving the yield of the high-voltage device.
Drawings
FIG. 1 is a schematic structural diagram of a pattern transfer region during dry etching of a high-voltage device in the prior art;
fig. 2 is a schematic flow chart illustrating a method for forming a high voltage device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a substrate having a pad oxide layer, a buffer layer, and a hard mask layer formed thereon according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a photoresist layer formed on a substrate after being subjected to an imaging process according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram after dry etching and before removing the remaining photoresist layer according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram illustrating a structure after removing the remaining photoresist layer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram after wet etching according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram after a high voltage gate oxide layer is formed according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of the hard mask layer and the buffer layer after being removed according to an embodiment of the present invention.
Description of reference numerals:
in fig. 1:
a-silicon loss defects; 10-a silicon substrate; 21-pad bottom oxide layer; 22-a silicon nitride layer; 30-an initial photoresist layer;
in FIGS. 3-9:
100-a substrate; 101-HVNMOS region; 102-HVPMOS region; 110-shallow trench isolation structures; 210-a pad bottom oxide layer; 220-a buffer layer; 230-hard mask layer; 300-a photoresist layer; 310 — a first opening; 320-a second opening; 410-a first groove; 420-a second groove; 500-high voltage gate oxide.
Detailed Description
A method of forming a high voltage device and a high voltage device of the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 2 is a schematic flow chart of a method for forming a high-voltage device according to this embodiment. As shown in fig. 2, the present embodiment provides a method for forming a high voltage device, including the following steps:
step S1: providing a substrate, wherein the substrate comprises a high-voltage element area, and a pad oxide layer, a buffer layer, a hard mask layer and a graphical photoresist layer are sequentially formed on the substrate of the high-voltage element area;
step S2: taking the patterned photoresist layer as a mask, etching the hard mask layer by a dry method to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad oxide layer, the buffer layer and the hard mask layer, and removing the residual photoresist layer;
step S3: wet etching the bottom of the first groove by taking the hard mask layer as a mask, and exposing the surface of the substrate to form a second groove, wherein the second groove is positioned below the first groove and is communicated with the first groove;
step S4: forming a high-voltage gate oxide layer in the first groove and the second groove;
step S5: and sequentially removing the hard mask layer and the buffer layer to form the high-voltage device.
A method for forming a high voltage device according to the present embodiment is described in detail below with reference to fig. 2 to 9.
Fig. 3 is a schematic structural diagram of a substrate provided in this embodiment, on which an underlying oxide layer, a buffer layer, and a hard mask layer are formed. Fig. 4 is a schematic structural diagram of the photoresist layer of the present embodiment after being subjected to an imaging process. As shown in fig. 3-4, step S1 is performed first, a substrate 100 is provided, the substrate 100 includes a high voltage device region, and a pad oxide layer 210, a buffer layer 220, a hard mask layer 230 and a patterned photoresist layer 300 are sequentially formed on the substrate 100 in the high voltage device region.
The method specifically comprises the following steps:
as shown in fig. 3, in step S11, a substrate 100 is provided. The substrate 100 may be any substrate for supporting a component of a semiconductor integrated circuit, which may be a bare chip or a wafer processed by an epitaxial growth process, and particularly, the substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator (ge) substrate.
The substrate comprises a low-voltage element area, a storage element area, a medium-voltage element area and a high-voltage element area which are adjacently arranged. The low voltage element region, the memory element region, the medium voltage element region and the high voltage element region are isolated by an isolation structure, such as a Shallow Trench Isolation (STI) 110. The high-voltage element region may include an HVNMOS region 101 and an HVPMOS region 102 which are adjacently disposed, and an STI 110 is further disposed between the HVNMOS region 101 and the HVPMOS region 102, wherein the STI 110 is used to isolate the HVNMOS region 101 from the HVPMOS region 102, the HVNMOS region 101 is used to form an HVNMOS, and the HVPMOS region 102 is used to form an HVPMOS.
As shown in fig. 3, in step S12, an under-pad oxide layer 210 is formed on the substrate 100 in the high-voltage device region through a thermal growth process, and a buffer layer 220 and a hard mask layer 230 are further sequentially formed on the under-pad oxide layer 210 through a deposition process. The buffer layer 220 and the pad oxide layer 210 both play a role in stopping etching so as to avoid the silicon loss defect caused by etching the substrate in the subsequent dry etching. The pad oxide layer 210 covers at least the substrate of the high voltage device region, and in this embodiment, the pad oxide layer 210 covers the low voltage device region, the memory device region, the medium voltage device region, and the high voltage device region.
The material of the underlying oxide layer 210 is silicon oxide; the material of buffer layer 220 is silicon carbonitride, the material of hard mask layer 230 is silicon nitride, the thickness of buffer layer 220 is 100 a ± 10 a, it is preferred, the thickness of buffer layer 220 is 100 a, the thickness of hard mask layer 230 is 500 a ± 50 a, it is preferred, the thickness of hard mask layer 230 is 500 a, the thickness of pad bottom oxide layer 210 is 55 a ± 5 a, it is preferred, the thickness of pad bottom oxide layer 210 is 55 a.
As shown in fig. 4, in step S13, a photoresist layer 300 is formed on the hard mask layer 230, and a patterned photoresist layer 300 is formed through a photolithography process, where the patterned photoresist layer 300 has a first opening 310 and a second opening 320, the first opening 310 is located above the substrate 100 of the HVNMOS region 101, and the second opening 320 is located above the substrate 100 of the HVPMOS region 102.
Fig. 5 is a schematic structural diagram after the dry etching and before the removal of the remaining photoresist layer provided in this embodiment. Fig. 6 is a schematic structural diagram of the present embodiment after removing the remaining photoresist layer. As shown in fig. 5-6, step S2 is performed to dry etch the hard mask layer 230 by using the patterned photoresist layer 300 as a mask to form a first groove 410, wherein the depth of the first groove 410 is greater than the thickness of the hard mask layer 230 and less than the total thickness of the pad oxide layer 210, the buffer layer 220 and the hard mask layer 230, and the remaining photoresist layer 300 is removed.
Among the bottom oxide layer 210, the buffer layer 220, and the hard mask layer 230, the buffer layer 220 has the smallest etching rate, and the hard mask layer 230 has the largest etching rate. In this step, since the materials of the pad oxide layer 210, the buffer layer 220 and the hard mask layer 230 are different, and the etching rate of the hard mask layer 230 is the largest, the etching rate of the buffer layer 220 is low, so that the buffer layer 220 is not easily etched in a vertical direction so as to expose the pad oxide layer 210 thereunder, and meanwhile, since the etching rate of the pad oxide layer 210 is also lower than that of the hard mask layer 230, the substrate 100 is not exposed when the dry etching is finished, and thus, no silicon loss defect occurs.
The method comprises the following steps:
as shown in fig. 5, first, the patterned photoresist layer 300 is used as a mask to dry etch the hard mask layer 230, and the etching is stopped in the buffer layer 220, at this time, the bottom of the first groove 410 is located in the buffer layer 220; or, dry etching the hard mask layer 230 and the buffer layer 220 with the patterned photoresist layer 300 as a mask to expose the bottom oxide layer 210, where the bottom of the first groove 410 is located on the surface of the bottom oxide layer 210 or in the bottom oxide layer 210. In this step, the HVNMOS region 101 and the HVPMOS region 102 are both formed with the first recess 410, and the depth of the first recess 410 of the HVNMOS region 101 is the same as the depth of the first recess 410 of the HVPMOS region 102.
As shown in fig. 6, the remaining photoresist layer 300 is removed by an ashing process to expose the hard mask layer 230 outside the first recess 410.
Fig. 7 is a schematic structural diagram after wet etching according to this embodiment. As shown in fig. 7, step S3 is performed to wet etch the bottom of the first groove with the hard mask layer 230 as a mask and expose the surface of the substrate 100 to form a second groove, wherein the second groove is located below the first groove and is communicated with the first groove.
In this step, when the groove bottom of the first groove 410 is in the buffer layer 220, the hard mask layer 230 is used as a mask, and the buffer layer 220 and the underlying oxide layer 210 located at the groove bottom of the first groove 410 are wet-etched to expose the surface of the substrate 100, so as to form a second groove 420. When the groove bottom of the first groove 410 is on the surface of the bottom oxide layer 210 or in the bottom oxide layer 210, wet etching the bottom oxide layer 210 located at the groove bottom of the first groove 410 by using the hard mask layer 230 as a mask to expose the surface of the substrate 100, thereby forming a second groove 420, that is, the second groove 420 of the HVNMOS region 101 and the second groove 420 of the HVPMOS region 102 are formed, the first groove 410 of the HVNMOS region 101 is located above the second groove 420 of the HVNMOS region 101, and the first groove 410 of the HVNMOS region 101 is communicated with the second groove 420 of the HVNMOS region 101; the first groove 410 of the HVPMOS region 102 is located above the second groove 420 of the HVPMOS region 102, and the first groove 410 of the HVPMOS region 102 and the second groove 420 of the HVPMOS region 102 communicate. In this step, after the wet etching process, the substrate 100 at the bottom of the second groove 420 is not etched, so that the problem of silicon loss does not occur, and the problem of yield reduction caused by failure of the high-voltage device does not occur.
Fig. 8 is a schematic structural diagram after a high-voltage gate oxide layer is formed in the present embodiment. As shown in fig. 8, next, step S4 is performed to form a high voltage gate oxide 500 in the first recess 410 and the second recess 420. In detail, a high-voltage gate oxide layer 500 is formed in the second groove 420 through a deposition process, the second groove 420 and the first groove 410 are filled with the high-voltage gate oxide layer 500, and the thickness of the high-voltage gate oxide layer 500 is greater than the total thickness of the bottom oxide layer 210, the buffer layer 220 and the hard mask layer 230.
Fig. 9 is a schematic structural diagram of the hard mask layer and the buffer layer removed according to this embodiment. As shown in fig. 9, step S5 is performed to sequentially remove the hard mask layer 230 and the buffer layer 220, so as to form a high voltage device.
The method comprises the following steps: the hard mask layer 230 and the buffer layer 220 are sequentially removed, and then a polysilicon gate is formed on the high-voltage gate oxide layer 500 to form an HVMOS transistor, thereby forming a high-voltage device.
The embodiment provides a high-voltage device prepared by the method.
In summary, the present invention provides a method for forming a high voltage device and a high voltage device, the method for forming a high voltage device includes: providing a substrate, wherein the substrate comprises a high-voltage element area, and a pad oxide layer, a buffer layer, a hard mask layer and a graphical photoresist layer are sequentially formed on the substrate of the high-voltage element area; taking the patterned photoresist layer as a mask, etching the hard mask layer by a dry method to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad oxide layer, the buffer layer and the hard mask layer, and removing the residual photoresist layer; wet etching the bottom of the first groove by taking the hard mask layer as a mask, and exposing the surface of the substrate to form a second groove, wherein the second groove is positioned below the first groove and is communicated with the first groove; forming a high-voltage gate oxide layer in the first groove and the second groove; and sequentially removing the hard mask layer and the buffer layer to form the high-voltage device. The invention improves the working effect of the etching stop layer by adding the buffer layer, and simultaneously, the substrate is not exposed during the dry etching by the etching stop action of the buffer layer and the bottom oxide layer, thereby solving the silicon loss defect generated in the pattern area during the dry etching, improving the failure problem of a high-voltage device and improving the yield of the high-voltage device.
In addition, unless otherwise specified or indicated, the description of the terms "first", "second", and the like in the specification is only used for distinguishing various components, elements, steps, and the like in the specification, and is not used for representing a logical relationship, a sequential relationship, and the like between various components, elements, steps.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, the foregoing description is not intended to limit the invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (12)

1. A method for forming a high-voltage device is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a high-voltage element area, and a substrate oxide layer, a buffer layer, a hard mask layer and a graphical photoresist layer are sequentially formed on the substrate of the high-voltage element area;
taking the patterned photoresist layer as a mask, etching the hard mask layer by a dry method to form a first groove, wherein the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the pad oxide layer, the buffer layer and the hard mask layer, and removing the residual photoresist layer;
wet etching the bottom of the first groove by taking the hard mask layer as a mask, and exposing the surface of the substrate to form a second groove, wherein the second groove is positioned below the first groove and is communicated with the first groove;
forming a high-voltage gate oxide layer in the first groove and the second groove;
and sequentially removing the hard mask layer and the buffer layer to form the high-voltage device.
2. The method of claim 1, wherein an etching rate of the buffer layer is the smallest and an etching rate of the hard mask layer is the largest among the underlying oxide layer, the buffer layer, and the hard mask layer.
3. The method of claim 1, wherein providing a substrate including a high voltage device region, and sequentially forming a pad oxide layer, a buffer layer, a hard mask layer, and a patterned photoresist layer on the substrate in the high voltage device region comprises:
providing a substrate, wherein the substrate comprises a high-voltage element region, and the high-voltage element region comprises an HVNMOS region and an HVPMOS region;
forming a pad bottom oxide layer on the substrate of the high-voltage element region through a thermal growth process;
sequentially forming a buffer layer and a hard mask layer on the underlying oxide layer through a deposition process; and
and forming a photoresist layer on the hard mask layer, and forming a patterned photoresist layer through a photoetching process, wherein the patterned photoresist layer is provided with a first opening and a second opening, the first opening is positioned above the substrate of the HVNMOS region, and the second opening is positioned above the substrate of the HVPMOS region.
4. The method of claim 1, wherein the material of the underlying oxide layer is silicon oxide; the buffer layer is made of silicon carbonitride, and the hard mask layer is made of silicon nitride.
5. A method of forming a high-voltage device as claimed in any one of claims 1-4, characterized in that the thickness of the buffer layer is 100 a ± 10 a, the thickness of the hard mask layer is 500 a ± 50 a, and the thickness of the underlying oxide layer is 55 a ± 5 a.
6. The method for forming a high-voltage device according to claim 3, wherein the patterned photoresist layer is used as a mask, the hard mask layer is dry-etched to form a first groove, the depth of the first groove is greater than the thickness of the hard mask layer and less than the total thickness of the underlying oxide layer, the buffer layer and the hard mask layer, and removing the remaining photoresist layer specifically comprises:
etching the hard mask layer by a dry method by taking the patterned photoresist layer as a mask, and stopping etching in the buffer layer, wherein the bottom of the first groove is positioned in the buffer layer; and
and removing the residual photoresist layer through an ashing process to expose the hard mask layer on the outer side of the first groove.
7. The method according to claim 3, wherein the step of dry etching the hard mask layer by using the patterned photoresist layer as a mask to form a first groove, wherein a depth of the first groove is greater than a thickness of the hard mask layer and less than a total thickness of the pad oxide layer, the buffer layer and the hard mask layer, and the step of removing the remaining photoresist layer specifically comprises:
taking the patterned photoresist layer as a mask, etching the hard mask layer and the buffer layer by a dry method, and exposing the bottom oxide layer, wherein the bottom of the first groove is positioned on the surface of the bottom oxide layer or in the bottom oxide layer; and
and removing the residual photoresist layer through an ashing process to expose the hard mask layer outside the first groove.
8. The method for forming a high-voltage device according to claim 6, wherein the wet etching the bottom of the first groove with the hard mask layer as a mask to expose the surface of the substrate to form a second groove specifically comprises:
and wet etching the buffer layer and the substrate oxide layer positioned at the bottom of the first groove by using the hard mask layer as a mask to expose the surface of the substrate so as to form a second groove.
9. The method for forming a high-voltage device according to claim 7, wherein wet etching the bottom of the first recess with the hard mask layer as a mask to expose the surface of the substrate to form a second recess specifically comprises:
and etching the bottom oxide layer positioned at the bottom of the first groove by using the hard mask layer as a mask through a wet method to expose the surface of the substrate so as to form a second groove.
10. The method of forming a high voltage device according to claim 8 or 9, wherein the first recess includes a first recess of the HVNMOS region and a first recess of the HVPMOS region, the second recess includes a second recess of the HVNMOS region and a second recess of the HVPMOS region, the first recess of the HVNMOS region is located above the second recess of the HVNMOS region, and the first recess of the HVNMOS region and the second recess of the HVNMOS region are in communication; the first groove of the HVPMOS region is located above the second groove of the HVPMOS region, and the first groove of the HVPMOS region and the second groove of the HVPMOS region are communicated.
11. The method of forming a high voltage device as claimed in claim 1 wherein forming a high voltage gate oxide layer in said first and second recesses specifically comprises:
and forming a high-voltage gate oxide layer in the second groove through a deposition process, wherein the high-voltage gate oxide layer fills the second groove and the first groove, and the thickness of the high-voltage gate oxide layer is greater than the total thickness of the bottom oxide layer, the first hard mask layer and the hard mask layer.
12. A high voltage device prepared by the method for forming a high voltage device of claim 1.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115332060A (en) * 2022-10-13 2022-11-11 合肥晶合集成电路股份有限公司 Manufacturing method of grid structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030160280A1 (en) * 2002-02-27 2003-08-28 Akira Yoshino Nonvolatile semiconductor memory device, manufacturing method thereof, and operating method thereof
US20060113629A1 (en) * 2004-11-30 2006-06-01 Andy Wei Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate
CN101409261A (en) * 2007-10-09 2009-04-15 上海华虹Nec电子有限公司 Technological method for forming high voltage gate oxygen structure
CN101572252A (en) * 2008-04-28 2009-11-04 中芯国际集成电路制造(北京)有限公司 Etching stopping layer, semiconductor device with through hole and method for forming same two
CN103730406A (en) * 2012-10-11 2014-04-16 中芯国际集成电路制造(上海)有限公司 Method for preparing dual damascene structure
CN104733373A (en) * 2013-12-19 2015-06-24 中芯国际集成电路制造(上海)有限公司 Manufacturing method for semiconductor component
CN105097657A (en) * 2014-05-09 2015-11-25 中芯国际集成电路制造(上海)有限公司 Semiconductor structure forming method
CN106128951A (en) * 2016-06-30 2016-11-16 上海华力微电子有限公司 Improve the method for silicon substrate integrity in flash array district oxygen pad layer etching process
US20180190537A1 (en) * 2016-12-30 2018-07-05 Globalfoundries Singapore Pte. Ltd. Methods for removal of hard mask
CN109755126A (en) * 2017-11-07 2019-05-14 中芯国际集成电路制造(上海)有限公司 The manufacturing method of semiconductor devices

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030160280A1 (en) * 2002-02-27 2003-08-28 Akira Yoshino Nonvolatile semiconductor memory device, manufacturing method thereof, and operating method thereof
US20060113629A1 (en) * 2004-11-30 2006-06-01 Andy Wei Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate
CN101409261A (en) * 2007-10-09 2009-04-15 上海华虹Nec电子有限公司 Technological method for forming high voltage gate oxygen structure
CN101572252A (en) * 2008-04-28 2009-11-04 中芯国际集成电路制造(北京)有限公司 Etching stopping layer, semiconductor device with through hole and method for forming same two
CN103730406A (en) * 2012-10-11 2014-04-16 中芯国际集成电路制造(上海)有限公司 Method for preparing dual damascene structure
CN104733373A (en) * 2013-12-19 2015-06-24 中芯国际集成电路制造(上海)有限公司 Manufacturing method for semiconductor component
CN105097657A (en) * 2014-05-09 2015-11-25 中芯国际集成电路制造(上海)有限公司 Semiconductor structure forming method
CN106128951A (en) * 2016-06-30 2016-11-16 上海华力微电子有限公司 Improve the method for silicon substrate integrity in flash array district oxygen pad layer etching process
US20180190537A1 (en) * 2016-12-30 2018-07-05 Globalfoundries Singapore Pte. Ltd. Methods for removal of hard mask
CN109755126A (en) * 2017-11-07 2019-05-14 中芯国际集成电路制造(上海)有限公司 The manufacturing method of semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115332060A (en) * 2022-10-13 2022-11-11 合肥晶合集成电路股份有限公司 Manufacturing method of grid structure
CN115332060B (en) * 2022-10-13 2022-12-16 合肥晶合集成电路股份有限公司 Manufacturing method of grid structure

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