CN110137260B - Field oxide layer isolation structure of LDMOS transistor and preparation method thereof - Google Patents

Field oxide layer isolation structure of LDMOS transistor and preparation method thereof Download PDF

Info

Publication number
CN110137260B
CN110137260B CN201910435315.1A CN201910435315A CN110137260B CN 110137260 B CN110137260 B CN 110137260B CN 201910435315 A CN201910435315 A CN 201910435315A CN 110137260 B CN110137260 B CN 110137260B
Authority
CN
China
Prior art keywords
oxide layer
isolation structure
layer
field oxide
ldmos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910435315.1A
Other languages
Chinese (zh)
Other versions
CN110137260A (en
Inventor
吴亚贞
刘长振
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201910435315.1A priority Critical patent/CN110137260B/en
Publication of CN110137260A publication Critical patent/CN110137260A/en
Application granted granted Critical
Publication of CN110137260B publication Critical patent/CN110137260B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a field oxide layer isolation structure of an LDMOS transistor and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate; sequentially forming a first oxide layer and a second oxide layer on the semiconductor substrate; forming a patterned photoresist layer on the second oxide layer; and taking the patterned photoresist layer as a mask, carrying out an etching process on the second oxide layer, and removing the patterned photoresist layer to form a field oxide layer isolation structure of the LDMOS transistor. The field oxide isolation structure of the existing ONO lamination is replaced by the laminated field oxide isolation structure consisting of the first oxide layer and the second oxide layer, so that the influence of the field oxide isolation structure on the electrical characteristics of the LDMOS transistor is reduced. Furthermore, a protective layer is formed on the second oxide layer to reduce the damage of the subsequent ion implantation process, cleaning process and the like to the field oxide layer isolation structure.

Description

Field oxide layer isolation structure of LDMOS transistor and preparation method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a field oxide layer isolation structure of an LDMOS transistor and a preparation method thereof.
Background
The BCD process is a process of fabricating a Bipolar Junction Transistor (BJT), a Complementary Metal Oxide Semiconductor (CMOS), and a Diffused Metal Oxide Semiconductor (DMOS) on the same chip. In the process of fabricating an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor by using a BCD process, a Field plate is usually used to reduce an electric Field and increase a voltage, and as shown in fig. 1, the Field plate is extended by a poly-crystal gate to cross over a Field Oxide (Field Oxide, FOX, Field Oxide for short). An Oxide-Nitride-Oxide (ONO) stacked structure is often used as a field Oxide isolation structure of the LDMOS transistor to solve the problem of damage to the surface of the semiconductor substrate due to an excessively thin Oxide layer between the semiconductor substrate and the Nitride during etching of the field Oxide isolation structure.
However, this structure causes an adaptive shift in the detected electrical characteristics of the drain current, drain voltage, etc., which affects the electrical characteristics of the LDMOS transistor.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a field oxide isolation structure of an LDMOS transistor and a preparation method thereof, which can reduce the influence of the field oxide isolation structure on the electrical characteristics of the LDMOS transistor.
In order to solve the technical problem, the invention provides a preparation method of a field oxide isolation structure of an LDMOS transistor, which comprises the following steps:
providing a semiconductor substrate;
sequentially forming a first oxide layer and a second oxide layer on the semiconductor substrate;
forming a patterned photoresist layer on the second oxide layer; and
and taking the patterned photoresist layer as a mask, carrying out an etching process on the second oxide layer, stopping etching on the first oxide layer with partial depth, and removing the patterned photoresist layer to form a field oxide layer isolation structure of the LDMOS transistor.
Optionally, the material of the first oxide layer includes silicon dioxide, and the thickness of the silicon dioxide is
Figure BDA0002070342140000021
Optionally, the material of the second oxide layer includes an ethyl orthosilicate layer with a thickness of
Figure BDA0002070342140000023
Figure BDA0002070342140000022
Optionally, after removing the patterned photoresist layer, the method further includes:
and forming a protective layer on the second oxide layer, wherein the protective layer at least covers the upper surface and the side wall of the second oxide layer.
Further, the protection layer includes a high temperature oxide layer for preventing a subsequent process from physically or chemically damaging the field oxide isolation structure.
Further, the thickness of the protective layer is
Figure BDA0002070342140000024
The invention also provides a field oxide isolation structure of the LDMOS transistor, which comprises a first oxide layer and a second oxide layer, wherein the first oxide layer and the second oxide layer are sequentially formed on the semiconductor substrate.
Optionally, the field oxide isolation structure further comprises a protective layer, wherein the protective layer covers the upper surface and the side wall of the second oxide layer and is used for preventing subsequent processes from physical damage or chemical damage to the field oxide isolation structure.
Optionally, the material of the first oxide layer includes silicon dioxide, and the thickness of the silicon dioxide is
Figure BDA0002070342140000025
Optionally, the material of the second oxide layer comprises an ethyl orthosilicate layer with a thickness of
Figure BDA0002070342140000026
Figure BDA0002070342140000027
Compared with the prior art, the method has the following beneficial effects:
according to the field oxide isolation structure of the LDMOS transistor and the preparation method thereof, in the preparation method of the field oxide isolation structure of the LDMOS transistor, the existing field oxide isolation structure of an ONO lamination layer is replaced by the laminated field oxide isolation structure consisting of a first oxide layer and a second oxide layer, so that the influence of the field oxide isolation structure on the electrical characteristics of the LDMOS transistor is reduced. Furthermore, a protective layer is formed on the second oxide layer to reduce the damage of the subsequent ion implantation process, cleaning process and the like to the field oxide layer isolation structure.
Drawings
FIG. 1 is a schematic cross-sectional view of an LDMOS transistor;
fig. 2 is a schematic flowchart illustrating a method for fabricating a field oxide isolation structure of an LDMOS transistor according to an embodiment of the invention;
fig. 3 is a schematic cross-sectional view of an LDMOS transistor according to an embodiment of the invention.
Description of reference numerals:
in fig. 1:
10-a semiconductor substrate; 20-field oxide isolation structures; 21-a first oxide layer; 22-a nitride layer; 23-a second oxide layer;
in fig. 3:
100-a semiconductor substrate;
200-field oxide isolation structures; 210-a first oxide layer; 220-a second oxide layer; 230-a protective layer;
300-field plate;
410-a source; 420-drain electrode.
Detailed Description
As shown in fig. 1, a method for manufacturing a field oxide isolation structure of an LDMOS transistor in the prior art includes the following steps:
step S11: providing a semiconductor substrate;
step S12: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate;
step S13: forming a patterned photoresist on the second oxide layer;
step S14: and taking the patterned photoresist as a mask, and sequentially etching the second oxide layer, the nitride layer and the first oxide layer to form a field oxide layer isolation structure of the LDMOS transistor.
The field oxide isolation structure of the ONO lamination formed by the prior art has the problem of adaptive transfer of electrical characteristics such as drain current, drain voltage and the like during testing, and the inventor researches and discovers that the problem is probably caused because the field oxide isolation structure of the ONO lamination traps some charges during testing, so that the drain current and the drain voltage are reduced, and the electrical characteristics of the LDMOS transistor are influenced.
Based on the research, in the preparation method of the field oxide isolation structure of the LDMOS transistor, the existing field oxide isolation structure of the ONO lamination is replaced by the laminated field oxide isolation structure consisting of the first oxide layer and the second oxide layer, so that the influence of the field oxide isolation structure on the electrical characteristics of the LDMOS transistor is reduced. Furthermore, a protective layer is formed on the second oxide layer to reduce the damage of the subsequent ion implantation process, cleaning process and the like to the field oxide layer isolation structure.
The field oxide isolation structure of the LDMOS transistor and the method for fabricating the same according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
The present embodiment provides a method for manufacturing a field oxide isolation structure of an LDMOS transistor. Fig. 2 is a schematic flow chart of a method for manufacturing a field oxide isolation structure of an LDMOS transistor according to this embodiment. As shown in fig. 2, the preparation method comprises the following steps:
step S21: providing a semiconductor substrate;
step S22: sequentially forming a first oxide layer and a second oxide layer on the semiconductor substrate;
step S23: forming a patterned photoresist layer on the second oxide layer; and
step S24: and taking the patterned photoresist layer as a mask, carrying out an etching process on the second oxide layer, stopping etching on the first oxide layer with partial depth, and removing the patterned photoresist layer to form a field oxide layer isolation structure of the LDMOS transistor.
A method for fabricating a field oxide isolation structure of an LDMOS transistor disclosed in this embodiment is described in more detail with reference to fig. 2 and fig. 3.
As shown in fig. 3, step S21 is first performed to provide a semiconductor substrate 100. The semiconductor substrate 100 may provide an operation platform for a subsequent process, and may be any substrate known to those skilled in the art for supporting a component of a semiconductor integrated circuit, such as a bare die, or a wafer processed by an epitaxial growth process, and in detail, the semiconductor substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator (ge) substrate. In addition, an active region may be defined on the semiconductor substrate 100. For simplicity, the semiconductor substrate 100 is represented here with only a blank. A first well region (not shown) and a second well region (not shown) are formed in the semiconductor substrate 100, and the first well region and the second well region are horizontally formed below the surface of the semiconductor substrate 100. The first well region has a first doping type (N-type or P-type), and the second well region has a second doping type (P-type or N-type). As an example, when the first doping type is N-type, the second doping type is P-type; on the contrary, when the first doping type is P-type, the second doping type is N-type. The first well region and the second well region are adjacently arranged.
Next, step S22 is performed to sequentially form a first oxide layer 210 and a second oxide layer 220 on the semiconductor substrate 100.
Specifically, a first oxide layer 210 and a second oxide layer 220 are sequentially deposited on the semiconductor substrate 100. The first oxide layer 210 is made of silicon dioxide, for example, and has a thickness of
Figure BDA0002070342140000051
Figure BDA0002070342140000052
The material of the second oxide layer 220 is, for example, a tetraethyl orthosilicate (TEOS) layer, and the thickness thereof is, for example
Figure BDA0002070342140000053
Next, step S23 is performed to form a patterned photoresist layer (not shown) on the second oxide layer 220. The patterned photoresist is used as a mask for forming a subsequent field oxide isolation structure.
Specifically, the method comprises the following steps: first, a photoresist layer is coated on the second oxide layer 220; then, the photoresist layer is patterned by exposure and development to cover the photoresist layer at the second oxide layer 220 where the field oxide isolation structure is formed and to form an opening outside the second oxide layer 220 where the field oxide isolation structure is formed. And then, performing step S24, using the patterned photoresist layer as a mask, performing an etching process on the second oxide layer 220, stopping etching on the first oxide layer 210 with a partial depth, and removing the patterned photoresist layer to form a field oxide isolation structure of the LDMOS transistor.
Specifically, the method comprises the following steps: firstly, the second oxide layer 220 except for the field oxide isolation structure is removed by a dry etching process and/or a wet etching process, and etching is stopped on the first oxide layer 210 with a partial depth. And then, removing the patterned photoresist layer. Next, a protection layer 230 is formed on the second oxide layer 220, wherein the protection layer 230 is, for example, a High Temperature Oxide (HTO) layer, and the protection layer covers at least an upper surface (i.e., a surface of the second oxide layer 220 facing away from the semiconductor substrate) and sidewalls of the second oxide layer 220. The protective layer230 is, for example, as
Figure BDA0002070342140000061
The protection layer 230 is used to prevent physical damage or chemical damage to the field oxide isolation structure 200 due to a subsequent process. For example, physical damage to the field oxide isolation structure 200 by a subsequent ion implantation process, chemical damage to the field oxide isolation structure 200 by a cleaning process, and the like are prevented. In the embodiment, the field oxide isolation structure of the existing ONO lamination is replaced by the field oxide isolation structure of the lamination consisting of the first oxide layer and the second oxide layer, so that the phenomenon that the field oxide isolation structure captures some charges during detection is avoided, and the influence of the field oxide isolation structure on the electrical characteristics of the LDMOS transistor is reduced.
After forming the field oxide isolation structure of the LDMOS transistor, the method further comprises the following steps: a field plate 300 is formed on the semiconductor substrate 100 at one side of the field oxide isolation structure, and the field plate 300 partially covers the oxide isolation structure 200, wherein the field plate 300 is, for example, a polysilicon gate. (ii) a
Forming source/ drain electrodes 410, 420 on both sides of the field oxide isolation structure 200 and field plate 300;
the first oxide layer 210 is etched to expose the source/ drain 410, 420 to form an LDMOS transistor.
Referring to fig. 3, the present embodiment further provides a field oxide isolation structure of an LDMOS transistor, which includes a first oxide layer 210, a second oxide layer 220 and a protection layer 230 sequentially formed on a semiconductor substrate 100, wherein the first oxide layer 210 is made of, for example, silicon dioxide, and has a thickness, for example, of
Figure BDA0002070342140000071
The second oxide layer 220 is made of, for example, ethyl orthosilicate and has a thickness of, for example
Figure BDA0002070342140000072
The thickness of the protective layer 230 is, for example
Figure BDA0002070342140000073
The protection layer 230 covers the upper surface and the sidewall of the second oxide layer 220, and the protection layer 230 is used for preventing the physical damage or the chemical damage of the subsequent process to the field oxide isolation structure 200.
In summary, in the method for manufacturing the field oxide isolation structure of the LDMOS transistor, the existing field oxide isolation structure of the ONO stack is replaced with the stacked field oxide isolation structure composed of the first oxide layer and the second oxide layer, so as to reduce the influence of the field oxide isolation structure on the electrical characteristics of the LDMOS transistor. Furthermore, a protective layer is formed on the second oxide layer to reduce the damage of the subsequent ion implantation process, cleaning process and the like to the field oxide layer isolation structure.
In addition, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification is only used for distinguishing various components, elements, steps and the like in the specification, and is not used for representing logical relationships or sequential relationships among the various components, elements, steps and the like. It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are within the scope of the technical solution of the present invention, unless the technical essence of the present invention is not departed from the content of the technical solution of the present invention.

Claims (9)

1. A preparation method of a field oxide isolation structure of an LDMOS transistor is characterized by comprising the following steps:
providing a semiconductor substrate;
sequentially forming a first oxide layer and a second oxide layer on the semiconductor substrate;
forming a patterned photoresist layer on the second oxide layer; and
taking the patterned photoresist layer as a mask, carrying out an etching process on the second oxide layer, stopping etching on the first oxide layer with a partial depth, and removing the patterned photoresist layer;
and forming a protective layer on the second oxide layer, wherein the protective layer at least covers the upper surface and the side wall of the second oxide layer so as to form a field oxide layer isolation structure of the LDMOS transistor.
2. The method of claim 1, wherein the material of the first oxide layer comprises silicon dioxide having a thickness of
Figure FDA0003552649510000011
3. The method of claim 1, wherein the material of the second oxide layer comprises an ethyl orthosilicate layer having a thickness of
Figure FDA0003552649510000012
4. The method of claim 1, wherein the protection layer comprises a high temperature oxide layer for preventing physical or chemical damage to the field oxide isolation structure from subsequent processes.
5. The method of claim 4, wherein the protective layer has a thickness of
Figure FDA0003552649510000013
6. A field oxide isolation structure of an LDMOS transistor is prepared by the preparation method of the field oxide isolation structure of the LDMOS transistor, which is characterized by comprising a first oxide layer and a second oxide layer, wherein the first oxide layer and the second oxide layer are sequentially formed on a semiconductor substrate.
7. The field oxide isolation structure of an LDMOS transistor set forth in claim 6 further comprising a protective layer covering the upper surface and sidewalls of said second oxide layer, said protective layer being for preventing physical or chemical damage to said field oxide isolation structure by subsequent processes.
8. The field oxide isolation structure of an LDMOS transistor of claim 7 wherein the material of the first oxide layer comprises silicon dioxide having a thickness of
Figure FDA0003552649510000014
9. The field oxide isolation structure of an LDMOS transistor of claim 7 wherein the material of the second oxide layer comprises a layer of ethyl orthosilicate having a thickness of
Figure FDA0003552649510000021
CN201910435315.1A 2019-05-23 2019-05-23 Field oxide layer isolation structure of LDMOS transistor and preparation method thereof Active CN110137260B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910435315.1A CN110137260B (en) 2019-05-23 2019-05-23 Field oxide layer isolation structure of LDMOS transistor and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910435315.1A CN110137260B (en) 2019-05-23 2019-05-23 Field oxide layer isolation structure of LDMOS transistor and preparation method thereof

Publications (2)

Publication Number Publication Date
CN110137260A CN110137260A (en) 2019-08-16
CN110137260B true CN110137260B (en) 2022-05-10

Family

ID=67572759

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910435315.1A Active CN110137260B (en) 2019-05-23 2019-05-23 Field oxide layer isolation structure of LDMOS transistor and preparation method thereof

Country Status (1)

Country Link
CN (1) CN110137260B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111403279B (en) * 2020-04-29 2023-03-28 上海华虹宏力半导体制造有限公司 Method for forming semiconductor device
CN111584361A (en) * 2020-05-26 2020-08-25 上海华虹宏力半导体制造有限公司 Method for forming semiconductor device
JP7398339B2 (en) * 2020-05-29 2023-12-14 ルネサスエレクトロニクス株式会社 semiconductor equipment
CN111710714B (en) * 2020-06-23 2022-08-23 杰华特微电子股份有限公司 Manufacturing method of field plate and semiconductor device
CN111785639B (en) * 2020-08-26 2024-02-02 上海华虹宏力半导体制造有限公司 LDMOS transistor and preparation method thereof
CN111785640A (en) * 2020-08-26 2020-10-16 上海华虹宏力半导体制造有限公司 Method for adjusting angle of oxide field plate in LDMOS transistor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101022109A (en) * 2006-02-15 2007-08-22 三菱电机株式会社 Semiconductor device and method of manufacturing the same
US10283622B1 (en) * 2018-01-16 2019-05-07 Globalfoundries Singapore Pte. Ltd. Extended drain transistor on a crystalline-on-insulator substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456451B2 (en) * 2005-09-13 2008-11-25 United Microelectronics Corp. Ultra high voltage MOS transistor device
US9484454B2 (en) * 2008-10-29 2016-11-01 Tower Semiconductor Ltd. Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101022109A (en) * 2006-02-15 2007-08-22 三菱电机株式会社 Semiconductor device and method of manufacturing the same
US10283622B1 (en) * 2018-01-16 2019-05-07 Globalfoundries Singapore Pte. Ltd. Extended drain transistor on a crystalline-on-insulator substrate

Also Published As

Publication number Publication date
CN110137260A (en) 2019-08-16

Similar Documents

Publication Publication Date Title
CN110137260B (en) Field oxide layer isolation structure of LDMOS transistor and preparation method thereof
US20090096036A1 (en) Semiconductor device and method of manufacturing the same
CN110517957B (en) Field oxide layer and forming method thereof
US10103175B2 (en) Fin-shaped structure
US9859147B2 (en) Fin structure cutting process
US11581405B2 (en) Methods, devices, and systems related to forming semiconductor power devices with a handle substrate
CN111403279B (en) Method for forming semiconductor device
US10469041B2 (en) Gallium nitride (GaN) power amplifiers (PA) with angled electrodes and 100 CMOS and method for producing the same
US10680074B2 (en) Tunable breakdown voltage RF FET devices
US11764060B2 (en) Field-effect transistors with a body pedestal
US9627482B2 (en) Reduced current leakage semiconductor device
CN115084030A (en) Forming method of high-voltage device and high-voltage device
US8822296B2 (en) Use of plate oxide layers to increase bulk oxide thickness in semiconductor devices
US10680065B2 (en) Field-effect transistors with a grown silicon-germanium channel
US10304679B2 (en) Method of fabricating a mask
US10074650B2 (en) Deep trench isolation for RF devices on SOI
CN111785639A (en) LDMOS transistor and preparation method thereof
US9349748B2 (en) Method for forming deep trench isolation for RF devices on SOI
US11605649B2 (en) Switches in bulk substrate
US20230135889A1 (en) Integrated circuit device with improved oxide edging
CN111477590B (en) Grid manufacturing method
CN110571148B (en) Processing method of power semiconductor device and power semiconductor device
US10170601B2 (en) Structure and formation method of semiconductor device with bipolar junction transistor
CN113140464A (en) Semiconductor device and method for manufacturing the same
KR100730476B1 (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant