CN113140464A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113140464A CN113140464A CN202110688897.1A CN202110688897A CN113140464A CN 113140464 A CN113140464 A CN 113140464A CN 202110688897 A CN202110688897 A CN 202110688897A CN 113140464 A CN113140464 A CN 113140464A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
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- 238000002955 isolation Methods 0.000 claims description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 9
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: the semiconductor device comprises a substrate, a first side wall and a second side wall. And before forming the second side wall, covering the surfaces of the substrate, the grid and the first side wall with a sacrificial oxide layer with a set thickness. The sacrificial oxide layer is used for protecting the substrate, the grid and the first side wall, so that the problems of appearance depression, channel shortening, leakage current and the like caused by erosion in the photoresist removing and cleaning process are avoided, and the performance and reliability of the device are improved. In addition, the set thickness of the sacrificial oxide layer is relatively thin, so that accurate injection can be realized by matching with an automatic ion injection control system in the process of executing ion injection, and the injection effect is not influenced. In addition, the sacrificial oxide layer will be oxidized and thinned gradually during the ion implantation process, and the sacrificial oxide layer will be removed during the photoresist removing process. Therefore, a step for removing the sacrificial oxide layer is not required to be independently executed, the operation is simple, and the cost is low.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor device and a preparation method thereof.
Background
A transistor (transistor) has a plurality of functions such as detection, rectification, amplification, switching, voltage stabilization, signal modulation, and the like, and is one of important component devices in an integrated circuit. In the process of manufacturing the transistor, as shown in fig. 1, a gate 11 and a sidewall 12 covering a sidewall of the gate 11 are formed on a substrate 10. When the sidewall 12 is formed by etching, the oxide layer on the surface of the substrate 10 is removed, so that the substrate 10 is exposed. Under the oxidation action of air, a thin natural oxide layer is formed on the surface of the substrate 10. Subsequently, when forming the lightly doped drain structure LDD, a patterned photoresist layer is formed on the substrate 10, and after ion implantation, the patterned photoresist layer is removed by cleaning. In the cleaning process, as shown in fig. 2, not only the native oxide layer on the surface of the substrate 10 but also a part of the thickness of the substrate 10 and the sidewall 12 are removed. P shown in fig. 2 is a defect after the substrate 10 and the sidewall 12 are etched. In the substrate 10, the locations where the source and drain electrodes are formed are consumed greatly, which may seriously affect the speed deviation of the device and the occurrence of leakage current. In addition, the thinning of the side wall 12 can cause the channel length of the device to be shortened, so that the mismatch of the whole device is poor. Meanwhile, the shallow trench isolation STI is also consumed, which may cause the isolation effect to be deteriorated and the device reliability to be reduced.
Therefore, a new method for manufacturing a semiconductor device is needed to solve the above problems and improve device performance and reliability.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which are used for relieving the problem that a substrate and a side wall are corroded.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate, wherein a grid electrode is formed on the substrate;
forming a first side wall, wherein the first side wall covers the side wall of the grid;
forming a sacrificial oxide layer with a set thickness, wherein the sacrificial oxide layer covers the substrate, the grid and the first side wall;
forming a patterned photoresist layer, wherein the patterned photoresist layer shields the grid electrode and a part of the substrate and exposes a part of the sacrificial oxide layer on the substrate connected with the first side wall;
performing a first ion implantation process on the substrate by taking the patterned photoresist layer and the first side wall as barriers to form a lightly doped drain structure in the substrate on two sides of the grid;
removing the patterned photoresist layer and simultaneously removing the sacrificial oxide layer;
and forming a second side wall, wherein the second side wall covers the first side wall.
Optionally, in the preparation method of the semiconductor device, the thickness range of the sacrificial oxide layer is as follows: 40 to 60 angstroms.
Optionally, in the preparation method of the semiconductor device, the material of the sacrificial oxide layer includes tetraethoxysilane.
Optionally, in the method for manufacturing a semiconductor device, a shallow trench isolation structure is further formed in the substrate, and the sacrificial oxide layer covers the shallow trench isolation structure.
Optionally, in the preparation method of the semiconductor device, the first sidewall includes a first oxide layer and a first nitride layer, and the first oxide layer and the first nitride layer sequentially cover a sidewall of the gate.
Optionally, in the preparation method of the semiconductor device, the second sidewall includes an ethyl orthosilicate layer and a second nitride layer, and the ethyl orthosilicate layer and the second nitride layer sequentially cover the first sidewall.
Optionally, in the method for manufacturing a semiconductor device, a second oxide layer is further formed between the substrate and the gate.
Optionally, in the method for manufacturing a semiconductor device, after forming the second sidewall, the method for manufacturing a semiconductor device further includes:
and performing a second ion implantation process on the substrate by taking the first side wall and the second side wall as barriers to form a source electrode and a drain electrode in the substrate at two sides of the grid electrode.
Optionally, in the preparation method of the semiconductor device, the patterned photoresist layer is removed by wet cleaning, and the sacrificial oxide layer is consumed and removed at the same time.
Based on the same inventive concept, the present invention also provides a semiconductor device, comprising:
a substrate, wherein a grid electrode is formed on the substrate;
the first side wall covers the side wall of the grid;
a second side wall covering the first side wall;
before the second side wall is formed, sacrificial oxide layers with set thickness are covered on the surfaces of the substrate, the grid and the first side wall.
In summary, the present invention provides a semiconductor device and a method for manufacturing the same, wherein the method comprises: providing a substrate, wherein a grid electrode is formed on the substrate; forming a first side wall, wherein the first side wall covers the side wall of the grid; forming a sacrificial oxide layer with a set thickness for protecting the substrate, the grid and the first side wall and avoiding erosion in the subsequent photoresist removing process; forming a patterned photoresist layer, wherein the patterned photoresist layer shields the grid electrode and a part of the substrate and exposes a part of the sacrificial oxide layer on the substrate connected with the first side wall; performing a first ion implantation process on the substrate by taking the patterned photoresist layer and the first side wall as barriers to form a lightly doped drain structure in the substrate on two sides of the grid; removing the patterned photoresist layer and simultaneously removing the sacrificial oxide layer; and forming a second side wall, wherein the second side wall covers the first side wall.
The sacrificial oxide layer is set to be thin, so that accurate injection can be achieved by matching with an automatic ion injection control system in the process of executing ion injection, and the injection effect is not affected. And in the ion implantation process, the sacrificial oxide layer can be naturally oxidized and gradually thinned, and in addition, the sacrificial oxide layer can be removed in the process of cleaning and removing the patterned photoresist layer. Therefore, the sacrificial oxide layer with a set thickness is arranged, so that the problems of appearance depression, leakage current, channel shortening and the like caused by erosion of the substrate, the grid and the first side wall in the photoresist removing and cleaning process are solved, and the performance and the reliability of the device are improved. In addition, the sacrificial oxide layer is removed through the links of natural oxidation and photoresist removal cleaning, a step for removing the sacrificial oxide layer does not need to be independently executed, and the method is simple to operate and low in cost.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure in the prior art;
FIG. 2 is a schematic illustration of a deficiency in the prior art;
fig. 3 is a flowchart of a method of manufacturing a semiconductor device of an embodiment of the present invention;
fig. 4-12 are schematic views of semiconductor structures at various steps in a method of fabricating a semiconductor device according to an embodiment of the present invention.
Wherein the reference numerals are:
10-a substrate; 11-a gate; 12-side walls; p-pits;
100-a substrate; 101-a gate; 102-shallow trench isolation; 103-a second oxide layer; 104 a-a first oxide layer; 104 b-a first nitride layer; 104-a first side wall; 105-a sacrificial oxide layer; 106-patterning a photoresist layer; 107-lightly doped drain structure; 108 a-ethyl orthosilicate layer; 108 b-a second nitride layer; 108-a second side wall; m-a medium voltage device region; an L-low voltage device region; an S-source electrode; and D-a drain electrode.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently. It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
To solve the above technical problem, the present embodiment provides a method for manufacturing a semiconductor device, referring to fig. 3, including:
step one S10: a substrate is provided, and a grid electrode is formed on the substrate.
Step two S20: and forming a first side wall, wherein the first side wall covers the side wall of the grid.
Step three S30: forming a sacrificial oxide layer with a set thickness, wherein the sacrificial oxide layer covers the substrate, the grid and the first side wall;
step four S40: forming a patterned photoresist layer, wherein the patterned photoresist layer shields the grid electrode and a part of the substrate and exposes a part of the sacrificial oxide layer on the substrate connected with the first side wall;
step five S50: performing a first ion implantation process on the substrate by taking the patterned photoresist layer and the first side wall as barriers to form a lightly doped drain structure in the substrate on two sides of the grid;
step six S60: removing the patterned photoresist layer and simultaneously removing the sacrificial oxide layer;
step seven S70: and forming a second side wall, wherein the second side wall covers the first side wall.
The following describes a method for manufacturing the semiconductor device with reference to fig. 4-12 of the specification:
step one S10: referring to fig. 4, a substrate 100 is provided, and a gate 101 is formed on the substrate 100.
The substrate 100 may be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a die, or a wafer processed by an epitaxial growth process. Optionally, the substrate 100 includes a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate.
Before the gate 101 is formed, a shallow trench isolation structure 102 is formed in the substrate 100 to define an active region, and the active region is divided into at least one of a high voltage device region, a medium voltage device region, and a low voltage device region. The active region illustrated in fig. 1 includes a medium voltage device region M and a low voltage device region L. After the preparation of the shallow trench isolation structure 102 is completed, ion doping is performed on the substrate 100 to form a P-well region or an N-well region, or a dual-well region. Then, a second oxide layer 103 is deposited on the surface of the substrate 100. The second oxide layer 103 serves to protect the substrate 100 from being damaged in a subsequent manufacturing process. Optionally, the second oxide layer 103 is formed by an atomic layer deposition process, a thermal oxidation process, or the like. The material of the second oxide layer 103 includes silicon oxide.
And depositing a polysilicon layer on the second oxide layer 103, and etching to form the gate 101. Optionally, the gate 101 is formed by a dry etching process.
Step two S20: referring to fig. 5 to 6, a first sidewall 104 is formed, and the first sidewall 104 covers the sidewall of the gate 101.
Referring to fig. 5, a first oxide layer 104a is deposited on the surface of the second oxide layer 103 and the surface of the gate 101, and then a first nitride layer 104b is deposited. Optionally, the material of the first oxide layer 104a includes silicon oxide, and the material of the first nitride layer 104b includes silicon nitride. The deposition method is not limited in this embodiment. After the first oxide layer 104a and the first nitride layer 104b are formed, referring to fig. 6, a dry etching process is used to remove a portion of the first oxide layer 104a, a portion of the first nitride layer 104b, and a portion of the second oxide layer 103 on the substrate surface, so as to retain a portion of the second oxide layer 103 simultaneously contacting the gate 101 and the substrate 100, and the first oxide layer 104a and the first nitride layer 104b covering the sidewall of the gate 101. The first oxide layer 104a and the first nitride layer 104b serve as a first sidewall 104 of the gate 101.
Step three S30: referring to fig. 7, a sacrificial oxide layer 105 with a predetermined thickness is formed, and the sacrificial oxide layer 105 covers the substrate 100, the gate 101 and the first sidewall 104.
The thickness range of the sacrificial oxide layer 105 is: 40 to 60 angstroms. Optionally 40 angstroms, 50 angstroms or 60 angstroms. The range of 40-60 angstroms is thin in film deposition, but has a certain barrier effect on subsequent photoresist removal cleaning, so that the shapes of the substrate 100 and the first side wall 104 are protected, and the photoresist can be consumed by self in a natural oxidation process without being removed independently. Further, the material of the sacrificial oxide layer 105 includes tetraethoxysilane. And the sacrificial oxide layer 105 covers the shallow trench isolation structure 102 to protect the morphology of the shallow trench isolation structure 102 and prevent the shallow trench isolation structure from being corroded in the subsequent cleaning and photoresist removing process, so that the reliability of the device is affected.
Step four S40: referring to fig. 8, a patterned photoresist layer 106 is formed, wherein the patterned photoresist layer 106 shields the gate 101 and a portion of the substrate 100, and exposes a portion of the sacrificial oxide layer 105 on the substrate 100 connected to the first sidewall 104.
Step five S50: referring to fig. 9, a first ion implantation process is performed on the substrate 100 with the patterned photoresist layer 106 and the first sidewall 104 as a barrier to form a lightly doped drain structure 107 in the substrate 100 on both sides of the gate 101.
The ions implanted in the first ion implantation process include, but are not limited to, N-type ions or P-type ions. Because the set thickness of the sacrificial oxide layer 105 is small, accurate implantation can be achieved by matching with an automatic ion implantation control system in the process of performing ion implantation, and the implantation effect is not affected. And in the ion implantation process, the sacrificial oxide layer 105 is naturally oxidized and gradually becomes thinner.
Step six S60: referring to fig. 10, the patterned photoresist layer 106 is removed and the sacrificial oxide layer 105 is also consumed.
In the process of cleaning the patterned photoresist layer 106, under the protection of the sacrificial oxide layer 105, erosion to the substrate 100, the gate 101, the first sidewall 104 and the shallow trench isolation structure 102 in the cleaning process is avoided, problems of topography depression, leakage current, channel shortening and the like are avoided, and the performance and reliability of the device are improved. In the cleaning and photoresist removing process, the sacrificial oxide layer 105 is gradually consumed and removed, so that when the patterned photoresist layer 106 is completely removed, the sacrificial oxide layer 105 is also completely removed. Therefore, the sacrificial oxide layer 105 can protect the substrate 100, the gate 101 and the first sidewall 104 when the patterned photoresist layer 106 is removed, and the sacrificial oxide layer 105 can be removed in the steps of natural oxidation and photoresist stripping cleaning, and a separate step for removing the sacrificial oxide layer 105 is not required, so that the operation is simple and the cost is low. Further, a wet cleaning process is used to remove the patterned photoresist layer 106 and simultaneously remove the sacrificial oxide layer 105.
Step seven S70: referring to fig. 11-12, a second sidewall 108 is formed, wherein the second sidewall 108 covers the first sidewall 104.
Further, referring to fig. 11, the second sidewall 108 includes an ethyl orthosilicate layer 108a and a second nitride layer 108b, and the ethyl orthosilicate layer 108a and the second nitride layer 108b sequentially cover the first sidewall 104. The material of the second nitride layer 108b includes silicon nitride.
After forming the second sidewall 108, referring to fig. 11, a second ion implantation process is performed on the substrate 100 with the first sidewall 104 and the second sidewall 108 as barriers, so as to form a source S and a drain D in the substrate 100 on both sides of the gate 101.
Based on the same inventive concept, the present embodiment further provides a semiconductor device, referring to fig. 7 to 12, the semiconductor device including:
a substrate 100, wherein a gate 101 is formed on the substrate 100;
a first sidewall 104, wherein the first sidewall 104 covers a sidewall of the gate 101;
a second side wall 108, the second side wall 108 covering the first side wall 104;
before forming the second side wall 108, the surfaces of the substrate 100, the gate 101, the first side wall 104, and the shallow trench isolation structure 102 are further covered with a sacrificial oxide layer 105 having a predetermined thickness. The thickness range of the sacrificial oxide layer 105 is as follows: 40 to 60 angstroms.
In summary, the present embodiment provides a semiconductor device and a method for manufacturing the same, the semiconductor device includes: a base 100, a first sidewall 104, and a second sidewall 108. Before forming the second sidewall 104, the surfaces of the substrate 100, the gate 101, and the first sidewall 108 are covered with a sacrificial oxide layer 105 having a predetermined thickness. The sacrificial oxide layer 105 is used to protect the substrate 100, the gate 101, the shallow trench isolation structure 102 and the first sidewall 104, and avoid the problems of topography recession, channel shortening, leakage current and the like caused by erosion in the photoresist stripping and cleaning process, thereby improving the performance and reliability of the device. In addition, the sacrificial oxide layer 105 is set to be thin, so that precise implantation can be realized by matching with an automatic ion implantation control system in the process of performing ion implantation, and the implantation effect is not influenced. In addition, the sacrificial oxide layer 105 is naturally oxidized and gradually thinned in the ion implantation process, and the sacrificial oxide layer 105 is removed in the cleaning and photoresist removing process. Therefore, a separate step for removing the sacrificial oxide layer 105 is not required, and the operation is simple and the cost is low.
It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a grid electrode is formed on the substrate;
forming a first side wall, wherein the first side wall covers the side wall of the grid;
forming a sacrificial oxide layer with a set thickness, wherein the sacrificial oxide layer covers the substrate, the grid and the first side wall;
forming a patterned photoresist layer, wherein the patterned photoresist layer shields the grid electrode and a part of the substrate and exposes a part of the sacrificial oxide layer on the substrate connected with the first side wall;
performing a first ion implantation process on the substrate by taking the patterned photoresist layer and the first side wall as barriers to form a lightly doped drain structure in the substrate on two sides of the grid;
removing the patterned photoresist layer and simultaneously removing the sacrificial oxide layer;
and forming a second side wall, wherein the second side wall covers the first side wall.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial oxide layer has a thickness in a range of: 40 to 60 angstroms.
3. The method of claim 1, wherein the sacrificial oxide layer comprises ethyl orthosilicate.
4. The method as claimed in claim 1, wherein a shallow trench isolation structure is further formed in the substrate, and the sacrificial oxide layer covers the shallow trench isolation structure.
5. The method according to claim 1, wherein the first sidewall comprises a first oxide layer and a first nitride layer, and the first oxide layer and the first nitride layer sequentially cover sidewalls of the gate.
6. The method according to claim 1, wherein the second sidewall comprises an ethyl orthosilicate layer and a second nitride layer, and the ethyl orthosilicate layer and the second nitride layer sequentially cover the first sidewall.
7. The method according to claim 1, wherein a second oxide layer is further formed between the substrate and the gate electrode.
8. The method for manufacturing a semiconductor device according to claim 1, wherein after the second sidewall is formed, the method for manufacturing a semiconductor device further comprises:
and performing a second ion implantation process on the substrate by taking the first side wall and the second side wall as barriers to form a source electrode and a drain electrode in the substrate at two sides of the grid electrode.
9. The method of claim 1, wherein the patterned photoresist layer is removed by wet cleaning while the sacrificial oxide layer is consumed.
10. A semiconductor device produced by the method for producing a semiconductor device according to any one of claims 1 to 9, comprising:
a substrate, wherein a grid electrode is formed on the substrate;
the first side wall covers the side wall of the grid;
a second side wall covering the first side wall;
before the second side wall is formed, sacrificial oxide layers with set thickness are covered on the surfaces of the substrate, the grid and the first side wall.
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| US20050277259A1 (en) * | 2004-06-09 | 2005-12-15 | Yamaha Corporation | Manufacturing method of gate oxidation films |
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