CN111710714B - Manufacturing method of field plate and semiconductor device - Google Patents
Manufacturing method of field plate and semiconductor device Download PDFInfo
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- CN111710714B CN111710714B CN202010581679.3A CN202010581679A CN111710714B CN 111710714 B CN111710714 B CN 111710714B CN 202010581679 A CN202010581679 A CN 202010581679A CN 111710714 B CN111710714 B CN 111710714B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 35
- 238000001312 dry etching Methods 0.000 claims abstract description 24
- 238000000137 annealing Methods 0.000 claims abstract description 16
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 14
- 210000000746 body region Anatomy 0.000 claims description 43
- 238000000151 deposition Methods 0.000 claims description 23
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 description 13
- 238000007254 oxidation reaction Methods 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The manufacturing method of the field plate comprises the steps of manufacturing field plate oxide layers with different thicknesses by adopting a TEOS deposition and high-temperature thermal annealing method, so that the thickness of the field plate oxide layer can be increased under the condition of not causing surface silicon damage, and the pressure resistance of the device can be improved; the field plate is prepared by two steps of etching: the method comprises the steps of firstly, obtaining a middle-stage field plate structure by dry etching and wet rinsing, and then, obtaining a final-stage field plate structure by dry etching the end part of the middle-stage field plate structure, removing the edge defect of the middle-stage field plate structure caused by wet rinsing, and improving the voltage-resistant reliability of the device. The manufacturing method of the semiconductor device and the semiconductor device comprise the manufacturing method of the field plate, the field plate oxide layer with large thickness is provided, and the voltage resistance is reliable.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a field plate, a manufacturing method of a semiconductor device and the semiconductor device.
Background
The field plate is a common terminal protection structure for improving the high-voltage breakdown resistance of the semiconductor device, and in the high-voltage device, a field plate oxidation layer with large thickness needs to be formed under a polycrystalline silicon or metal field plate so as to reduce the vertical electric field intensity of the field plate terminal, improve the breakdown voltage and improve the voltage withstanding reliability of the device.
In the traditional method, a thermal oxidation method is adopted to manufacture a field plate oxidation layer, and the thermal oxidation method only grows the oxidation layer in a field region, so that the loss of the field region oxidation layer can be caused in the subsequent etching process if the thickness of the field plate oxidation layer manufactured by the traditional thermal oxidation method is too thick, the thickness of the field plate oxidation layer manufactured by the traditional thermal oxidation method is generally less than 300 angstroms, and the pressure-resistant reliability is low; the High Temperature Oxide (HTO) deposition method can avoid the above problems, but requires special high temperature oxide deposition equipment, which results in high production cost.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a field plate, a method for manufacturing a semiconductor device, and a semiconductor device, which can obtain a field plate structure with good performance at a low cost and improve the withstand voltage reliability of the semiconductor device.
According to a first aspect of the present invention, there is provided a method for manufacturing a field plate, including:
a field plate oxide layer with the thickness of 300-2000 angstroms is manufactured on the upper surface of a body region of the semiconductor device by adopting a TEOS deposition method;
annealing the field plate oxide layer by adopting a high-temperature thermal annealing method;
etching the field plate oxide layer subjected to annealing treatment to obtain a field plate structure;
the body region comprises a drift region and a source region, the drift region further comprises a drain region injection region, and the field plate structure is located on the drift region and between the drain region injection region and the edge of the drift region close to the source region.
Optionally, before the step of obtaining the field plate structure, the method further includes:
and etching the field plate oxide layer subjected to annealing treatment by adopting a dry etching and wet rinsing method to obtain a middle-stage field plate structure, wherein the size of the middle-stage field plate structure is larger than that of the field plate structure on the upper surface of the body region of the semiconductor device.
Optionally, the method further comprises:
and etching the middle-stage field plate structure at one end of the middle-stage field plate structure close to the drain region injection region by adopting a dry etching method to obtain the field plate structure.
Optionally, the method further comprises:
growing thin gate oxide and depositing polysilicon on the semiconductor device with the middle-stage field plate structure, and manufacturing a gate,
and etching the middle-stage field plate structure by using the gate as a mask to obtain the self-aligned field plate structure.
Optionally, the body region further includes a well region, the well region is located on the upper surface of the body region and does not overlap with the drift region, the source region is located in the well region, and the source region is tangent to the gate.
According to a second aspect of the present invention, there is provided a method for manufacturing a field plate, including:
manufacturing a field plate oxide layer on the upper surface of a body region of the semiconductor device;
etching the field plate oxide layer by adopting a dry etching and wet rinsing method to obtain a middle-stage field plate structure;
etching the middle-stage field plate structure by adopting a dry etching method to obtain a final-stage field plate structure;
on the upper surface of the semiconductor device body region, the size of the middle-stage field plate structure is larger than that of the field plate structure, and the final-stage field plate structure is located between the source end and the drain end of the semiconductor device body region.
Optionally, the method further comprises:
growing thin gate oxide on the semiconductor device with the obtained middle-stage field plate structure, depositing polycrystalline silicon, and etching to manufacture a gate;
and etching the middle-stage field plate structure at one end of the middle-stage field plate structure close to the drain end of the semiconductor device body area by taking the gate as a mask so as to obtain the final-stage field plate structure.
According to a third aspect of the present invention, a method of manufacturing a semiconductor device, includes:
the field plate oxide layer is manufactured by adopting the manufacturing method of the field plate provided by the invention.
Optionally, the semiconductor device comprises an LDMOS device.
According to a fourth aspect of the present invention, a semiconductor device is provided, which is manufactured by the manufacturing method of the semiconductor device provided by the present invention.
According to the manufacturing method of the field plate oxide layer, TEOS deposition and high-temperature thermal annealing are adopted to manufacture the field plate oxide layer on the body area of the semiconductor device, the thickness of the field plate oxide layer is 300-2000 angstroms, the field plate oxide layer is etched to manufacture the field plate structure, and the field plate structure is positioned on the drift area so as to improve the surface breakdown voltage of the drift area. The manufacturing method of TEOS deposition and high-temperature thermal annealing is low in cost, no silicon is consumed in the process of manufacturing the field plate oxide layer, the obtained large-thickness field plate oxide layer is high in reliability, the surface breakdown voltage of the drift region is guaranteed to be improved, and the voltage resistance of the device is improved.
Before the drain terminal self-alignment field plate oxide layer is manufactured, a conventional dry etching and wet rinsing method is adopted to manufacture the middle-stage field plate structure, the size of the middle-stage field plate structure is larger than that of the final field plate structure on the upper surface of the body region of the semiconductor device, the middle-stage field plate structure is etched, residues on the upper surface of the body region of the semiconductor device are removed, and convenience is brought to the subsequent manufacturing of thin gate oxide.
The field plate structure is obtained by etching the middle-stage channel structure by adopting a dry etching method, so that the loss defect caused by wet rinsing on the middle-stage field plate structure can be removed, and the reliability of a final field plate oxidation layer of the semiconductor device is ensured.
The final field plate structure is obtained by adopting the stage field plate structure in the grid self-alignment etching, and the subsequent drain region injection region can adopt the grid self-alignment injection, so that the injection alignment precision of the drain region injection region is ensured, the drain end self-alignment semiconductor device structure is realized, the consistency of the device structure is improved, and the electrical characteristics of the device are improved.
The manufacturing method of the field plate comprises the steps of manufacturing the middle-stage field plate structure through dry etching and wet rinsing, and etching the middle-stage field plate structure through the dry etching to obtain the final-stage field plate structure, so that the problem that the wet rinsing affects the side undercut of the field plate structure can be solved, the performance of a side wall structure of the field plate structure connected with the injection region of the drain region is guaranteed, and the reliability of the final-stage field plate structure is guaranteed.
According to the manufacturing method of the semiconductor device, the field plate oxide layer is manufactured by the manufacturing method of the field plate oxide layer, so that the reliability of the field plate oxide layer can be improved, and the withstand voltage reliability of the semiconductor device is further improved. The LDMOS device structure with the self-aligned drain terminal is realized, the influence of process fluctuation on the device characteristics is reduced, and the consistency of the device performance is improved.
The semiconductor device provided by the invention is manufactured by adopting the manufacturing method of the semiconductor device provided by the invention, and the device has high voltage withstanding reliability and good performance consistency.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1, 2 and 3 show schematic cross-sectional views of stages of a method of fabricating a field plate oxide layer according to the prior art;
fig. 4, 5, 6 and 7 are schematic cross-sectional views illustrating stages in a method for fabricating a field plate oxide layer according to an embodiment of the present invention.
Fig. 8 shows a partial flow diagram of a method of fabricating a semiconductor device according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1, 2 and 3 show schematic cross-sectional views of stages of a method of fabricating a field plate oxide layer according to the prior art. As shown in the figure, in the cross section, the field plate oxide layer 130 is located on the upper surface of the body region of the semiconductor device 100, and the body region includes the first body region 110 and the second body region located on the upper surface of the first body region 110, if an LDMOS (laterally-diffused metal-oxide semiconductor) device is taken as an example, the first body region 110 may be a substrate, which may be a silicon substrate or a gallium nitride substrate, etc., and the second body region 120 may be an N-type drift region, and the LDMOS may be used as a high-voltage power device, and it is better to use a field plate oxide layer with a large thickness.
Wherein, a thermal oxidation method can be used to grow the field plate oxide layer 130 on the upper surface of the body region to form the structure shown in fig. 1, and the thickness of the field plate oxide layer 130 grown by the method is generally less than 300 angstroms. Alternatively, the field plate oxide layer 130 can be formed by a High Temperature Oxide (HTO) deposition process to obtain a field plate oxide layer with a thickness greater than 300 angstroms, but the process requires special high temperature oxide deposition equipment and is costly to produce.
After the field plate oxide layer 130 is manufactured, the field plate oxide layer 130 is etched by a dry etching method, so as to obtain the trench field plate oxide layer 131 located within the second body region 120, and meanwhile, the first end (left end in fig. 2) of the trench field plate oxide layer 131 is close to the first end (left end in fig. 2) of the second body region 120, so as to form the structure shown in fig. 2.
Then, a gate 140 is formed on the body region of the semiconductor device 100 and the trench gate oxide layer 131 to form a structure as shown in fig. 3, wherein the gate 140 is grown on the upper surface of the semiconductor device 100 by deposition or other methods, and has a shape conforming to the upper surface of the semiconductor device 100, and includes a first gate 141 and a second gate 142, the first gate 141 is located on the trench field plate oxide layer 131, the second gate 142 is located on the upper surface of the first body region 110 (a thin gate oxide structure, not shown, is further disposed between the second gate 142 and the first body region 110 to form a channel in this portion), and is connected to the first gate 141, and a channel region is formed at the overlapping portion of the lower surface of the second gate 142 and the P-type well region 150. Taking an LDMOS device as an example, the second body region 120 is an N-type drift region, the drain doped region 121 and the source doped region 151 are doped N-type, the source doped region 151 is further located in a P-type well region 150, and the P-type well region 150 is located on the upper surface of the first body region 110 and does not overlap with the second body region 120.
In the method for manufacturing a field plate oxide layer in the prior art, the step of manufacturing the field plate oxide layer 131 to form the structure shown in fig. 2 further includes: after the field plate oxide layer 131 is etched by a dry method, wet rinsing is also adopted for carrying out matched etching, the drain end of the etching step is not self-aligned with the first gate 141, only an LDMOS structure with the non-self-aligned drain end can be realized, the size of the device is larger, other mask plates are adopted in the step of manufacturing the drain end doping region 121, the alignment precision of the mask plates and the edge of the trench field plate oxide layer 131 is low, and the performance consistency of the device is poor.
Fig. 4, 5, 6 and 7 show schematic cross-sectional views of stages of a method of fabricating a field plate oxide layer according to an embodiment of the invention. Fig. 8 shows a partial flow diagram of a method of fabricating a semiconductor device according to an embodiment of the invention.
As shown in the figure, the method for manufacturing a field plate oxide layer according to the embodiment of the invention includes:
step S01: the field plate oxide layer is made by TEOS (Tetraethyl orthosilicate, a precursor of chemical vapor deposition) deposition and high-temperature annealing.
In the method for manufacturing a field plate oxide layer according to the embodiment of the present invention, a field plate oxide layer 230 with a thickness of 300 angstroms to 2000 angstroms is first manufactured on the upper surface of the body region of the semiconductor device 200 by using a TEOS deposition method, and the body region includes a first body region 210 and a second body region 220. for an LDMOS device, the first body region 210 may be a substrate, which may be a silicon substrate or a gallium nitride substrate, and the second body region 220 may be an N-type drift region located on the upper surface of the first body region 210. Then, the field plate oxide layer 230 is annealed at a high temperature to improve the quality of the field plate oxide layer 230, so as to obtain a field plate oxide layer with better performance than that of the prior art.
The TEOS deposition method is a standard method of a CMOS (Complementary Metal Oxide Semiconductor) process, no additional equipment is needed, the temperature of the TEOS deposition method is low, the quality of a manufactured field plate Oxide layer is not high, the quality of the field plate Oxide layer can be obviously improved by adopting high-temperature annealing, the high-quality field plate Oxide layer can be obtained by combining the TEOS deposition method and the high-temperature annealing, and the cost is low compared with an HTO deposition method which needs special high-temperature Oxide layer deposition equipment.
Step S02: and etching the field plate oxide layer by adopting a dry etching method and a wet rinsing method in sequence to manufacture the area field plate oxide layer after the channel end is etched.
The step of fabricating the middle-stage field plate structure 231 includes etching the field plate oxide layer 230 by dry etching, and then performing conventional processing on the middle-stage field plate structure 231 by wet rinsing to form the structure shown in fig. 5. Since the surface breakdown of the LDMOS device mainly occurs in the second body region 220, which is an N-type drift region, the mid-stage field plate structure 231 is located within the second body region 220.
Step S03: and preparing a gate, and etching the region field plate oxide layer etched at the channel end by using the gate as a mask by adopting a dry etching method to manufacture the final-stage field plate structure.
The step includes performing thermal oxidation to prepare a thin gate oxide layer on the semiconductor device 200 on which the middle-stage field plate structure 231 is formed, then fabricating a gate 240 on the thin gate oxide layer, wherein the gate 240 is conformally fabricated to include a first gate 241 and a second gate 242 (the thin gate oxide layer is located on the lower surface of the second gate 242 and on the upper surface of the well region 250, and is connected to the source region 251 to form a channel from the source region to the drift region), the first gate 241 is located on the middle-stage field plate structure 231, and the semiconductor device 200 is subjected to self-aligned etching by using the first gate 241 as a mask to obtain a final-stage field plate structure 232, so as to obtain the structure shown in fig. 6. The etching is performed only by a dry etching, and the size of the field plate structure 232 at the final stage is smaller than that of the field plate structure 231 at the intermediate stage, so that a defective portion (i.e., a portion where a undercut is formed, which is generally located at an edge portion) of the field plate oxide layer caused by wet rinsing is removed in the etching, thereby reducing adverse effects of the edge gate of the field plate oxide layer of the semiconductor device according to the embodiment of the present invention, and improving the voltage endurance reliability of the device. The gate is used as a mask to etch the field plate structure 232 in the final stage in a self-alignment manner, a complete channel region can be directly formed after etching, and the main manufacturing process of the device can be completed by subsequently manufacturing the well region and the source and drain regions, so that the process flow can be simplified, and the production efficiency can be improved.
Step S04: and manufacturing a well region and a source drain region. The structure shown in fig. 7 is formed, wherein the well region 250 is at least partially located within the second gate 242, and the portion of the well region 250 located outside the second gate 242 is self-aligned to perform the implantation of the source region 251 by using the second gate 242 as a mask, and the implantation of the drain region 221 is performed by using the first gate 241 as a mask in the second body region 220, so that the source region 251 and the drain region 221 are formed to be tangent to the second gate 242 and the second gate 241, respectively. The source and drain regions are manufactured by self-aligned injection, the alignment precision is high, the tangent connection between the edges of the source and drain regions and the edge of the gate 240 can be ensured, the channel region on the lower surface of the gate is ensured to be connected with the source region, the size of the drain end drift region is determined by the size of the gate 240, and the consistency of the device characteristics is ensured.
The method for manufacturing the field plate oxide layer adopts a TEOS deposition and high-temperature annealing method to manufacture the field plate oxide layer, the thickness of the field plate oxide layer can be thicker (300-2000 angstroms), the thicker field plate oxide layer can improve the surface breakdown voltage of the region of the gate corresponding to the field plate oxide layer and the pressure resistance of a semiconductor device, and the cost of the TEOS deposition and high-temperature annealing is low, namely the method for manufacturing the field plate oxide layer can obtain the field plate oxide layer with large thickness at low cost. And the process of manufacturing the field plate oxide layer by the TEOS deposition and high-temperature annealing method does not consume silicon, so that the material utilization rate can be improved, the cost is reduced, the loss defect of the field oxide layer in a large thickness field plate oxide layer is not easy to generate in the etching process, the performance of the device can be greatly reduced, and the voltage-resistant reliability of the device is ensured.
Further, a field plate oxide layer after the etching of the channel end is manufactured through etching by a dry etching and wet rinsing method, then a grid is manufactured, the field plate oxide layer after the etching of the channel end is subjected to self-alignment etching by taking the grid as a mask, and the etching only adopts dry etching, so that a final stage field plate structure is obtained, the part of the field plate oxide layer defect caused by dry etching and wet rinsing in the field plate oxide layer after the etching of the channel end is manufactured can be removed, the property of the field plate oxide layer is ensured, the final field plate oxide layer of the device is the final field plate oxide layer of the device, the drain region is connected, the connection of the grid and the drain is ensured, and the voltage withstanding reliability of the device and the consistency of the device property are ensured.
The semiconductor device manufactured by the manufacturing method of the field plate oxide layer has high voltage-resistant reliability and low production cost, does not need special deposition equipment, is easy to realize, and can be compatible with a CMOS (complementary metal oxide semiconductor) process.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A manufacturing method of a field plate comprises the following steps:
a field plate oxide layer with the thickness of 300-2000 angstroms is manufactured on the upper surface of a body region of the semiconductor device by adopting a TEOS deposition method;
annealing the field plate oxide layer by adopting a high-temperature thermal annealing method;
etching the field plate oxide layer subjected to annealing treatment by adopting a dry etching and wet rinsing method to obtain a middle-stage field plate structure;
preparing a gate, and dry-etching the middle-stage field plate structure by using the gate as a mask to obtain a self-aligned field plate structure,
the field plate structure is positioned on the drift region and between the drain region injection region and the edge of the drift region close to the source region, and the drain region injection region is self-aligned and injected by taking the grid as a mask.
2. The method of claim 1, wherein the dimensions of the mid-stage field plate structure are larger than the dimensions of the field plate structure on the semiconductor device body region upper surface.
3. The method of claim 2, wherein the step of dry etching the mid-stage field plate structure with the gate as a mask comprises:
and etching the middle-stage field plate structure at one end of the middle-stage field plate structure close to the drain region injection region by adopting a dry etching method so as to obtain the self-aligned field plate structure.
4. The method of fabricating a field plate of claim 3, wherein the step of fabricating a gate comprises:
and growing thin gate oxide on the semiconductor device with the middle-stage field plate structure, depositing polycrystalline silicon, and manufacturing the gate.
5. The method of claim 4, wherein,
the body region also comprises a well region, the well region is positioned on the upper surface of the body region and is not overlapped with the drift region, the source region is positioned in the well region, and the source region is tangent to the gate.
6. A manufacturing method of a field plate comprises the following steps:
manufacturing a field plate oxide layer on the upper surface of a body region of the semiconductor device;
etching the field plate oxide layer by adopting a dry etching and wet rinsing method to obtain a middle-stage field plate structure;
preparing a gate, and etching the middle-stage field plate structure by using the gate as a mask in a dry method to obtain a final-stage field plate structure;
on the upper surface of the semiconductor device body region, the size of the middle-stage field plate structure is larger than that of the field plate structure, and the final-stage field plate structure is located between the source end and the drain end of the semiconductor device body region.
7. The method of claim 6, wherein the step of preparing the gate and dry etching the middle-stage field plate structure by using the gate as a mask comprises:
growing thin gate oxide on the semiconductor device with the obtained middle-stage field plate structure, depositing polycrystalline silicon, and etching to manufacture the gate;
and etching the middle-stage field plate structure at one end of the middle-stage field plate structure close to the drain end of the semiconductor device body area by taking the gate as a mask so as to obtain the final-stage field plate structure.
8. A method for manufacturing a semiconductor device includes:
the field plate oxide layer is manufactured by the method for manufacturing the field plate according to any one of claims 1 to 7.
9. The method of manufacturing a semiconductor device according to claim 8,
the semiconductor device includes an LDMOS device.
10. A semiconductor device fabricated by the method for fabricating a semiconductor device according to claim 8 or 9.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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