CN110137260A - Field oxide isolation structure of ldmos transistor and preparation method thereof - Google Patents
Field oxide isolation structure of ldmos transistor and preparation method thereof Download PDFInfo
- Publication number
- CN110137260A CN110137260A CN201910435315.1A CN201910435315A CN110137260A CN 110137260 A CN110137260 A CN 110137260A CN 201910435315 A CN201910435315 A CN 201910435315A CN 110137260 A CN110137260 A CN 110137260A
- Authority
- CN
- China
- Prior art keywords
- layer
- isolation structure
- oxide layer
- oxide
- field oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 72
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 123
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000011241 protective layer Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 1
- 238000003475 lamination Methods 0.000 abstract description 11
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000004140 cleaning Methods 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract description 4
- 239000007924 injection Substances 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000006396 nitration reaction Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of field oxide isolation structure and preparation method thereof of ldmos transistor provided by the invention, the preparation method include: offer semi-conductive substrate；The first oxide layer and the second oxide layer are sequentially formed on the semiconductor substrate；Patterned photoresist layer is formed in second oxide layer；And using the patterned photoresist layer as mask, technique is performed etching to second oxide layer, and remove the patterned photoresist layer, to form the field oxide isolation structure of ldmos transistor.The field oxide isolation structure of existing ONO lamination is replaced with the field oxide isolation structure for the lamination being made of the first oxide layer and the second oxide layer by the present invention, to lower influence of the field oxide isolation structure to the electrical characteristic of ldmos transistor.Further, protective layer is formed in second oxide layer, to lower the damage to field oxide isolation structure such as subsequent ion injection technology, cleaning process.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of field oxide of ldmos transistor
Isolation structure and preparation method thereof.
Background technique
BCD technique be on the same chip make bipolar transistor (Bipolar Junction Transistor, BJT),
The technique of CMOS complementary metal-oxide-semiconductor (CMOS), diffused metal oxide emiconductor (DMOS).Using BCD technique into
Row preparation LDMOS (Laterally Diffused Metal Oxide Semiconductor, lateral diffused metal oxide half
Conductor) during transistor, field plate is generallyd use to reduce electric field, improve voltage, as shown in Figure 1, field plate is by polysilicon gate
Field oxide (Field Oxide, FOX, abbreviation field oxygen) is stepped up in extension.And it is frequently necessary to using ONO (Oxide-Nitride-
Oxide, oxide/nitride/oxide) field oxide isolation structure of the laminated construction as ldmos transistor, to solve field
Oxide layer isolation structure causes semiconductor to serve as a contrast in etching since the oxide layer between semiconductor substrate and nitride is too thin
The damage of bottom surface.
However, the structure causes the electrical characteristics such as the drain current detected, drain voltage that adaptability transfer occurs, influence
The electrical characteristic of ldmos transistor.
Summary of the invention
Technical problem to be solved by the invention is to provide the field oxide isolation structures and its system of a kind of ldmos transistor
Preparation Method can lower influence of the field oxide isolation structure to the electrical characteristic of ldmos transistor.
In order to solve the above-mentioned technical problems, the present invention provides a kind of field oxide isolation structures of ldmos transistor
Preparation method, the preparation method comprises the following steps:
Semi-conductive substrate is provided；
The first oxide layer and the second oxide layer are sequentially formed on the semiconductor substrate；
Patterned photoresist layer is formed in second oxide layer；And
Using the patterned photoresist layer as mask, technique, and etching stopping are performed etching to second oxide layer
In first oxide layer of partial depth, the patterned photoresist layer is removed, to form the field oxygen of ldmos transistor
Change layer isolation structure.
Optionally, the material of first oxide layer includes silica, with a thickness of
Optionally, the material of second oxide layer includes teos layer, with a thickness of
Optionally, after the removing patterned photoresist layer, further includes:
A protective layer is formed in second oxide layer, the protective layer covers at least the upper of second oxide layer
Surface and side wall.
Further, the protective layer includes high temperature oxide layer, be used to preventing subsequent technique to the field oxide every
Physical damnification or chemical damage from structure.
Further, the protective layer with a thickness of
The present invention also provides a kind of field oxide isolation structures of ldmos transistor, including the first oxide layer and second
Oxide layer, first oxide layer and the second oxide layer are sequentially formed in semiconductor substrate.
It optionally, further include protective layer, the protective layer covers upper surface and the side wall of second oxide layer, the guarantor
Sheath is for preventing subsequent technique to the physical damnification or chemical damage of the field oxide isolation structure.
Optionally, the material of first oxide layer includes silica, with a thickness of
Optionally, the material of second oxide layer includes teos layer, with a thickness of
Exist compared with prior art it is following the utility model has the advantages that
A kind of field oxide isolation structure and preparation method thereof of ldmos transistor provided by the invention, the LDMOS are brilliant
In the preparation method of the field oxide isolation structure of body pipe, by the field oxide isolation structure of existing ONO lamination replace with by
The field oxide isolation structure of the lamination of first oxide layer and the second oxide layer composition, to lower field oxide isolation structure pair
The influence of the electrical characteristic of ldmos transistor.Further, protective layer is formed in second oxide layer, it is subsequent to lower
The damage to field oxide isolation structure such as ion implantation technology, cleaning process.
Detailed description of the invention
Fig. 1 is a kind of the schematic diagram of the section structure of ldmos transistor；
Fig. 2 is that the process of the preparation method of the field oxide isolation structure of the ldmos transistor of one embodiment of the invention is shown
It is intended to；
Fig. 3 is the schematic diagram of the section structure of the ldmos transistor of one embodiment of the invention.
Description of symbols:
In Fig. 1:
10- semiconductor substrate；20- field oxide isolation structure；The first oxide layer of 21-；22- nitration case；23- second is aoxidized
Layer；
In Fig. 3:
100- semiconductor substrate；
200- field oxide isolation structure；The first oxide layer of 210-；The second oxide layer of 220-；230- protective layer；
300- field plate；
410- source electrode；420- drain electrode.
Specific embodiment
As shown in Figure 1, a kind of preparation method of the field oxide isolation structure of existing ldmos transistor includes following step
It is rapid:
Step S11: semi-conductive substrate is provided；
Step S12: the first oxide layer, nitration case and the second oxide layer are sequentially formed on the semiconductor substrate；
Step S13: patterned photoresist is formed in second oxide layer；
Step S14: using the patterned photoresist as mask, successively to second oxide layer, nitration case and first
Oxide layer performs etching technique, to form the field oxide isolation structure of ldmos transistor.
There is drain current, drain electrode in test in the field oxide isolation structure for the ONO lamination that existing technique is formed
The problem of adaptability transfer, occurs for the electrical characteristics such as voltage, and inventor is the study found that cause the possible cause of the problem folded for ONO
The field oxide isolation structure of layer has captured some charges in test, so that drain current, drain voltage become smaller, it has impact on
The electrical characteristic of ldmos transistor.
Based on the studies above, a kind of field oxide isolation structure of ldmos transistor provided by the invention and its preparation side
Method, in the preparation method of the field oxide isolation structure of the ldmos transistor, by the field oxide of existing ONO lamination every
From the field oxide isolation structure that structure replaces with the lamination being made of the first oxide layer and the second oxide layer, to lower field oxidation
Influence of the layer isolation structure to the electrical characteristic of ldmos transistor.Further, protection is formed in second oxide layer
Layer, to lower the damage to field oxide isolation structure such as subsequent ion injection technology, cleaning process.
Field oxide isolation structure of a kind of ldmos transistor of the invention and preparation method thereof will be made below further
Detailed description.The present invention is described in more detail below with reference to accompanying drawings, which show preferred implementations of the invention
Example, it should be appreciated that those skilled in the art can modify invention described herein and still realize advantageous effects of the invention.
Therefore, following description should be understood as the widely known of those skilled in the art, and be not intended as to limit of the invention
System.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to side
Just, the purpose of the embodiment of the present invention is lucidly aided in illustrating.
A kind of preparation method of the field oxide isolation structure of ldmos transistor provided by the present embodiment.Fig. 2 is this reality
Apply the flow diagram of the preparation method of the field oxide isolation structure of the ldmos transistor of example.As shown in Fig. 2, the preparation side
Method the following steps are included:
Step S21: semi-conductive substrate is provided；
Step S22: the first oxide layer and the second oxide layer are sequentially formed on the semiconductor substrate；
Step S23: patterned photoresist layer is formed in second oxide layer；And
Step S24: using the patterned photoresist layer as mask, performing etching technique to second oxide layer, and
Etching stopping removes the patterned photoresist layer, in first oxide layer of partial depth to form LDMOS crystal
The field oxide isolation structure of pipe.
Below with reference to Fig. 2 and Fig. 3 to a kind of field oxide isolation structure of ldmos transistor disclosed in the present embodiment
Preparation method introduced in more detail.
As shown in figure 3, step S21 is first carried out, semi-conductive substrate 100 is provided.After the semiconductor substrate 100 can be
Continuous technique provides operating platform, can be well known to those skilled in the art any to bearing semiconductor integrated circuit composition
The ground of element, can be bare die, be also possible to by epitaxial growth technology treated wafer, detailed, the semiconductor
Substrate 100 be, for example, silicon-on-insulator (silicon-on-insulator, SOI) substrate, body silicon (bulk silicon) substrate,
Germanium substrate, germanium silicon base, indium phosphide (InP) substrate, GaAs (GaAs) substrate or germanium on insulator substrate etc..In addition, institute
Active area can be defined by stating in semiconductor substrate 100.To put it more simply, only indicating the semiconductor substrate herein with a blank
100.The first well region (not shown) and the second well region (not shown), institute are formed in the semiconductor substrate 100
State the first well region and the second well region it is horizontal be formed in the surface of the semiconductor substrate 100 or less.Wherein the first well region has
First doping type (N-type or p-type), the second well region have the second doping type (p-type or N-type).As an example, when the first doping
When type is N-type, the second doping type is p-type；Conversely, the second doping type is N-type when the first doping type is p-type.The
One well region and the second well region are disposed adjacent.
Then step S22 is executed, the first oxide layer 210 and the second oxidation are sequentially formed in the semiconductor substrate 100
Layer 220.
Specifically, being sequentially depositing the first oxide layer 210 and the second oxide layer 220 in the semiconductor substrate 100.It is described
The material of first oxide layer 210 is, for example, silica, and thickness is, for example, Second oxide layer 220
Material be, for example, teos layer (TEOS), thickness is, for example,
Then step S23 is executed, patterned photoresist layer is formed in second oxide layer 220 and (does not show in figure
Out).The patterned photoresist is as the mask for forming subsequent field oxide isolation structure.
It is specific: firstly, coating a photoresist layer in second oxide layer 220；Then, by exposing, development figure
Photoresist layer described in shape to cover photoresist at the second oxide layer 220 for forming field oxide isolation structure, and is formed
Opening is formed other than second oxide layer 220 of field oxide isolation structure.Then step S24 is executed, with the patterned light
Photoresist layer is mask, performs etching technique to second oxide layer 220, and etching stopping is in first oxygen of partial depth
Change on layer 210, the patterned photoresist layer is removed, to form the field oxide isolation structure of ldmos transistor.
It is specific: for the first time, field oxide isolation structure position to be removed by dry etch process and/or wet-etching technology
Second oxide layer 220 in addition, and etching stopping is in first oxide layer 210 of partial depth.Then, institute is removed
State patterned photoresist layer.Then, a protective layer 230, the protective layer 230 are formed in second oxide layer 220
High temperature oxide layer (HTO) in this way, the protective layer cover at least the upper surface of second oxide layer 220 (that is, described second
Oxide layer 220 is backwards to the surface of the semiconductor substrate) and side wall.The thickness of the protective layer 230 is, for example,
The protective layer 230 for preventing subsequent technique to the physical damnification of the field oxide isolation structure 200 or
Chemical damage.E.g. prevent subsequent ion injection technology to the physical damnification of field oxide isolation structure 200, cleaning process pair
The chemical damage etc. of field oxide isolation structure 200.The present embodiment replaces the field oxide isolation structure of existing ONO lamination
Field oxide isolation structure for the lamination being made of the first oxide layer and the second oxide layer, avoids field oxide isolation structure
Some charges are captured when detecting, to lower influence of the field oxide isolation structure to the electrical characteristic of ldmos transistor.
After the field oxide isolation structure for forming ldmos transistor, further includes: in the field oxide isolation structure
Field plate 300 is formed in the semiconductor substrate 100 of side, and 300 part of the field plate covers the oxidation isolation structure 200,
In, the field plate 300 is, for example, polysilicon gate.；
Source/drain 410,420 is formed in the field oxide isolation structure 200 and 300 two sides of field plate；
It etches first oxide layer 210 and exposes the source/drain 410,420, to form ldmos transistor.
Please continue to refer to Fig. 3, the present embodiment additionally provides a kind of field oxide isolation structure of ldmos transistor, including
The first oxide layer 210, the second oxide layer 220 and the protective layer 230 being sequentially formed in semiconductor substrate 100, first oxygen
The material for changing layer 210 is, for example, silica, and thickness is, for example,The material of second oxide layer 220 is for example
It is teos layer, thickness is, for example,The thickness of the protective layer 230 is, for example,The protective layer 230 covers upper surface and the side wall of second oxide layer 220, and the protective layer 230 is used
In prevent subsequent technique to the physical damnification or chemical damage of the field oxide isolation structure 200.
In summary, the field oxide isolation structure and preparation method thereof of a kind of ldmos transistor provided by the invention, institute
It states in the preparation method of field oxide isolation structure of ldmos transistor, by the field oxide isolation structure of existing ONO lamination
The field oxide isolation structure for the lamination being made of the first oxide layer and the second oxide layer is replaced with, to lower field oxide isolation
Influence of the structure to the electrical characteristic of ldmos transistor.Further, protective layer is formed in second oxide layer, to subtract
The damage to field oxide isolation structure such as low subsequent ion injection technology, cleaning process.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two " description is used only for distinguishing various components, element, step etc. in specification, without being intended to indicate that various components, member
Logical relation or ordinal relation between element, step etc..It is understood that although the present invention is disclosed with preferred embodiment
As above, however above-described embodiment is not intended to limit the invention.For any person skilled in the art, it is not taking off
From under technical solution of the present invention ambit, many all is made to technical solution of the present invention using the technology contents of the disclosure above
Possible changes and modifications or equivalent example modified to equivalent change.Therefore, all without departing from technical solution of the present invention
Content, any simple modifications, equivalents, and modifications made to the above embodiment, still belong to according to the technical essence of the invention
In the range of technical solution of the present invention protection.
Claims (10)
1. a kind of preparation method of the field oxide isolation structure of ldmos transistor, which is characterized in that the preparation method includes
Following steps:
Semi-conductive substrate is provided；
The first oxide layer and the second oxide layer are sequentially formed on the semiconductor substrate；
Patterned photoresist layer is formed in second oxide layer；And
Using the patterned photoresist layer as mask, technique is performed etching to second oxide layer, and etching stopping is in portion
Divide in first oxide layer of depth, the patterned photoresist layer is removed, to form the field oxide of ldmos transistor
Isolation structure.
2. preparation method as described in claim 1, which is characterized in that the material of first oxide layer includes silica,
Its with a thickness of
3. preparation method as described in claim 1, which is characterized in that the material of second oxide layer includes ethyl orthosilicate
Layer, with a thickness of
4. preparation method as described in claim 1, which is characterized in that after removing the patterned photoresist layer, also wrap
It includes:
A protective layer is formed in second oxide layer, the protective layer covers at least the upper surface of second oxide layer
And side wall.
5. preparation method as claimed in claim 4, which is characterized in that the protective layer includes high temperature oxide layer, is used to prevent
Only physical damnification or chemical damage of the subsequent technique to the field oxide isolation structure.
6. preparation method as claimed in claim 5, which is characterized in that the protective layer with a thickness of
7. a kind of field oxide isolation structure of ldmos transistor, which is characterized in that aoxidized including the first oxide layer and second
Layer, first oxide layer and the second oxide layer are sequentially formed in semiconductor substrate.
8. the field oxide isolation structure of ldmos transistor as claimed in claim 7, which is characterized in that it further include protective layer,
The protective layer covers upper surface and the side wall of second oxide layer, it is described it is protective layer used in prevent subsequent technique to the field
The physical damnification or chemical damage of oxide layer isolation structure.
9. the field oxide isolation structure of ldmos transistor as claimed in claim 8, which is characterized in that first oxidation
The material of layer includes silica, with a thickness of
10. the field oxide isolation structure of ldmos transistor as claimed in claim 8, which is characterized in that second oxidation
The material of layer includes teos layer, with a thickness of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910435315.1A CN110137260B (en) | 2019-05-23 | 2019-05-23 | Field oxide layer isolation structure of LDMOS transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910435315.1A CN110137260B (en) | 2019-05-23 | 2019-05-23 | Field oxide layer isolation structure of LDMOS transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110137260A true CN110137260A (en) | 2019-08-16 |
| CN110137260B CN110137260B (en) | 2022-05-10 |
Family
ID=67572759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910435315.1A Active CN110137260B (en) | 2019-05-23 | 2019-05-23 | Field oxide layer isolation structure of LDMOS transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110137260B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111403279A (en) * | 2020-04-29 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
| CN111584361A (en) * | 2020-05-26 | 2020-08-25 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
| CN111710714A (en) * | 2020-06-23 | 2020-09-25 | 杰华特微电子（杭州）有限公司 | Manufacturing method of field plate and semiconductor device |
| CN111785640A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Method for adjusting angle of oxide field plate in LDMOS transistor |
| CN111785639A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS transistor and preparation method thereof |
| EP3916802A1 (en) * | 2020-05-29 | 2021-12-01 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070057293A1 (en) * | 2005-09-13 | 2007-03-15 | Ching-Hung Kao | Ultra high voltage mos transistor device |
| CN101022109A (en) * | 2006-02-15 | 2007-08-22 | 三菱电机株式会社 | Semiconductor device and method of manufacturing the same |
| US20140070315A1 (en) * | 2008-10-29 | 2014-03-13 | Tower Semiconductor Ltd. | Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure |
| US10283622B1 (en) * | 2018-01-16 | 2019-05-07 | Globalfoundries Singapore Pte. Ltd. | Extended drain transistor on a crystalline-on-insulator substrate |
-
2019
- 2019-05-23 CN CN201910435315.1A patent/CN110137260B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070057293A1 (en) * | 2005-09-13 | 2007-03-15 | Ching-Hung Kao | Ultra high voltage mos transistor device |
| CN101022109A (en) * | 2006-02-15 | 2007-08-22 | 三菱电机株式会社 | Semiconductor device and method of manufacturing the same |
| US20140070315A1 (en) * | 2008-10-29 | 2014-03-13 | Tower Semiconductor Ltd. | Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure |
| US10283622B1 (en) * | 2018-01-16 | 2019-05-07 | Globalfoundries Singapore Pte. Ltd. | Extended drain transistor on a crystalline-on-insulator substrate |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111403279A (en) * | 2020-04-29 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
| CN111403279B (en) * | 2020-04-29 | 2023-03-28 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
| CN111584361A (en) * | 2020-05-26 | 2020-08-25 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
| EP3916802A1 (en) * | 2020-05-29 | 2021-12-01 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US11527632B2 (en) * | 2020-05-29 | 2022-12-13 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN111710714A (en) * | 2020-06-23 | 2020-09-25 | 杰华特微电子（杭州）有限公司 | Manufacturing method of field plate and semiconductor device |
| CN111710714B (en) * | 2020-06-23 | 2022-08-23 | 杰华特微电子股份有限公司 | Manufacturing method of field plate and semiconductor device |
| CN111785640A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Method for adjusting angle of oxide field plate in LDMOS transistor |
| CN111785639A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS transistor and preparation method thereof |
| CN111785639B (en) * | 2020-08-26 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | LDMOS transistor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110137260B (en) | 2022-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110137260A (en) | Field oxide isolation structure of ldmos transistor and preparation method thereof | |
| US9478549B2 (en) | FinFET with dielectric isolation by silicon-on-nothing and method of fabrication | |
| US20090108348A1 (en) | Semiconductor device | |
| CN107180869B (en) | Semiconductor device and method of forming the same | |
| CN110517957B (en) | Field oxide layer and forming method thereof | |
| JPH0714800A (en) | Forming contact on front side surface of silicon substrate of silicon-on-insulator (soi) wafer | |
| KR102648999B1 (en) | Lateral double diffused metal oxide semiconductor and method for fabricating the same | |
| US20160380095A1 (en) | High voltage finfet structure with shaped drift region | |
| CN102299177B (en) | Method for manufacturing contact and semiconductor device with contact | |
| CN107731808B (en) | Electrostatic discharge protection structure and forming method thereof | |
| US10692992B2 (en) | Semiconductor device and fabrication method thereof | |
| CN109585558B (en) | LDMOS FINFET structure with multiple gate structures | |
| CN111211171A (en) | Lateral diffusion metal oxide semiconductor device | |
| CN107492495A (en) | Semiconductor structure and forming method thereof | |
| US20110081760A1 (en) | Method of manufacturing lateral diffusion metal oxide semiconductor device | |
| US9905480B1 (en) | Semiconductor devices and methods for forming the same | |
| JP2005039057A (en) | Semiconductor device and its manufacturing method | |
| US20050009277A1 (en) | Termination structure of DMOS device and method of forming the same | |
| CN111785639A (en) | LDMOS transistor and preparation method thereof | |
| US8552478B2 (en) | Corner transistor and method of fabricating the same | |
| CN110021561A (en) | Semiconductor device and forming method thereof | |
| CN110098150A (en) | Semiconductor structure and forming method thereof | |
| CN106992123B (en) | Lateral diffusion metal oxide semiconductor element and manufacturing method thereof | |
| US9059202B2 (en) | Metal-oxide-semiconductor (MOS) device and method for fabricating the same | |
| US20090020837A1 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |