CN113889433A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113889433A CN113889433A CN202111121722.9A CN202111121722A CN113889433A CN 113889433 A CN113889433 A CN 113889433A CN 202111121722 A CN202111121722 A CN 202111121722A CN 113889433 A CN113889433 A CN 113889433A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
The application provides a semiconductor device and a preparation method thereof, wherein the method comprises the following steps: sequentially depositing an insulating layer and a stop layer on a substrate, wherein the substrate comprises a high-voltage device area and a non-high-voltage device area, and the thickness of the insulating layer above the high-voltage device area is greater than that of the non-high-voltage device area; forming a plurality of first grooves and a plurality of second grooves which penetrate through the stop layer and the insulating layer respectively above a high-voltage device area and a non-high-voltage device area of the substrate; etching part of the stop layer above the first groove to enable the opening width of the first groove at the side far away from the substrate to be larger than the opening width at the side close to the substrate; and further etching the bottoms of the first and second plurality of grooves such that the depths of the first and second grooves extend into at least a portion of the substrate.
Description
Technical Field
The present disclosure relates to the field of semiconductor design and manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
At present, with the development of semiconductor technology, the feature size of an integrated circuit is smaller and smaller, the number of transistors on a chip is gradually increased, and in order to further improve the memory performance of a memory, the number of chips (chips) included on each wafer is also larger and larger, wherein each chip includes millions of semiconductor devices in an Active Area (AA), and the semiconductor devices in the active area of the chip generally adopt Shallow Trench Isolation (STI) to avoid mutual interference between the independent semiconductor devices.
Each wafer generally includes a plurality of types of transistors, such as a high voltage transistor (HV MOS), a low voltage transistor (LV MOS), and a low voltage transistor (LLV MOS), and the operation voltages of the different types of transistors are generally different, and the size or shape of the required shallow trench isolation is also generally different. Therefore, it becomes important to satisfy effective isolation between different transistors on the same die.
Disclosure of Invention
The present application provides a semiconductor device and a method of manufacturing the same that can at least partially solve the above-mentioned problems in the prior art.
According to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, which may include: sequentially depositing an insulating layer and a stop layer on a substrate, wherein the substrate comprises a high-voltage device area and a non-high-voltage device area, and the thickness of the insulating layer above the high-voltage device area is greater than that of the non-high-voltage device area; forming a plurality of first grooves and a plurality of second grooves penetrating through the stop layer and the insulating layer respectively above a high-voltage device region and a non-high-voltage device region of the substrate; etching a part of the stop layer above the first groove to enable the opening width of the first groove at the side far away from the substrate to be larger than the opening width at the side close to the substrate; and further etching the bottoms of the first and second plurality of grooves such that the depths of the first and second grooves extend into at least a portion of the substrate.
In an embodiment of the application, after the further etching treatment, an opening width of the second groove on a side away from the substrate may be equal to an opening width of a side close to the substrate.
In an embodiment of the present application, the step of etching the portion of the stop layer above the first groove may include: filling and covering the second grooves by a patterned photoresist layer so that only the stop layer in the plurality of first grooves is etched during an etching process.
In an embodiment of the application, after the further etching process, projection profiles of the plurality of first grooves along the extending direction of the respective grooves may be the same.
In an embodiment of the application, after the further etching process, the plurality of first grooves include at least two grooves whose projection profiles along the groove extending direction may be different.
In an embodiment of the application, after the further etching process, the plurality of second grooves may include at least two grooves having different widths from each other.
In an embodiment of the application, after the further etching process, the width of each second groove may be the same.
In one embodiment of the present application, the step of sequentially depositing an insulating layer and a stop layer on the substrate may include: depositing a first insulating layer on the substrate; removing at least one part of the first insulating layer above a non-high-voltage device area of the substrate through etching treatment; and depositing the stop layer on the insulating layer after the etching treatment.
In one embodiment of the present application, after etching the bottoms of the plurality of first grooves and the plurality of second grooves such that the depths of the first grooves and the second grooves extend to at least a portion of the substrate, the method may further include: and filling the first groove and the second groove to form a filling layer.
In one embodiment of the present application, the material of the filling layer may include an insulating material.
In one embodiment of the present application, the high voltage device region of the substrate may be used to form a high voltage transistor device, and the non-high voltage device region of the substrate may be used to form a low voltage transistor device and a low voltage transistor device.
Another aspect of the present application provides a semiconductor device, which may include: a substrate divided into a plurality of high voltage device regions and non-high voltage regions; a stacked structure formed over the substrate; and a plurality of first groove structures formed by filling an insulating material in first grooves, the first grooves penetrating the laminated structure and extending to at least a part of the substrate corresponding to the high-voltage device region, and having an opening width on a side away from the substrate larger than an opening width on a side close to the substrate; and a plurality of second groove structures formed by filling an insulating material in second grooves corresponding to at least a portion of the high-voltage device region, which penetrate the stacked structure and extend to the substrate.
In one embodiment of the present application, the stacked structure may include an insulating layer and a stop layer, wherein a thickness of the insulating layer over the high voltage device region may be greater than a thickness over the non-high voltage device region.
In one embodiment of the present application, the projection profiles of the plurality of first grooves along the extending direction of their respective grooves may be the same.
In one embodiment of the present application, the plurality of first grooves may include at least two grooves having different projection profiles along a groove extending direction thereof.
In one embodiment of the present application, the plurality of second grooves may include at least two grooves having different widths from each other.
In one embodiment of the present application, each of the second grooves may have the same width.
In one embodiment of the present application, the high voltage device region of the substrate may be used to form a high voltage transistor device, and the non-high voltage device region of the substrate may be used to form a low voltage transistor device and a low voltage transistor device.
According to the semiconductor device and the preparation method thereof, the groove structures in different shapes are formed in the high-voltage device area and the non-high-voltage device area through etching, the isolation requirements of transistors with different working voltages on the same substrate can be met, such as a high-voltage transistor (HV MOS), a low-voltage transistor (LV MOS) and a low-voltage transistor (LLV MOS), the isolation effect between the devices is improved to a certain extent, and the improvement of the performance of the semiconductor device is facilitated.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:
fig. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure; and
fig. 2A to 2F are process diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
In the drawings, the size, dimension, and shape of elements have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. In addition, in the present application, the order in which the processes of the respective steps are described does not necessarily indicate an order in which the processes occur in actual operation, unless explicitly defined otherwise or can be inferred from the context.
It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor device 1000 according to an embodiment of the present disclosure. As shown in fig. 1, the present application provides a method 1000 of fabricating a semiconductor device, comprising:
step S110: sequentially depositing an insulating layer and a stop layer on a substrate, wherein the substrate comprises a high-voltage device area and a non-high-voltage device area, and the thickness of the insulating layer above the high-voltage device area is greater than that of the non-high-voltage device area;
step S120: forming a plurality of first grooves and a plurality of second grooves which penetrate through the stop layer and the insulating layer respectively above a high-voltage device area and a non-high-voltage device area of the substrate;
step S130: etching part of the stop layer above the first groove to enable the opening width of the first groove at the side far away from the substrate to be larger than the opening width at the side close to the substrate;
step S140: the bottoms of the first and second plurality of recesses are further etched such that the depths of the first and second recesses extend into at least a portion of the substrate.
The specific processes of the steps of the above-described manufacturing method 1000 will be described in detail with reference to fig. 2A to 2F.
Step S110
As shown in fig. 2A, a first insulating layer (not shown in the figure) is deposited on the semiconductor substrate 10, wherein the substrate 10 includes a high-voltage device region (substrate within the dashed box) and a non-high-voltage device region (substrate outside the dashed box), and the non-high-voltage device region may include a low-voltage device region and a low-voltage device region. Wherein the high voltage device region may be used for a high voltage transistor (HV MOS), the low voltage device region may be used for a low voltage transistor (LV MOS), and the low voltage device region may be used for a low voltage transistor (LLV MOS), for example. The semiconductor substrate 10 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The material of the substrate 110 may also be a compound semiconductor. For example, the substrate 110 may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like. It is noted that the substrate 10 of the present application may also be fabricated using at least one of the other semiconductor materials known in the art.
Etching the first insulating layer above the low-voltage device region and the low-voltage device region to form an insulating layer 20, wherein the thickness of the insulating layer 20 above the high-voltage device region in the substrate 10 is greater than that of the non-high-voltage device region, and then depositing a stop layer 30 on the insulating layer 20. The material of the insulating layer 20 may be an insulating material including silicon oxide, the material of the stop layer 30 may be an insulating material including silicon nitride, and the stop layer 30 is mainly used for a subsequent stop layer for chemical mechanical planarization. The stop layer 30 may then be planarized, typically also by Chemical Mechanical Polishing (CMP). The method of depositing the first insulating layer and the stop layer 30 may include a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this application.
Step S120
As shown in fig. 2B, the insulating layer 20 and the stop layer 30 may be etched using, for example, a dry or wet etching process to form a plurality of first grooves 21 and a plurality of second grooves 22 and 23 penetrating the stop layer 30 and the insulating layer 20, the plurality of first grooves 21 being located above the high voltage device region of the substrate 10, and the plurality of second grooves 22 and 23 being located above the non-high voltage device region of the substrate 10. For example, second recess 22 is located over a low voltage device region of substrate 10 and second recess 23 is located over a low voltage device region of substrate 10. The plurality of first grooves 21 may include grooves with at least two widths, and alternatively, the widths of the plurality of first grooves 21 may be the same. The plurality of second grooves 22 and 23 may include grooves of at least two widths, and alternatively, the widths of the plurality of second grooves 22 and 23 may be the same. The widths of the plurality of first grooves 21 and the plurality of second grooves 22 and 23 are not particularly limited, and may be specifically set according to isolation conditions required for subsequent formation of a semiconductor device.
Step S130
As shown in fig. 2C, a patterned photoresist layer 40 may be deposited over the stop layer 30, and a portion of the stop layer 30 over the first groove 21 is etched through the patterned photoresist layer 40, and the photoresist layer 40 is removed after the etching is completed. After the photoresist layer 40 is removed, as shown in fig. 2D, after etching the portion of the stop layer 30 above the first groove 21, the opening width of the first groove 21 on the side away from the substrate is greater than the opening width on the side close to the substrate.
Step S140
As shown in fig. 2E, the bottoms of the plurality of first recesses 21 and the plurality of second recesses 22 and 23 are further etched such that the depths of the first recesses 21 and the second recesses 22 and 23 extend into at least a portion of the substrate 10. Wherein the projection profiles of the plurality of first grooves 21 in the extending direction of their respective grooves are the same. Alternatively, the plurality of first grooves 21 includes at least two kinds of grooves having different projection profiles along the groove extending direction thereof. The plurality of second grooves 22 and 23 includes at least two kinds of grooves having different widths from each other. Alternatively, the widths of the second grooves 22 and 23 are the same. The part of the first groove 21 in the substrate 10 is in the shape of an inverted trapezoid with a large upper opening and a small lower opening, and the side surface of the first groove 21 forms a certain angle with the plane of the substrate 10, which is more beneficial to the isolation of high-voltage transistor devices. The plurality of second grooves 22 and 23 may be grooves with the same width of the upper and lower openings, which not only optimizes the process, but also facilitates the effective isolation between the low voltage transistor device and the low voltage transistor device due to the shape of the groove with the profile. However, those skilled in the art will appreciate that the depths of the first recess 21 and the second recesses 22 and 23 may be different, and the depths may be defined according to the actual required isolation requirements, which is not limited in the present application.
After the first and second grooves 21, 22, and 23 having the shapes shown in fig. 2E are formed, the first and second grooves 21, 22, and 23 may be filled to form the filling layer 50, and the filling layer 50 may be planarized by Chemical Mechanical Polishing (CMP). When the filling layer 50 is planarized, the stop layer 30 can be used as a reference for chemical mechanical polishing, i.e., the polishing can be stopped until the stop layer 30 is exposed by chemical mechanical polishing. The semiconductor device after the planarization process is shown in fig. 2F. The material of the filling layer 50 may be an insulating material, such as silicon oxide, and the dielectric constants of different materials may have a certain difference, and in an actual production process, the material with a suitable dielectric constant may be selected according to the isolation requirement of the semiconductor device, which is not limited in this application.
In the above embodiments of the present application, by etching the insulating layer and the stop layer on the semiconductor substrate, the plurality of first grooves and the plurality of second grooves with different shapes can be formed simultaneously, and the groove structure is formed after the plurality of first grooves and the plurality of second grooves are filled, so that the isolation requirements of transistor devices with different operating voltages on the same substrate can be met simultaneously for effective isolation between different semiconductor devices, such as a high-voltage transistor device, a low-voltage transistor device, and a low-voltage transistor device. And the groove structures with different shapes improve the isolation effect between devices to a certain extent, and are beneficial to the improvement of the performance of semiconductor devices.
In another embodiment of the present application, there is also provided a semiconductor device that may include a substrate divided into a plurality of high voltage device regions and non-high voltage regions, a stacked structure formed over the substrate, a plurality of first recess structures, and a plurality of second recess structures. Wherein the plurality of first groove structures are formed by filling an insulating material in the first grooves, the first grooves penetrate through the stacked structure and extend to at least a portion of the substrate corresponding to the high-voltage device region, and the width of the opening at the side away from the substrate is larger than the width of the opening at the side close to the substrate, and the plurality of second groove structures are formed by filling an insulating material in the second grooves penetrating through the stacked structure and extend to at least a portion of the substrate corresponding to the high-voltage device region.
The objects, technical solutions and advantageous effects of the present invention are further described in detail with reference to the above-described embodiments. It should be understood that the above description is only a specific embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims (18)
1. A method of manufacturing a semiconductor device, comprising:
sequentially depositing an insulating layer and a stop layer on a substrate, wherein the substrate comprises a high-voltage device area and a non-high-voltage device area, and the thickness of the insulating layer above the high-voltage device area is greater than that of the non-high-voltage device area;
forming a plurality of first grooves and a plurality of second grooves penetrating through the stop layer and the insulating layer respectively above a high-voltage device region and a non-high-voltage device region of the substrate;
etching a part of the stop layer above the first groove to enable the opening width of the first groove at the side far away from the substrate to be larger than the opening width at the side close to the substrate; and
further etching the bottoms of the first and second plurality of grooves such that the depths of the first and second grooves extend into at least a portion of the substrate.
2. The method of claim 1, wherein after the further etching process, the width of the opening of the second groove on the side away from the substrate is equal to the width of the opening on the side close to the substrate.
3. The method of claim 1 or 2, wherein the step of etching the portion of the stop layer above the first recess comprises:
filling and covering the second grooves by a patterned photoresist layer so that only the stop layer in the plurality of first grooves is etched during an etching process.
4. The method of claim 1, wherein after the further etching, the plurality of first grooves have the same projection profile along the extending direction of their respective grooves.
5. The method of claim 1, wherein after the further etching, the first plurality of grooves includes at least two grooves having different projection profiles along the groove extending direction.
6. The method of claim 1, wherein after the further etching, the second plurality of grooves comprises at least two grooves having different widths from each other.
7. The method of claim 1, wherein after the further etching, the width of each of the second grooves is the same.
8. The method of claim 1, wherein the step of sequentially depositing an insulating layer and a stop layer on the substrate comprises:
depositing a first insulating layer on the substrate;
removing at least one part of the first insulating layer above a non-high-voltage device area of the substrate through etching treatment; and
and depositing the stop layer on the insulating layer after the etching treatment.
9. The method of claim 1, wherein etching the bottoms of the first and second plurality of grooves extends the depth of the first and second grooves to at least a portion of the substrate, the method further comprising:
and filling the first groove and the second groove to form a filling layer.
10. The method of claim 9, wherein the material of the fill layer comprises an insulating material.
11. The method of claim 1, wherein the high voltage device region of the substrate is used to form a high voltage transistor device and the non-high voltage device region of the substrate is used to form a low voltage transistor device and a low voltage transistor device.
12. A semiconductor device, comprising:
a substrate divided into a plurality of high voltage device regions and non-high voltage regions;
a stacked structure formed over the substrate; and
a plurality of first groove structures formed by filling an insulating material in first grooves, the first grooves penetrating the stacked structure and extending to at least a portion of the substrate corresponding to the high-voltage device region, and having an opening width on a side away from the substrate larger than an opening width on a side close to the substrate; and
and a plurality of second groove structures formed by filling an insulating material in second grooves corresponding to at least a portion of the high-voltage device region, which penetrate the stacked structure and extend to the substrate.
13. The semiconductor device of claim 12, wherein the stacked structure comprises an insulating layer and a stop layer, wherein a thickness of the insulating layer over the high voltage device region is greater than a thickness over a non-high voltage device region.
14. The semiconductor device according to claim 12 or 13, wherein projection profiles of the plurality of first grooves in a direction in which their respective grooves extend are the same.
15. The semiconductor device according to claim 12 or 13, wherein the plurality of first grooves includes at least two kinds of grooves different in projection profile in a groove extending direction thereof.
16. The semiconductor device according to claim 12 or 13, wherein the plurality of second grooves includes at least two grooves different in width from each other.
17. The semiconductor device according to claim 12 or 13, wherein the width of each of the second grooves is the same.
18. The semiconductor device of claim 12, wherein the high voltage device region of the substrate is used to form a high voltage transistor device and the non-high voltage device region of the substrate is used to form a low voltage transistor device and a low voltage transistor device.
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| CN202111121722.9A CN113889433A (en) | 2021-09-24 | 2021-09-24 | Semiconductor device and method for manufacturing the same |
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| CN202111121722.9A CN113889433A (en) | 2021-09-24 | 2021-09-24 | Semiconductor device and method for manufacturing the same |
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