CN113517181A - Hard mask laminated structure and semiconductor device forming method - Google Patents
Hard mask laminated structure and semiconductor device forming method Download PDFInfo
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- CN113517181A CN113517181A CN202110460771.9A CN202110460771A CN113517181A CN 113517181 A CN113517181 A CN 113517181A CN 202110460771 A CN202110460771 A CN 202110460771A CN 113517181 A CN113517181 A CN 113517181A
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims description 28
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- 239000012792 core layer Substances 0.000 claims abstract description 102
- 239000000463 material Substances 0.000 claims abstract description 54
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- 238000000059 patterning Methods 0.000 claims abstract description 21
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 12
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 95
- 229910052710 silicon Inorganic materials 0.000 claims description 95
- 239000010703 silicon Substances 0.000 claims description 95
- 238000005530 etching Methods 0.000 claims description 93
- 125000006850 spacer group Chemical group 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 238000005240 physical vapour deposition Methods 0.000 description 10
- 238000002360 preparation method Methods 0.000 description 10
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- 238000012546 transfer Methods 0.000 description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
Abstract
The embodiment of the invention discloses a hard mask laminated structure used for a self-aligned quadruple-patterning process, which is characterized by comprising the following components in parts by weight: the circuit comprises a first hard mask layer, a first core layer and a second core layer which are arranged in a stacked mode, wherein the first core layer is located between the first hard mask layer and the second core layer; wherein the first hard mask layer comprises an amorphous carbon layer, the first core layer and the second core layer each comprising a spin-on carbon-containing material layer.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a hard mask stack structure and a semiconductor device.
Background
The Self-aligned quad Patterning (SAQP) process can obtain a pattern with a quarter of an exposure size through one exposure, and can greatly improve the integration of a semiconductor device.
The phase change memory is used for switching a phase change memory material between a crystalline phase and an amorphous phase by means of electric heating so as to realize data storage. The phase-change temperature of the phase-change storage material is low, and in order to improve the storage density and stabilize the performance of the phase-change storage material, a low-temperature SAQP process is needed to be matched in the process of forming a phase-change storage unit by etching.
At present, a low-temperature SAQP process with high performance and low cost is a key and difficult point for research and development of various semiconductor manufacturers.
Disclosure of Invention
Embodiments of the present invention provide a hard mask stack structure and a method for forming a semiconductor device to solve at least one of the problems of the related art.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a hard mask laminated structure which is used for a self-aligned quadruple-patterning process, and the hard mask laminated structure comprises: the circuit comprises a first hard mask layer, a first core layer and a second core layer which are arranged in a stacked mode, wherein the first core layer is located between the first hard mask layer and the second core layer;
wherein the first hard mask layer comprises an amorphous carbon layer, the first core layer and the second core layer each comprising a spin-on carbon-containing material layer.
In the foregoing solution, the hard mask stacked structure further includes a first silicon oxynitride layer, and the first silicon oxynitride layer is located between the first hard mask layer and the first core layer.
In the above aspect, the first silicon oxynitride layer has a thickness of
In the meantime.
In the foregoing scheme, the hard mask stacked structure further includes a second silicon oxynitride layer, and the second silicon oxynitride layer is located between the first core layer and the second core layer.
In the above aspect, the thickness of the second silicon oxynitride layer is within
In the meantime.
In the foregoing solution, the hard mask stacked structure further includes a third silicon oxynitride layer, where the third silicon oxynitride layer is located on a side of the second core layer away from the first core layer.
In the above aspect, the thickness of the third silicon oxynitride layer is
In the meantime.
In the foregoing scheme, the hard mask stacked structure further includes a silicon nitride layer, and the silicon nitride layer is located on one side of the first hard mask layer, which is far away from the first core layer.
In the scheme, the preparation temperature of the hard mask laminated structure is below 300 ℃.
The embodiment of the invention also provides a method for forming the semiconductor device, which is characterized by comprising the following steps:
providing a substrate, and forming a layer to be etched on the substrate;
forming a hard mask laminated structure on the layer to be etched; wherein the hard mask stack structure is the hard mask stack structure of any one of the above embodiments;
performing self-aligned quadruple patterning on the hard mask laminated structure to form a target mask pattern;
and etching the layer to be etched by taking the target mask pattern as a mask.
In the foregoing solution, the performing self-aligned quadruple patterning on the hard mask stack structure to form a target mask pattern includes:
performing a first etching on the hard mask laminated structure to form a first mandrel, wherein the first mandrel comprises a second core layer which is patterned after the first etching; forming a first sidewall layer at a sidewall location of the first mandrel; removing the first mandrel;
performing second etching on the hard mask laminated structure by taking the first side wall layer as a mask to form a second mandrel, wherein the second mandrel comprises the first side wall layer which is remained after the second etching and a first core layer which is patterned after the second etching; forming a second sidewall layer at a sidewall location of the second mandrel; removing the second mandrel;
and performing third etching on the hard mask laminated structure by taking the second side wall layer as a mask to form a target mask pattern, wherein the target mask pattern comprises the second side wall layer remained after the third etching and the first hard mask layer which is patterned after the third etching.
In the foregoing solution, the hard mask stacked structure further includes a third silicon oxynitride layer, where the third silicon oxynitride layer is located on a side of the second core layer away from the first core layer;
the performing a first etch on the hard mask stack structure to form a first mandrel includes:
and performing first etching on the third silicon oxynitride layer and the second core layer to form a first mandrel, wherein the first mandrel comprises the third silicon oxynitride layer and the second core layer which are patterned after the first etching.
In the above scheme, the hard mask laminated structure further includes a second silicon oxynitride layer, and the second silicon oxynitride layer is located between the second core layer and the first core layer;
the performing a first etch on the hard mask stack structure to form a first mandrel includes:
performing a first etching on the third silicon oxynitride layer, the second core layer and the second silicon oxynitride layer to form a first mandrel, the first etching being stopped in the second silicon oxynitride layer, the first mandrel including the third silicon oxynitride layer and the second core layer patterned after the first etching, and a portion of the second silicon oxynitride layer patterned after the first etching.
In the above solution, the hard mask laminated structure further includes a first silicon oxynitride layer, where the first silicon oxynitride layer is located between the first core layer and the first hard mask layer;
the second etching is performed on the hard mask laminated structure by taking the first side wall layer as a mask to form a second mandrel, and the method comprises the following steps:
and performing second etching on the part, which is not patterned after the first etching, of the second silicon oxynitride layer, the first core layer and the first silicon oxynitride layer by taking the first side wall layer as a mask to form a second mandrel, wherein the second etching is stopped in the first silicon oxynitride layer, and the second mandrel comprises a part, which is patterned after the second etching, of the second silicon oxynitride layer, a first core layer, which is patterned after the second etching, and a part, which is patterned after the second etching, of the first silicon oxynitride layer.
In the foregoing solution, the performing a third etching on the hard mask stacked structure to form a target mask pattern by using the second sidewall layer as a mask includes:
and taking the second side wall layer as a mask, and performing third etching on the part, which is not patterned, of the first silicon oxynitride layer after the second etching to form a target mask pattern, wherein the target mask pattern comprises the second side wall layer left after the third etching, the part, which is patterned, of the first silicon oxynitride layer after the third etching, and the first hard mask layer, which is patterned after the third etching.
In the foregoing aspect, the forming a first sidewall layer at a sidewall position of the first mandrel includes:
forming a first layer of spacer material overlying the first mandrel;
removing a portion of the first spacer material layer to form a first sidewall layer, wherein the first sidewall layer is located at a sidewall position of the first mandrel.
In the foregoing aspect, the forming a second sidewall layer at a sidewall position of the second mandrel includes:
forming a second spacer material layer overlying the second mandrel;
and removing part of the second spacer material layer to form a second side wall layer, wherein the second side wall layer is positioned at the position of the side wall of the second mandrel.
In the above scheme, the hard mask laminated structure further includes a silicon nitride layer, where the silicon nitride layer is located on one side of the first hard mask layer away from the first core layer;
the etching the layer to be etched by taking the target mask pattern as a mask comprises the following steps:
and etching the silicon nitride layer and the layer to be etched by taking the target mask pattern as a mask.
In the above scheme, the layer to be etched includes a phase change memory cell stack.
The embodiment of the invention provides a hard mask laminated structure and a method for forming a semiconductor device, wherein the hard mask laminated structure is used for a self-aligned quadruple-patterning process, and comprises the following steps: the circuit comprises a first hard mask layer, a first core layer and a second core layer which are arranged in a stacked mode, wherein the first core layer is located between the first hard mask layer and the second core layer; wherein the first hard mask layer comprises an amorphous carbon layer, the first core layer and the second core layer each comprising a spin-on carbon-containing material layer. The hard mask laminated structure can be prepared in a temperature range below 300 ℃, and can be applied to a preparation process of a semiconductor device based on a low-temperature process; in addition, the hard mask laminated structure has good line width consistency and edge roughness, and can realize pattern transfer with extremely small line width (less than 10nm) when being applied to a self-aligned quadruple patterning process.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a diagram illustrating a hard mask stack structure according to an embodiment of the present invention;
fig. 2 is a flow chart of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 3a to 3k are process flow diagrams of methods for forming a semiconductor device according to embodiments of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As the development of the semiconductor industry gradually enters the post-molar era, the development of low-line-width and high-density manufacturing processes becomes the focus of the development of various semiconductor manufacturers. The limit of the pitch size of the currently widely used 192nm lithography machine is 80nm, and the pitch size can only be made 40nm by the SADP process. As the integration degree of semiconductor devices is gradually increased, the conventional one-shot exposure or SADP process has not been able to meet the requirements. Meanwhile, the existing EUV lithography machine is high in use cost, and large-scale use is difficult to realize at present.
In order to further reduce the pitch size without increasing the cost, each semiconductor manufacturer starts to develop a self-aligned quad-patterning (SAQP) process, which can greatly reduce the pitch size and greatly improve the integration of the semiconductor device.
The SAQP process requires multiple pattern transfers through the hard mask material, which imposes strict requirements on the hard mask material selected in the process. To date, the hard mask materials provided in the prior art for application to the SAQP process mainly suffer from the following two problems:
firstly, the preparation temperature of the hard mask material is too high to be applied to the preparation process of the semiconductor device based on the low-temperature process, such as the phase change memory;
second, the line width uniformity and edge roughness of the hard mask material still need to be improved.
Based on this, the following technical solutions of the embodiments of the present invention are proposed.
The embodiment of the invention provides a hard mask laminated structure which is used for a self-aligned quadruple-patterning process, and the hard mask laminated structure comprises: the circuit comprises a first hard mask layer, a first core layer and a second core layer which are arranged in a stacked mode, wherein the first core layer is located between the first hard mask layer and the second core layer; wherein the first hard mask layer comprises an amorphous carbon layer, the first core layer and the second core layer each comprising a spin-on carbon-containing material layer.
The hard mask laminated structure can be prepared at the temperature below 300 ℃, can be applied to a self-aligned four-repeat patterning process of a semiconductor device based on a low-temperature process, such as a phase change memory, and can stabilize the performance of a phase change memory material when being applied to the preparation process of the phase change memory. But not limited thereto, the hard mask stack structure may also be applied to a self-aligned quadruple patterning process of other semiconductor devices.
The hard mask laminated structure has good line width consistency and edge roughness, and can realize the pattern transfer of a very small line width (less than 10nm) when being applied to a self-aligned quadruple-patterning process.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention.
Fig. 1 is a schematic diagram of a hard mask stack structure according to an embodiment of the present invention. As shown, the hard mask laminated structure 13 includes a first hard mask layer 132, a first core layer 134, and a second core layer 136, which are stacked, wherein the first core layer 134 is located between the first hard mask layer 132 and the second core layer 136; wherein the first hard mask layer 132 comprises an amorphous carbon layer, and the first core layer 134 and the second core layer 136 each comprise a spin-on carbon-containing material layer.
The first hard mask layer 132 may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).
The first hard mask layer 132 has a thickness of
In one embodiment, the thickness of the first hard mask layer 132 is
The first hard mask layer 132 includes an amorphous carbon layer having a very high hardness to maintain a good roughness.
The first core layer 134 and the second core layer 136 each include a spin-coated carbon-containing material layer formed by spin coating, and the spin-coated carbon-containing material layer may be a fluorine-free carbon-containing material.
In order to ensure the uniformity of the film, the above spin-coated carbon-containing material layer should be ensured to have a sufficient thickness. In some embodiments, the thickness of the spin-coated carbon-containing material layer may be within
In between, e.g.
The first hard mask layer, the first core layer and the second core layer are main pattern transfer layers in the hard mask laminated structure, but not limited thereto, in order to improve line width consistency and edge roughness, the hard mask laminated structure may further include other functional film layers.
In an embodiment, the hard mask stacked structure 13 further includes a first silicon oxynitride layer 133, wherein the first silicon oxynitride layer 133 is located between the first hard mask layer 132 and the first core layer 134.
The first silicon oxynitride layer not only participates in pattern transmission, but also serves as an etching barrier layer, the thickness of the first silicon oxynitride layer is more critical, and the excessive thickness can cause the excessive thickness of the spacing material layer formed above the first silicon oxynitride layer, so that the characteristic dimension can not reach the target requirement; being too thin may damage the underlying mask layer. In some embodiments, the first silicon oxynitride layer has a thickness of
In between, e.g.
The first silicon oxynitride layer is prepared by a method including, but not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).
In an embodiment, the hard mask stack structure 13 further includes a second silicon oxynitride layer 135, and the second silicon oxynitride layer 135 is located between the first core layer 134 and the second core layer 136.
In one embodiment, the thickness of the second silicon oxynitride layer is the same as the thickness of the first silicon oxynitride layer.
The second silicon oxynitride layer has a similar function to that of the first silicon oxynitride layer, and is used for both participating in pattern transfer and serving as an etching barrier layer.
In some embodiments, the second silicon oxynitride layer may have a thickness of
In between, e.g.
The second silicon oxynitride layer may be prepared by a method including, but not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).
In an embodiment, the hard mask stacked structure 13 further includes a third silicon oxynitride layer 137, and the third silicon oxynitride layer 137 is located on a side of the second core layer 136 away from the first core layer 134.
The third silicon oxynitride layer may be formed by a method including, but not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and the like.
In an embodiment, a thickness of the third silicon oxynitride layer is smaller than a thickness of the first silicon oxynitride layer and a thickness of the second silicon oxynitride layer.
The thickness of the third silicon oxynitride layer determines the lithography quality of the photoresist, and the thickness of the third silicon oxynitride layer is preferably set to
In between, e.g.
In an embodiment, the hard mask stack 13 further includes a silicon nitride layer 131, and the silicon nitride layer 131 is located on a side of the first hard mask layer 132 away from the core layer 134.
The silicon nitride layer can be prepared by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) or the like.
In the above embodiments, the temperature for fabricating the hardmask stack structure is below 300 ℃.
The preparation temperature of the hard mask laminated structure is 300 ℃ or lower, which means that the preparation temperature of each material layer constituting the hard mask laminated structure is 300 ℃ or lower. The preparation temperature not only refers to the deposition temperature or the formation temperature of a certain material layer, but also includes the temperature of post-treatment after deposition is finished.
In a specific embodiment, the preparation temperature of the hard mask laminated structure is between 200 ℃ and 300 ℃.
In the hard mask laminated structure provided by the embodiment of the invention, the cost of the silicon nitride layer, the first silicon oxynitride layer, the second silicon oxynitride layer and the carbon-containing material layer is lower, so that the hard mask laminated structure provided by the embodiment of the invention also has the advantage of low cost.
An embodiment of the present invention further provides a method for forming a semiconductor device, as shown in fig. 2, the method includes the following steps:
and 204, etching the layer to be etched by taking the target mask pattern as a mask.
The method for forming the semiconductor device according to the embodiment of the present invention will be described in further detail with reference to fig. 3a to 3 k.
First, as shown in fig. 3a, step 201 is performed to provide a substrate 11, and a layer to be etched 12 is formed on the substrate 11.
The material of the substrate may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide.
The layer to be etched is used for forming the semiconductor device; the layer to be etched may be a single-layer film or may include multiple layers of films.
Next, as shown in fig. 3b, step 202 is executed to form a hard mask stack structure 13 on the layer to be etched 12, where the hard mask stack structure 13 includes the hard mask stack structure described in any of the foregoing embodiments, and details are not repeated herein.
Then, step 203 is performed to perform self-aligned quadruple patterning on the hard mask stack structure 13 to form a target mask pattern 23, as shown in fig. 3c-3 j.
The self-aligned quadruple patterning comprises the following steps:
first, as shown in fig. 3c, a patterned photoresist layer 14 is formed on the hard mask stack structure 13. The method for forming the patterned photoresist layer 14 is well known in the art and will not be described herein.
Next, using the patterned photoresist layer 14 as a mask, a first etching is performed on the hard mask stack 13 to form a first mandrel 21, as shown in fig. 3 d.
In one embodiment, the first mandrel 21 includes a second core layer 136' patterned after the first etching.
In an embodiment, the hard mask stacked structure 13 further includes a third silicon oxynitride layer 137, where the third silicon oxynitride layer 137 is located on a side of the second core layer 136 away from the first core layer 134;
the performing a first etching on the hard mask stack structure 13 to form a first mandrel 21 includes:
a first etching is performed on the third silicon oxynitride layer 137 and the second core layer 136 to form the first mandrel 21, which includes the third silicon oxynitride layer 137 'and the second core layer 136' patterned after the first etching.
In an embodiment, the hard mask stack structure 13 further includes a second silicon oxynitride layer 135, the second silicon oxynitride layer 135 being located between the second core layer 136 and the first core layer 134;
the performing a first etching on the hard mask stack structure 13 to form a first mandrel 21 includes:
performing a first etching on the third silicon oxynitride layer 137, the second core layer 136 and the second silicon oxynitride layer 135 to form a first mandrel 21, the first etching being stopped in the second silicon oxynitride layer 135, the first mandrel 21 including a third silicon oxynitride layer 137' and a second core layer 136' patterned after the first etching, and a portion 1351' patterned after the first etching of the second silicon oxynitride layer.
Next, referring to fig. 3e, a first spacer material layer 15 is formed on the first mandrel 21.
The first spacer material layer 15 is used for forming a first sidewall layer 15' subsequently, and the material thereof may be nitride, silicon oxide or other suitable materials.
In a specific embodiment, the first spacer material layer is silicon oxide.
The first spacer material layer may be formed by a Chemical Vapor Deposition (CVD) method, an Atomic Layer Deposition (ALD) method, or the like. In one embodiment, the first spacer material layer is formed using Atomic Layer Deposition (ALD). The atomic layer deposition method has better filling performance, so that the formed first spacing material layer can be ensured to well cover the side wall area of the patterned core layer, and the quality and the yield of the subsequently formed first side wall layer are further ensured.
After the first spacer material layer 15 is formed, the first spacer material layer 15 is etched back to obtain a first sidewall layer 15', and the first sidewall layer 15' is located at a sidewall position of the first mandrel 21.
By controlling the thickness of the first spacer material layer 15 and the process parameters of the etch back, the line width of the first sidewall layer 15' can be controlled.
Next, the first mandrel 21 is removed, as shown in fig. 3 f.
The pattern period of the first sidewall layer 15' is half of the pattern period of the patterned photoresist layer 14, achieving a multiplication of the spatial pattern density.
Next, using the first sidewall layer 15' as a mask, a second etching is performed on the hard mask stack 13 to form a second mandrel 22, as shown in fig. 3 g.
In one embodiment, the second mandrel 22 includes the first sidewall layer 15 ″ remaining after the second etching and the first core layer 134' patterned after the second etching.
In one embodiment, the hard mask stack 13 further includes a first silicon oxynitride layer 133, the first silicon oxynitride layer 133 being located between the first core layer 134 and the first hard mask layer 132;
the second etching is performed on the hard mask laminated structure 13 by using the first sidewall layer 15' as a mask to form a second mandrel 22, including:
performing a second etching on the unpatterned portion 1352 of the second silicon oxynitride layer after the first etching, the first core layer 134 and the first silicon oxynitride layer 133 to form a second mandrel 22 with the first sidewall layer 15 'as a mask, the second etching being stopped in the first silicon oxynitride layer 133, the second mandrel 22 including a portion 1352' of the second silicon oxynitride layer patterned after the second etching, a first core layer 134 'of the second core layer patterned after the second etching, and a portion 1331' of the first silicon oxynitride layer patterned after the second etching.
After forming the second mandrel 22, referring to fig. 3h, a second spacer material layer 16 is formed on the second mandrel 22.
The second spacer material layer 16 is used to subsequently form a second sidewall layer 16', which may be a nitride, an oxide of silicon, or other suitable material.
In an embodiment, the material of the second spacer material layer 16 is the same as the material of the first spacer material layer 15.
The second spacer material layer is formed by a method including, but not limited to, Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD).
After forming the second spacer material layer 16, etching back the second spacer material layer 16 to obtain a second sidewall layer 16', where the second sidewall layer 16' is located at a sidewall position of the second mandrel 22.
By controlling the thickness of the second spacer material layer 16 and the process parameters of the etch-back, the line width of the second sidewall layer 16' can be controlled.
Next, the second mandrel 22 is removed, see fig. 3 i.
The pattern period of the second sidewall layer 16 'is one fourth of the pattern period of the patterned photoresist layer 14, and the pattern density of the second sidewall layer 16' is 4 times the pattern density of the patterned photoresist layer 14.
Next, referring to fig. 3j, a third etching is performed on the hard mask stack 13 using the second sidewall layer 16' as a mask to form a target mask pattern 23.
In one embodiment, the target mask pattern 23 includes the second sidewall layer 16 ″ remaining after the third etching and the first hard mask layer 132' patterned after the third etching.
In one embodiment, the target mask pattern 23 includes the second sidewall layer 16 ″ remaining after the third etching, the patterned portion 1332 'of the first silicon oxynitride layer after the third etching, and the patterned first hard mask layer 132' after the third etching.
To this end, the self-aligned quadruple patterning provided by the embodiment of the present invention is completed to form a target mask pattern, and the pattern density of the target mask pattern is 4 times that of the photoresist layer. The self-aligned quadruple-patterning provided by the embodiment of the invention can realize the pattern transfer of the extremely small line width (less than 10nm) based on the photoetching machine with lower resolution. In addition, the self-aligned quadruple patterning provided by the implementation of the invention can be applied to the preparation process of the semiconductor device based on the low-temperature process.
Next, referring to fig. 3k, step 204 is performed to etch the layer to be etched 12 by using the target mask pattern 23 as a mask, so as to obtain a patterned layer to be etched 12'.
In an embodiment, the hard mask stacked structure 13 further includes a silicon nitride layer 131, wherein the silicon nitride layer 131 is located on a side of the first hard mask layer 132 away from the first core layer 134;
the etching the layer to be etched 12 by using the target mask pattern 23 as a mask includes:
and etching the silicon nitride layer 131 and the layer to be etched 12 by using the target mask pattern 23 as a mask to obtain a patterned silicon nitride layer 131 'and a patterned layer to be etched 12'.
In one embodiment, the layer to be etched 12 includes a phase change memory cell stack for forming a phase change memory.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (19)
1. A hardmask stack structure for use in a self-aligned quadruple patterning process, the hardmask stack structure comprising: the circuit comprises a first hard mask layer, a first core layer and a second core layer which are arranged in a stacked mode, wherein the first core layer is located between the first hard mask layer and the second core layer;
wherein the first hard mask layer comprises an amorphous carbon layer, the first core layer and the second core layer each comprising a spin-on carbon-containing material layer.
2. The hard mask stack structure of claim 1, further comprising a first silicon oxynitride layer between the first hard mask layer and the first core layer.
3. The hardmask stack structure according to claim 2, wherein the first SiON layer has a thickness of
In the meantime.
4. The hard mask stack structure of claim 1, further comprising a second silicon oxynitride layer between the first core layer and the second core layer.
5. The hardmask stack structure according to claim 4, wherein the second silicon oxynitride layer has a thickness of
In the meantime.
6. The hard mask stack structure of claim 1, further comprising a third silicon oxynitride layer on a side of the second core layer remote from the first core layer.
7. The hardmask stack structure according to claim 6, wherein the third SiON isThe thickness of the layer is
In the meantime.
8. The hard mask stack structure of claim 1, further comprising a silicon nitride layer on a side of the first hard mask layer distal from the first core layer.
9. The hardmask stack structure according to any one of claims 1-8, wherein the hardmask stack structure is prepared at a temperature of less than 300 ℃.
10. A method of forming a semiconductor device, the method comprising:
providing a substrate, and forming a layer to be etched on the substrate;
forming a hard mask laminated structure on the layer to be etched; wherein the hard mask stack is the hard mask stack of any one of claims 1-9;
performing self-aligned quadruple patterning on the hard mask laminated structure to form a target mask pattern;
and etching the layer to be etched by taking the target mask pattern as a mask.
11. The method of claim 10, wherein the self-aligned quadruple patterning of the hard mask stack structure to form a target mask pattern comprises:
performing a first etching on the hard mask laminated structure to form a first mandrel, wherein the first mandrel comprises a second core layer which is patterned after the first etching; forming a first sidewall layer at a sidewall location of the first mandrel; removing the first mandrel;
performing second etching on the hard mask laminated structure by taking the first side wall layer as a mask to form a second mandrel, wherein the second mandrel comprises the first side wall layer which is remained after the second etching and a first core layer which is patterned after the second etching; forming a second sidewall layer at a sidewall location of the second mandrel; removing the second mandrel;
and performing third etching on the hard mask laminated structure by taking the second side wall layer as a mask to form a target mask pattern, wherein the target mask pattern comprises the second side wall layer remained after the third etching and the first hard mask layer which is patterned after the third etching.
12. The method of claim 11, wherein the hard mask stack structure further comprises a third silicon oxynitride layer on a side of the second core layer remote from the first core layer;
the performing a first etch on the hard mask stack structure to form a first mandrel includes:
and performing first etching on the third silicon oxynitride layer and the second core layer to form a first mandrel, wherein the first mandrel comprises the third silicon oxynitride layer and the second core layer which are patterned after the first etching.
13. The method of forming a semiconductor device according to claim 12, wherein the hard mask stack structure further comprises a second silicon oxynitride layer between the second core layer and the first core layer;
the performing a first etch on the hard mask stack structure to form a first mandrel includes:
performing a first etching on the third silicon oxynitride layer, the second core layer and the second silicon oxynitride layer to form a first mandrel, the first etching being stopped in the second silicon oxynitride layer, the first mandrel including the third silicon oxynitride layer and the second core layer patterned after the first etching, and a portion of the second silicon oxynitride layer patterned after the first etching.
14. The method of claim 13, wherein the hard mask stack structure further comprises a first silicon oxynitride layer between the first core layer and the first hard mask layer;
the second etching is performed on the hard mask laminated structure by taking the first side wall layer as a mask to form a second mandrel, and the method comprises the following steps:
and performing second etching on the part, which is not patterned after the first etching, of the second silicon oxynitride layer, the first core layer and the first silicon oxynitride layer by taking the first side wall layer as a mask to form a second mandrel, wherein the second etching is stopped in the first silicon oxynitride layer, and the second mandrel comprises a part, which is patterned after the second etching, of the second silicon oxynitride layer, a first core layer, which is patterned after the second etching, and a part, which is patterned after the second etching, of the first silicon oxynitride layer.
15. The method for forming a semiconductor device according to claim 14, wherein the performing a third etching on the hard mask stack structure with the second sidewall layer as a mask to form a target mask pattern comprises:
and taking the second side wall layer as a mask, and performing third etching on the part, which is not patterned, of the first silicon oxynitride layer after the second etching to form a target mask pattern, wherein the target mask pattern comprises the second side wall layer left after the third etching, the part, which is patterned, of the first silicon oxynitride layer after the third etching, and the first hard mask layer, which is patterned after the third etching.
16. The method of claim 11, wherein the forming a first sidewall layer at a sidewall location of the first mandrel comprises:
forming a first layer of spacer material overlying the first mandrel;
removing a portion of the first spacer material layer to form a first sidewall layer, wherein the first sidewall layer is located at a sidewall position of the first mandrel.
17. The method of claim 11, wherein forming a second sidewall layer at a sidewall location of the second mandrel comprises:
forming a second spacer material layer overlying the second mandrel;
and removing part of the second spacer material layer to form a second side wall layer, wherein the second side wall layer is positioned at the position of the side wall of the second mandrel.
18. The method of claim 10, wherein the hard mask stack structure further comprises a silicon nitride layer on a side of the first hard mask layer remote from the first core layer;
the etching the layer to be etched by taking the target mask pattern as a mask comprises the following steps:
and etching the silicon nitride layer and the layer to be etched by taking the target mask pattern as a mask.
19. The method for forming a semiconductor device according to any one of claims 10 to 18, wherein the layer to be etched includes a phase-change memory cell stack.
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