CN107482008B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory device region and a peripheral device region, the memory device region and the peripheral device region are isolated by an isolation structure, and a gate material layer is formed on the semiconductor substrate; forming a flowable oxide layer on the gate material layer, the flowable oxide layer having a flat surface; forming a control gate hard mask layer on the flowable oxide layer; imaging the control gate hard mask layer; forming a graphical grid hard mask layer on the control grid hard mask layer; and etching the grid material layer by taking the patterned control grid hard mask layer and the grid hard mask layer as masks to form a control grid in the storage device area and form a grid in the peripheral device area. The manufacturing method can overcome the gate defect caused by the STI step height. The semiconductor device and the electronic device have the advantages of less defects and higher performance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
NAND flash memory has become the mainstream non-volatile memory technology at present, is widely applied to various fields such as data center, personal computer, cell phone, intelligent terminal, consumer electronics, and still presents a situation of continuously increasing demand. NAND flash memory generally includes a memory device region and a peripheral device region, which are usually isolated by a Shallow Trench Isolation (STI), and the Step height (Step height) of the STI has a significant influence on the pattern formation in the control gate/gate etching process of the NAND flash memory. This is because the STI in the memory device region and the peripheral device region generally have a large step height, and a recessed region (recessed area) is formed in a film layer formed on the STI corresponding region, which makes the bottom anti-reflection layer (BARC) on the region thicker, and the amount of over-etching needs to be increased in order to remove the thicker bottom anti-reflection layer (BARC) on the region. This still presents challenges for the 38nm technology node and below, because the photoresist layer (PR) thickness is small and severe residue problems are observed in the recessed regions of the STI, affecting the performance of the final device.
Therefore, in order to overcome the gate defect caused by the STI step height, it is necessary to provide a new manufacturing method to solve the above problem.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which can overcome the gate defect caused by the STI step height, thereby improving the performance of a flash memory.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory device region and a peripheral device region, the memory device region and the peripheral device region are separated by an isolation structure, and a gate material layer is formed on the semiconductor substrate; forming a flowable oxide layer on the gate material layer, the flowable oxide layer having a planar surface; forming a control gate hard mask layer on the flowable oxide layer; imaging the control gate hard mask layer, wherein the imaged control gate hard mask layer is provided with a control gate pattern positioned in the storage device area; forming a graphical grid hard mask layer on the control grid hard mask layer, wherein the graphical grid hard mask layer is provided with a grid pattern located in a peripheral device area; and etching the grid material layer by taking the patterned control grid hard mask layer and the grid hard mask layer as masks so as to form a control grid in the storage device area and form a grid in the peripheral device area.
Preferably, the flowable oxide layer is a flowable chemical vapour deposition oxide layer, a graphene oxide layer or a graphite oxide layer.
Preferably, the control gate hard mask layer comprises a hard mask material and an anti-reflection material.
Preferably, the control gate hard mask layer is formed by single pattern or double pattern etching.
Preferably, the patterning of the control gate hard mask layer and the forming of the patterned gate hard mask layer are completed in the same step.
Preferably, the gate material layer includes a floating gate material layer, a gate dielectric layer, a control gate material layer and a hard mask layer.
Preferably, after the flowable oxide layer is formed on the gate material layer, an annealing step is further included.
According to the manufacturing method of the semiconductor device, the flowing oxide layer is formed below the control gate hard mask layer to reduce the step height, and the flowing oxide layer has a flat surface, so that the thickness of a pit reflection layer used for subsequently etching the control gate hard mask layer is consistent, an anti-reflection layer in an STI (shallow trench isolation) concave area does not need to be removed through etching, the residual problem caused by the anti-reflection layer is reduced, and the performance of the device is improved.
Another aspect of the present invention provides a semiconductor device manufactured by the above manufacturing method, the semiconductor device including: the semiconductor substrate comprises a storage device region and a peripheral device region, wherein the storage device region and the peripheral device region are separated by an isolation structure, and a grid stack comprising a floating grid, a grid dielectric layer and a control grid is formed in the storage device region and the peripheral device region.
The semiconductor device provided by the invention has fewer defects and higher performance.
Still another aspect of the present invention provides an electronic device including the semiconductor device described above and an electronic component connected to the semiconductor device.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a flow chart of steps of a method of fabricating a semiconductor device according to an embodiment of the invention;
fig. 2A to 2E are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 3 illustrates a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 4 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
FIG. 1 shows a flow chart of steps of a method of fabricating a semiconductor device according to an embodiment of the invention; fig. 2A to 2E are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method for manufacturing a semiconductor device according to an embodiment of the present invention.
The invention provides a manufacturing method of a semiconductor device, as shown in fig. 1, the main steps of the manufacturing method include:
in step 101, providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory device region and a peripheral device region, the memory device region and the peripheral device region are separated by an isolation structure, and a gate material layer is formed on the semiconductor substrate;
in step 102, forming a flowable oxide layer on the gate material layer, wherein the flowable oxide layer has a flat surface;
in step 103, forming a control gate hard mask layer on the flowable oxide layer;
in step 104, patterning the control gate hard mask layer, wherein the patterned control gate hard mask layer has a control gate pattern located in the memory device region;
in step 105, forming a patterned gate hard mask layer on the control gate hard mask layer, wherein the patterned gate hard mask layer has a gate pattern located in a peripheral device region;
in step 106, the gate material layer is etched by using the patterned control gate hard mask layer and the patterned gate hard mask layer as masks, so as to form a control gate in the memory device region and a gate in the peripheral device region.
According to the manufacturing method of the invention, the step height is reduced by forming the flowing oxide layer below the control gate hard mask layer, and the flowing oxide layer has a flat surface, so that the thickness of a pit reflection layer used for subsequently etching the control gate hard mask layer is consistent, an anti-reflection layer in an STI (shallow trench isolation) concave area does not need to be removed by over-etching, the residual problem caused by over-etching is reduced, and the performance of the device is improved.
Next, a detailed description will be given of a specific embodiment of a method for manufacturing a semiconductor device according to the present invention with reference to fig. 2A to 2E.
First, as shown in fig. 2A, a semiconductor substrate 200 is provided, the semiconductor substrate 200 including a memory device region and a peripheral device region, the memory device region and the peripheral device region being isolated by an isolation structure 201. A gate material layer including a floating gate material layer 202, a gate dielectric layer 203, a control gate material layer 204 and a first hard mask layer material layer 205 is formed on each of the memory device region and the peripheral device region, a flowable oxide layer 206 is formed on the gate material layer, and a control gate hard mask layer 207, a second hard mask layer 208, a bottom anti-reflection layer 209 and a patterned photoresist layer 210 are formed on the flowable oxide layer 206.
Specifically, the semiconductor substrate 200 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon.
Illustratively, the isolation structure 201 is a Shallow Trench Isolation (STI), which may be formed by an etching and filling process commonly used in the art and will not be described herein again. Illustratively, the left portion of the isolation structure 201 is a memory device region and the right portion is a peripheral device region. As shown in fig. 2A, since the isolation structure 201 is used to isolate the memory device region and the peripheral device region, it has a large step height (step height).
The floating gate material layer 202, the gate dielectric layer 203, the control gate material layer 204 and the first hard mask layer material layer 205 are formed on the semiconductor substrate 200 by a method commonly used in the art. Alternatively, the deposition method of the floating gate material layer 202 may be one of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). A gate dielectric layer 203 is formed on the floating gate material layer 202, wherein the gate dielectric layer 203 may be made of an insulating material commonly used in the art, such as one or more of oxide and nitride. For example, in this embodiment, the gate dielectric layer 203 is ONO (oxide-nitride-oxide structure constituting the gate dielectric layer). A control gate material layer 204 is formed on the gate dielectric layer 203, wherein the control gate material layer 204 may be made of a semiconductor material, such as silicon, polysilicon, Ge, or the like, but is not limited to a certain material, and in this embodiment, the control gate material layer 204 is made of polysilicon. A first hard mask layer 205 is formed on the control gate material layer 204, and the first hard mask layer 205 may be made of a conventional hard mask material, such as oxide, nitride, or the like. In this embodiment, the first hard mask layer 205 is made of silicon oxide, which can be formed by thermal oxidation, chemical vapor deposition, physical vapor deposition, atomic layer deposition, furnace oxidation, and the like.
The isolation structure 201 has a larger step height, so that the floating gate material layer 202, the gate dielectric layer 203, the control gate material layer 204 and the first hard mask layer material layer 205 formed in the region have a recessed region, and if an anti-reflection layer is directly formed on the recessed region, the thickness of the recessed region is larger than that of other regions, so that residues are easily generated, and the device performance is affected. Therefore, in the present embodiment, the flowable oxide layer 206 is formed on the gate material layer, and the flowable oxide layer 206 has a flat surface, so that the step height of the isolation structure 201 can be reduced, and the thickness of the subsequent film deposited thereon is uniform, so that no excessive over-etching is required during the removal process, and the residue is not easily generated. The flowable oxide layer 206 may be formed by a Flowable Chemical Vapor Deposition (FCVD), graphene oxide, or graphite oxide process. In the present embodiment, the flowable oxide layer 206 is formed by a flowable chemical vapor deposition process.
After the flowable oxide layer 206 is formed, a control gate hard mask layer 207, a second hard mask layer 208, a bottom anti-reflective layer 209, and a patterned photoresist layer 210 are formed on the flowable oxide layer 206. The control gate hard mask layer 207, the second hard mask layer 208, the bottom anti-reflection layer 209 and the patterned photoresist layer 210 are formed by using materials and processes commonly used in the art, for example, the control gate hard mask layer 207 may be formed by using silicon oxide, nitride or oxynitride of the second hard mask layer 208, low temperature oxide and suitable organic substances (such as ODL, NFC, etc.), the bottom reflective layer 209 is formed by using silicon-containing anti-reflection layer, and the patterned photoresist layer 210 is formed by using a commonly used positive or negative photoresist and is patterned by a corresponding exposure and development process. The patterned photoresist layer 210 has a pattern corresponding to the pattern of the control gates of the memory device regions.
Next, as shown in fig. 2B, the control gate hard mask layer 207 is patterned, i.e., the pattern of the patterned photoresist layer 210 is transferred to the control gate hard mask layer 207, and the patterned control gate hard mask layer 207 has a control gate pattern in the memory device region. Specifically, the bottom anti-reflection layer 209 and the second hard mask layer 208 are etched by a suitable dry or wet etching process using the patterned photoresist layer 210 as a mask, the pattern is transferred onto the bottom anti-reflection layer 209 and the second hard mask layer 208, and then the patterned photoresist layer 210 is removed by a suitable volume or ashing method. Next, the control gate hard mask layer 207 is etched by a suitable dry or wet etching process using the patterned bottom anti-reflection layer 209 and the second hard mask layer 208 as masks, and the pattern is transferred onto the control gate hard mask layer 207.
Next, as shown in fig. 2C, a gate hard mask layer 211, a bottom anti-reflection layer 212, and a patterned photoresist layer 213 are formed on the patterned control gate hard mask layer 207. The gate hard mask layer 211, the bottom anti-reflection layer 212 and the patterned photoresist layer 213 are formed by using materials and processes commonly used in the art, for example, the gate hard mask layer 211 may be formed by using silicon oxide, nitride or oxynitride, low temperature oxide and suitable organic (such as ODL, NFC, etc.), the bottom anti-reflection layer 212 may be formed by using silicon-containing anti-reflection layer, and the patterned photoresist layer 213 may be formed by using a commonly used positive or negative resist and patterned by using corresponding exposure and development processes. The patterned photoresist layer 213 has a pattern corresponding to the gate pattern of the peripheral device region.
Next, as shown in fig. 2D, the gate hard mask layer 211 is patterned, and the patterned gate hard mask layer 211 has a gate pattern in the peripheral device region. Specifically, the bottom anti-reflection layer 212 and the gate hard mask layer 211 are etched by a suitable wet or dry etching process with the patterned photoresist layer 213 as a mask, the pattern of the patterned photoresist layer 213 is transferred to the gate hard mask layer 211, and then the patterned photoresist layer 213 is removed.
Finally, as shown in fig. 2E, the gate material layer is etched by using the patterned control gate hard mask layer 207 and the patterned gate hard mask layer 211 as masks, so as to form a control gate in the memory device region and a gate in the peripheral device region.
Specifically, the patterned control gate hard mask layer 207 and the gate hard mask layer 211 are used as masks to etch the flowable oxide layer 206 and the first hard mask layer 205 through a suitable wet or dry etching process, the patterns are transferred onto the first hard mask layer 205, then the patterned control gate hard mask layer 207, the gate hard mask layer 211 and the flowable oxide layer 206 are removed, the patterned first hard mask layer 205 is used as a mask to etch the control gate material layer 204, the gate dielectric layer 203 and the floating gate material layer 202 through a suitable wet or dry etching process, so that a control gate is formed in the memory device region, and a gate is formed in the peripheral device region.
Now that the process steps performed by the method according to the embodiment of the present invention are completed, it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps, such as ion doping, before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device according to the embodiment of the present invention.
It is understood that the etching process in this embodiment may be a wet etching process or a dry etching process, the wet etching process includes a wet etching process such as hydrofluoric acid, phosphoric acid, etc., and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting.
Further, although in the present embodiment, the control gate is patterned by single pattern lithography, in other embodiments, double or multiple pattern lithography may be used, and a sacrificial material layer, such as amorphous carbon, may be included in the second mask layer or the control gate hard mask layer to facilitate the double or multiple pattern lithography. Furthermore, although in the present embodiment the patterning of the memory device region and the patterning of the peripheral device region are performed in two steps, in other embodiments, the patterning of the memory device region and the patterning of the peripheral device region may be performed in only one step, for example, by the photoresist layer 210 including both the pattern corresponding to the control gate and the pattern corresponding to the gate of the peripheral device region, or in one step, without performing the steps shown in fig. 2C and 2D.
It is also understood that the method for manufacturing a semiconductor device according to the present embodiment can be used to manufacture not only a flash memory device, but also other devices having a stacked gate structure, which are similarly suitable for the method.
Example two
The present invention also provides a semiconductor device manufactured by the above manufacturing method, as shown in fig. 3, the semiconductor device includes: the semiconductor device comprises a semiconductor substrate 300, wherein the semiconductor substrate 300 comprises a memory device region and a peripheral device region, the memory device region and the peripheral device region are separated by an isolation structure 301, and a gate stack comprising a floating gate 302, a gate dielectric layer 303 and a control gate 304 is formed in the memory device region and the peripheral device region.
Wherein the semiconductor substrate 300 may be at least one of the following mentioned materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like.
The isolation structure 301 is a Shallow Trench Isolation (STI) structure, which can be formed by etching and filling processes commonly used in the art, and is not described herein again. Illustratively, the left portion of the isolation structure 301 is a memory device region and the right portion is a peripheral device region.
The floating gate 302, gate dielectric layer 303, and control gate layer 304 may be deposited using processes commonly used in the art. Alternatively, the semiconductor substrate 300 may be deposited by one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG), thermal oxidation, chemical vapor deposition, physical vapor deposition, atomic layer deposition, furnace tube oxidation, and the like. The floating gate 302 and the control gate 304 may be made of polysilicon, and the gate dielectric layer 303 may be made of one or more of oxide and nitride, for example. For example, in this embodiment, the gate dielectric layer 303 is ONO (oxide-nitride-oxide structure constituting the gate dielectric layer). After the deposition is completed, the semiconductor device of the embodiment can be obtained by performing the patterning, and the semiconductor device of the embodiment has fewer defects and higher performance.
EXAMPLE III
Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor substrate comprises a storage device region and a peripheral device region, wherein the storage device region and the peripheral device region are separated by an isolation structure, and a grid stack comprising a floating grid, a grid dielectric layer and a control grid is formed in the storage device region and the peripheral device region.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Wherein figure 4 shows an example of a handset. The exterior of the cellular phone 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.
The electronic device of the embodiment of the invention has the similar advantages because the electronic device contains fewer defects of semiconductor devices and has higher performance.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (6)
1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory device region and a peripheral device region, the memory device region and the peripheral device region are isolated by an isolation structure, a grid material layer is formed on the semiconductor substrate, and the grid material layer comprises a floating grid material layer, a grid dielectric layer, a control grid material layer and a first hard mask material layer;
forming a flowable oxide layer on the gate material layer, the flowable oxide layer having a planar surface;
forming a control gate hard mask layer on the flowable oxide layer;
imaging the control gate hard mask layer, wherein the imaged control gate hard mask layer is provided with a control gate pattern positioned in the storage device area;
forming a graphical grid hard mask layer on the control grid hard mask layer, wherein the graphical grid hard mask layer is provided with a grid pattern located in a peripheral device area;
and etching the grid material layer by taking the patterned control grid hard mask layer and the grid hard mask layer as masks so as to form a control grid in the storage device area and form a grid in the peripheral device area.
2. The method according to claim 1, wherein the flowable oxide layer is a flowable chemical vapor deposition oxide layer, a graphene oxide layer, or a graphite oxide layer.
3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the control gate hard mask layer comprises a hard mask material and an anti-reflective material.
4. The method of claim 1, wherein the patterned control gate hard mask layer is formed by single pattern or double pattern etching.
5. The method of claim 1, wherein the patterning the control gate hard mask layer and the forming the patterned gate hard mask layer are performed in the same step.
6. The method of claim 1, further comprising performing an annealing step after forming a flowable oxide layer on the gate material layer.
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