CN108336086B

CN108336086B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN108336086B
Application number: CN201710035429.8A
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd; Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-01-17
Filing date: 2017-01-17
Publication date: 2021-03-19
Anticipated expiration: 2037-01-17
Also published as: CN108336086A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, and forming a floating gate on the semiconductor substrate; and forming a control gate on the floating gate, wherein the floating gate comprises a main body part located above the semiconductor substrate and protruding parts located at two ends of the main body part and protruding towards the control gate. The manufacturing method can increase the grid capacitance between the control grid and the floating grid interface, improve the power consumption of the device and reduce the leakage current. The semiconductor device and the electronic apparatus have similar advantages.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

With the development of semiconductor process technology, flash memories (flash memories) with faster access speed have been developed for memory devices. Flash memory has the characteristics of being capable of storing, reading and erasing information for many times, and the stored information does not disappear after power failure, so flash memory has become a nonvolatile memory widely used in personal computers and electronic devices.

As devices shrink, the power consumption of flash memory becomes increasingly worse, and therefore ultra-shallow junctions and abrupt transitions have been used to improve the short channel effect of core devices. However, even in line with gate material requirements, balancing power consumption and capacitance control has become an increasingly challenging problem. To overcome this problem, more effort, pre-amorphization co-implantation, stress engineering, has been used to optimize the doping profile of the floating gate to improve device power consumption and capacitance control. These efforts still do not solve the above problems well.

Therefore, it is necessary to provide a semiconductor device and a method for fabricating the same to solve the above problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which can increase the grid capacitance between a control grid and a floating grid interface, improve the power consumption of the device and reduce the leakage current.

In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, and forming a floating gate on the semiconductor substrate; and forming a control gate on the floating gate, wherein the floating gate comprises a main body part located above the semiconductor substrate and protruding parts located at two ends of the main body part and protruding towards the control gate.

Further, the protruding portions are located at two ends of the floating gate in the length direction.

Further, still include:

forming a grid dielectric layer on the semiconductor substrate;

and forming an isolation structure and an active region divided by the isolation structure in the semiconductor substrate, wherein the floating gate is formed on a gate dielectric layer of the active region.

Further, the step of forming the isolation structure and the active region separated by the isolation structure in the semiconductor substrate includes: forming a floating gate material layer and a hard mask layer on the semiconductor substrate in sequence; etching the hard mask layer, the floating gate material layer, the gate dielectric layer and the semiconductor substrate to form a groove and an active region separated by the groove in the semiconductor substrate, and forming a main body part of the floating gate on the gate dielectric layer on the active region; filling the groove to form the isolation structure, wherein the height of the isolation structure is higher than the surface of the semiconductor substrate and lower than the body part of the floating gate; forming the protruding portions at both ends of the body portion of the floating gate; and removing the hard mask layer.

Further, the hard mask layer is used as a mask to form the protruding portions at two ends of the main body portion of the floating gate through an epitaxial process.

Further, the hard mask layer is nitride.

According to the manufacturing method of the semiconductor device, the protruding parts protruding towards the control gate are formed at the two ends of the floating gate main body part, so that the contact area of the floating gate and the control gate interface is increased, the gate capacitance of the interface between the control gate and the floating gate is increased, the power consumption of the device is further improved, and the leakage current is reduced.

Another aspect of the present invention provides a semiconductor device, including: a semiconductor substrate on which a floating gate is formed; a control gate is formed on the floating gate, wherein the floating gate includes a body portion located above the semiconductor substrate and protruding portions located at both ends of the body portion and protruding toward the control gate.

Further, the height of the isolation structure is higher than the surface of the semiconductor substrate and lower than the body portion of the floating gate.

Further, the semiconductor device further includes:

the semiconductor device comprises an isolation structure positioned in the semiconductor substrate and an active region divided by the isolation structure;

and a grid dielectric layer is formed on the active region, and the floating grid is formed on the grid dielectric layer of the active region.

Further, both ends of the main body portion are formed at least partially over the isolation structure.

The semiconductor device provided by the invention increases the grid capacitance between the control grid and the floating grid interface, improves the power consumption of the device and reduces the leakage current.

Still another aspect of the present invention provides an electronic device including a semiconductor device and an electronic component connected to the semiconductor device, the semiconductor device including:

the electronic device provided by the invention has similar advantages due to the semiconductor device.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 shows a schematic diagram of a flash memory cell and its equivalent capacitance representation;

FIG. 2 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;

fig. 3A to 3G are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 4 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 5 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Referring to fig. 1, a schematic diagram of a flash memory cell structure and an equivalent capacitance graph are shown, wherein the performance of the flash memory is mainly related to the gate capacitance (Cono) between the Control Gate (CG) and Floating Gate (FG) interface, and the larger the gate capacitance between the Control Gate (CG) and Floating Gate (FG) interface is, the better the performance of the memory cell is.

The present invention provides a method for manufacturing a semiconductor device to improve the performance of a flash memory, as shown in fig. 2, the method includes:

step 201: providing a semiconductor substrate, and forming a floating gate on the semiconductor substrate;

step 202: a control gate is formed over the floating gate,

wherein the floating gate includes a body portion located above the semiconductor substrate and protruding portions located at both ends of the body portion and protruding toward the control gate.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Example one

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3G. It is understood that, for the flash memory, not only the memory (cell) but also the peripheral region is included, but the manufacturing method of the semiconductor device of the present embodiment mainly aims at the storage region of the flash memory, so that only the cross-sectional schematic view of the flash memory storage region is shown in fig. 3A to 3G, where fig. 3A to 3G are cross-sectional views of the flash memory storage cell along the length direction of the floating gate, and the so-called floating gate length direction refers to the direction perpendicular to the connecting line of the source and the drain or the word line direction.

First, a semiconductor substrate 300 is provided, a gate dielectric layer 301 and a floating gate material layer 302 on the gate dielectric layer 301 are formed on the semiconductor substrate, and the formed structure is as shown in fig. 3A.

Wherein the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.

The gate dielectric layer 301 may be formed of a conventional dielectric material such as an oxide, nitride or oxynitride. Illustratively, in the present embodiment, the gate dielectric layer 301 is made of an oxide, which can be formed by a thermal oxidation method, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.

The floating gate material layer 302 is illustratively a polysilicon material, which may be formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).

Next, a hard mask layer 303 is formed over the floating gate material layer 302, and the structure is as shown in fig. 3B.

The hard mask layer 303 may also be formed using a common hard mask material such as oxide, nitride, or the like by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like, which are commonly used in the art. Illustratively, in the present embodiment, the hard mask layer 303 is made of a nitride, such as silicon nitride (Si)₃N) formed by an atomic layer deposition method.

Next, the hard mask layer 303, the floating gate material layer 302, the gate dielectric layer 301 and the semiconductor substrate 300 are etched to form a trench and an active region separated by the trench in the semiconductor substrate 300, a main body portion 302A of the floating gate is formed on the gate dielectric layer 301 of the active region, and the trench is filled to form an isolation structure 304, and the formed structure is as shown in fig. 3C.

In this step, active area etching is performed, specifically, a patterned photoresist layer is formed on the hard mask layer 303, and the patterned photoresist layer defines a pattern of the active area; then, sequentially etching the hard mask layer 303, the floating gate material layer 302, the gate dielectric layer 301 and the semiconductor substrate 300 by using the patterned photoresist layer as a mask, thereby forming a trench and an active region separated by the trench in the semiconductor substrate 300, and simultaneously forming a main body portion 302A of the floating gate on the gate dielectric layer 301 of the active region; finally, the trench is filled with an isolation material to form an isolation structure 304, wherein the height of the isolation structure 304 is consistent with that of the hard mask layer 303.

Illustratively, the isolation structure 304 uses an oxide, such as silicon oxide, as an isolation material, and is filled by, for example, first forming a liner layer on the surface of the trench, then filling the trench by a CVD method to form the isolation structure 304, and finally performing a planarization process, such as a CMP (chemical mechanical polishing) process, so that the height of the isolation structure 304 is consistent with the height of the hard mask layer 303.

Next, a portion of the isolation structure 304 is removed, so that the height of the isolation structure 304 is higher than the surface of the semiconductor substrate 300 and lower than the body portion 302A of the floating gate, and the structure is as shown in fig. 3D.

Illustratively, a recess etching process is performed to remove a portion of the isolation structure 304, so that the height of the isolation structure 304 is higher than the surface of the semiconductor substrate 300 and lower than the body portion 302A of the floating gate. The recess etch process illustratively employs a dry etch process. The dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. As an example, in this embodiment, the etching is dry etching, and the process parameters of the dry etching include: the etching gas comprises CF4, CHF3, etc., with a flow rate of 50 sccm-500 sccm, 10 sccm-100 sccm, and a pressure of 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents mTorr.

Next, projections 305 projecting toward the control gate are formed at both ends of the floating gate main body portion 302A, and the structure is as shown in fig. 3E.

Exemplarily, in the present embodiment, the protrusion 305 is formed by the following steps: epitaxial growth is performed on both ends of the floating gate main body portion 302A in the longitudinal direction by an epitaxial process (i.e., a selective epitaxial process) using the hard mask layer 303 as a mask, so that protruding portions 305 protruding toward the control gate are formed on both ends of the floating gate main body portion 302A in the longitudinal direction. Due to the restriction of the hard mask layer 303 and the isolation structure 304A, protruding portions 305 are formed at both ends in the length direction of the floating gate main body portion 302A, and protrude upward, i.e., toward the control gate.

In the present embodiment, the floating gate body portion 302A and the protruding portion 305 together constitute the floating gate 306, and the surface area of the upper surface of the floating gate 306 is increased because the floating gate upper surface forms an upward protruding portion.

In addition, the protrusion 305 is formed on the isolation structure 304A, and the size in the active region direction (i.e., width direction) is not increased, so that the area of the memory cell on the active region is not increased. That is, on the premise that the active regions have the same memory cell area, the surface area of the upper surface of the floating gate can be increased, so that the gate capacitance between the floating gate and the control gate is increased.

The hard mask layer 303 is then removed, resulting in the structure shown in FIG. 3F.

Specifically, the hard mask layer 303 may be removed by a suitable dry etch or wet etch. Illustratively, since the hard mask layer 303 is formed of silicon nitride in this embodiment, the remaining hard mask layer 303 may be removed by wet etching with phosphoric acid. Of course, if other materials are used for the hard mask layer 303, they may be removed by other suitable methods.

Finally, step 307 is performed to form an isolation layer 307 and a control gate (not shown) on the isolation layer 307 on the floating gate 306, and the resulting structure is shown in fig. 3G.

The isolation layer 307 may be an ONO (oxide-nitride-oxide) structure, thereby having both good interface performance and a high dielectric constant. In this embodiment, the surface area of the upper surface of the floating gate 306 is increased, so that the contact area of the interface between the floating gate 306 and the control gate is increased, and the gate capacitance between the control gate and the floating gate 306 is increased, thereby improving the power consumption of the device and reducing the leakage current.

The control gate is formed by deposition and etching processes commonly used in the art, and will not be described herein.

Now that the process steps performed by the method according to the embodiment of the present invention are completed, it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps, such as ion doping, before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

It is understood that the method for manufacturing a semiconductor device according to the present embodiment can be used to manufacture not only a flash memory device, but also other devices having a stacked gate structure, which are similarly suitable for the method.

According to the manufacturing method of the semiconductor device of the embodiment, the protruding parts protruding towards the control gate are formed at the two ends of the floating gate main body part, so that the contact area of the floating gate and the control gate interface is increased, the gate capacitance of the interface between the control gate and the floating gate is increased, the power consumption of the device is further improved, and the leakage current is reduced.

Example two

The present invention also provides a semiconductor device, as shown in fig. 4, including: the semiconductor device comprises a semiconductor substrate 400, wherein an isolation structure 401 and an active region separated by the isolation structure are formed in the semiconductor substrate 400, and a gate dielectric layer 402 and a floating gate 403 positioned above the gate dielectric layer 402 are formed on the active region; an isolation layer 404 and a control gate located above the isolation layer 404 are formed on the floating gate 403, wherein the floating gate 403 includes a body 4030 located above the gate dielectric layer 402 and a protrusion 4031 located at two ends of the body 4030 and protruding toward the control gate.

Among them, the semiconductor substrate 400 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, the semiconductor substrate 400 is P-type doped monocrystalline silicon.

The isolation structure 401 may employ a commonly used isolation structure such as STI (shallow trench isolation). The height of the isolation structure 401 is higher than the surface of the semiconductor substrate 400 and lower than the body 4030 of the floating gate.

The gate dielectric layer 402 is made of oxide, nitride or oxynitride, and in this embodiment, the gate dielectric layer 402 is made of oxide, for example.

The floating gate 403 is made of a commonly used gate material such as polysilicon, for example, P-type doped polysilicon. The protruding portions 4031 are located at both ends of the floating gate 403 in the longitudinal direction.

The gate dielectric layer 404 is preferably an ONO structure, i.e., oxide, nitride, oxide, which has both good interface properties and a high dielectric constant.

The control gate is made of a commonly used gate material such as polysilicon, for example, N-type doped polysilicon.

According to the semiconductor device of the embodiment, the protruding portions protruding toward the control gate are formed at both ends of the floating gate main body portion, so that the contact area at the interface between the control gate and the floating gate interface is increased, the gate capacitance between the control gate and the floating gate interface is increased, the power consumption of the device is improved, and the leakage current is reduced.

EXAMPLE III

Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: a semiconductor substrate on which a floating gate is formed; a control gate is formed on the floating gate, wherein the floating gate includes a body portion located above the semiconductor substrate and protruding portions located at both ends of the body portion and protruding toward the control gate.

Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, may also be formed in the semiconductor substrate. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.

The electronic component may be any electronic component such as a discrete device and an integrated circuit.

The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.

Fig. 5 shows an example of a mobile phone. The exterior of the cellular phone 500 is provided with a display portion 502, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like, which are included in a housing 501.

According to the electronic device provided by the embodiment of the invention, as the gate capacitance between the control gate and the floating gate interface is increased by the contained semiconductor device, the power consumption of the device is improved, and the leakage current is reduced. The electronic device also has similar advantages.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a floating gate on the semiconductor substrate;

a control gate is formed over the floating gate,

wherein the floating gate includes a body portion located above the semiconductor substrate and protruding portions located at both ends of the body portion and protruding toward the control gate; wherein the step of forming a floating gate on the semiconductor substrate comprises:

forming a grid dielectric layer on the semiconductor substrate;

forming a floating gate material layer and a hard mask layer on the semiconductor substrate in sequence;

etching the hard mask layer, the floating gate material layer, the gate dielectric layer and the semiconductor substrate to form a groove and an active region separated by the groove in the semiconductor substrate, and forming a main body part of the floating gate on the gate dielectric layer on the active region;

filling the groove to form an isolation structure, wherein the height of the isolation structure is higher than the surface of the semiconductor substrate and lower than the body part of the floating gate;

forming the protruding parts at two ends of the main body part of the floating gate by using the hard mask layer as a mask through an epitaxial process;

and removing the hard mask layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the protruding portions are located at both ends in a longitudinal direction of the floating gate.

3. The method of claim 1, wherein the hard mask layer is a nitride.

4. A semiconductor device fabricated using the method of claim 1, comprising:

the semiconductor device comprises a semiconductor substrate, wherein a floating gate and an isolation structure are formed on the semiconductor substrate;

a control gate is formed over the floating gate,

the floating gate comprises a main body part and protruding parts, wherein the main body part is located on the semiconductor substrate, the protruding parts are located at two ends of the main body part and protrude towards the control gate, the protruding parts are located at two ends of the floating gate in the length direction, the height of the isolation structure is higher than the surface of the semiconductor substrate and lower than the main body part of the floating gate, and two ends of the main body part are at least partially formed on the isolation structure.

5. The semiconductor device according to claim 4, further comprising:

6. An electronic device comprising a semiconductor device according to any one of claims 4 to 5 and an electronic component connected to the semiconductor device.