CN108336086A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN108336086A CN108336086A CN201710035429.8A CN201710035429A CN108336086A CN 108336086 A CN108336086 A CN 108336086A CN 201710035429 A CN201710035429 A CN 201710035429A CN 108336086 A CN108336086 A CN 108336086A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
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- 238000002955 isolation Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 9
- 239000011469 building brick Substances 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 description 12
- 238000003860 storage Methods 0.000 description 9
- 150000004767 nitrides Chemical group 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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- 229910000673 Indium arsenide Inorganic materials 0.000 description 3
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- 238000001312 dry etching Methods 0.000 description 3
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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Abstract
A kind of semiconductor devices of present invention offer and preparation method thereof, electronic device, the production method include：Semiconductor substrate is provided, forms floating boom on the semiconductor substrate；Control gate is formed on the floating gate, wherein the floating boom includes being located at main part on the semiconductor substrate and positioned at the main part both ends and towards control gate protruding portion outstanding.The production method can increase the grid capacitance between control gate and floating boom interface, improve device power consumption, and reduce leakage current.The semiconductor devices has the advantages that similar with electronic device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device
Device (flash memory).Flash memory has can be repeatedly into actions such as the deposit of row information, reading and erasings, and are stored in
The characteristic that information will not disappear after a loss of power, therefore, flash memory has become PC and electronic equipment is adopted extensively
A kind of nonvolatile memory.
With the diminution of device, the power consumption of flash memory becomes increasingly worse, therefore has used ultra-shallow junctions and dashed forward
Become the short-channel effect for fetching and improving core device.However, even if meeting grid material demand, the balance of power consumption and Capacity control is
Through increasingly becoming a big challenge.In order to overcome the problem, more effort, pre-amorphous total injection, stress
Engineering has been used for the doping section for optimizing floating boom, to improve device power consumption and Capacity control.But these effort are still not
It can drip and solve the above problems very well.
Therefore, it is necessary to a kind of semiconductor devices and preparation method thereof be proposed, to solve the above problems.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of production method of semiconductor devices, can increase control gate
Grid capacitance between floating boom interface improves device power consumption, and reduces leakage current.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of production method of semiconductor devices, the system
Include as method：Semiconductor substrate is provided, forms floating boom on the semiconductor substrate；Control gate is formed on the floating gate,
Wherein, the floating boom includes being located at main part on the semiconductor substrate and positioned at the main part both ends and towards described
Control gate protruding portion outstanding.
Further, the protruding parts are in the both ends in the floating gate length direction.
Further, further include：
Gate dielectric layer is formed on the semiconductor substrate；
The active area for forming isolation structure in the semiconductor substrate and being divided by the isolation structure, the floating boom shape
At on the gate dielectric layer of the active area.
Further, the isolation structure is formed in the semiconductor substrate and is separated by the isolation structure active
The step of area includes：Floating gate material layer and hard mask layer are sequentially formed on the semiconductor substrate；To the hard mask layer, institute
It states floating gate material layer, the gate dielectric layer and the semiconductor substrate to perform etching, to be formed in the semiconductor substrate
Groove and by the active area of the trench separation, formed on the active area be located at it is described floating on the gate dielectric layer
The main part of grid；It fills the groove and forms the isolation structure, the height of the isolation structure is higher than the semiconductor substrate
Surface, and less than the floating boom main part；The protruding portion is formed at the both ends of the main part of the floating boom；Described in removal
Hard mask layer.
Further, it is formed at the both ends of the main part of the floating boom by epitaxy technique using the hard mask layer as mask
The protruding portion.
Further, the hard mask layer is nitride.
The production method of semiconductor device according to the invention, by being formed towards control gate at the both ends of floating boom main part
Protruding portion outstanding increases the contact area of floating boom and control gate interface, to increase the boundary of control gate and floating boom
Grid capacitance at face, and then device power consumption is improved, and reduce leakage current.
Another aspect of the present invention provides a kind of semiconductor devices, which includes：Semiconductor substrate, described half
It is formed with floating boom on conductor substrate；It is formed with control gate on the floating gate, wherein the floating boom includes being located at the semiconductor
The main part of substrate and positioned at the main part both ends and towards control gate protruding portion outstanding.
Further, the protruding parts are in the both ends in the floating gate length direction.
Further, the height of the isolation structure is higher than the surface of the semiconductor substrate, and less than the floating boom
Main part.
Further, which further includes：
Isolation structure in the semiconductor substrate and the active area divided by the isolation structure；
Be formed with gate dielectric layer on the active area, the floating boom be formed in the active area gate dielectric layer it
On.
Further, the both ends of the main part are at least partially formed on the isolation structure.
Semiconductor devices proposed by the present invention increases the grid capacitance between control gate and floating boom interface, improves device
Power consumption, and reduce leakage current.
Further aspect of the present invention provides a kind of electronic device comprising a kind of semiconductor devices and with the semiconductor device
The electronic building brick that part is connected, the semiconductor devices include：
Electronic device proposed by the present invention due to above-mentioned semiconductor device, thus has the advantages that similar.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the structural schematic diagram and its equivalent capacity diagram of fast storage storage unit；
Fig. 2 shows the step flow charts of the production method of semiconductor devices according to an embodiment of the present invention；
The production method that Fig. 3 A~Fig. 3 G show semiconductor devices according to an embodiment of the present invention is implemented respectively successively
The diagrammatic cross-section of the obtained semiconductor devices of step；
Fig. 4 shows the structural schematic diagram of semiconductor devices according to an embodiment of the present invention；
Fig. 5 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with reference numeral.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device in attached drawing is overturn, then, it is described as " below other elements "
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
Referring to FIG. 1, it illustrates the structural schematic diagrams of fast storage storage unit and equivalent capacity to illustrate, wherein
Grid capacitance (Cono) of the performance of fast storage mainly between control gate (CG) and the interface floating boom (FG) is related, control gate
(CG) grid capacitance between the interface floating boom (FG) is bigger, and the performance of storage unit is better.
A kind of production method of semiconductor devices is proposed the present invention is based on this, the performance for improving flash memory, such as
Shown in Fig. 2, which includes：
Step 201：Semiconductor substrate is provided, forms floating boom on the semiconductor substrate；
Step 202：Control gate is formed on the floating gate,
Wherein, the floating boom include be located at main part on the semiconductor substrate and positioned at the main part both ends and
Towards control gate protruding portion outstanding.
The production method of semiconductor device according to the invention, by being formed towards control gate at the both ends of floating boom main part
Protruding portion outstanding increases the contact area of floating boom and control gate interface, to increase the boundary of control gate and floating boom
Grid capacitance at face, and then device power consumption is improved, and reduce leakage current.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
The production method of the semiconductor devices of an embodiment of the present invention is done below with reference to Fig. 3 A~Fig. 3 G and is retouched in detail
It states.It is understood that for flash memory, includes not only memory (cell), further include external zones, and the present embodiment
The memory block mainly for flash memory of the production method of semiconductor devices, thus quick flashing is only shown in Fig. 3 A~Fig. 3 G
The diagrammatic cross-section of memory storage area, wherein Fig. 3 A~Fig. 3 G are flash memory cell cuing open along floating gate length direction
Face figure, so-called floating gate length direction refer to the direction vertical with source electrode and drain electrode line or word-line direction.
First, semiconductor substrate 300 is provided, forms gate dielectric layer 301 on the semiconductor substrate and positioned at described
Floating gate material layer 302 on gate dielectric layer 301, it is as shown in Figure 3A to be formed by structure.
Wherein, semiconductor lining 300 can be following at least one of the material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or for silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, semiconductor substrate 300
Constituent material select monocrystalline silicon.
Common dielectric material, such as oxide, nitride or nitrogen oxides may be used in gate dielectric layer 301.Example
Property, in the present embodiment, gate dielectric layer 301 uses oxide, can (physical vapor is heavy by thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), the methods of ALD (atomic layer deposition) formed.
Floating gate material layer 302 illustratively uses polycrystalline silicon material, can be by that can select molecular beam epitaxy
(MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) with
And a kind of formation in selective epitaxy growth (SEG).
Then, hard mask layer 303 is formed on the floating gate material layer 302, and it is as shown in Figure 3B to be formed by structure.
Hard mask layer 303 can also use the common hard mask materials such as oxide, nitride, and normal by this field
The methods of PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer deposition) formation.Illustratively, exist
Hard mask layer 303 uses nitride, such as silicon nitride (Si in the present embodiment3N), formed by Atomic layer deposition method.
Then, to the hard mask layer 303, floating gate material layer 302, gate dielectric layer 301 and semiconductor substrate 300 into
Row etching, with the formation groove in the semiconductor substrate 300 and by the active area of the trench separation, in the active area
The main part 302A of floating boom is formed on gate dielectric layer 301, and fills the groove and forms isolation structure 304, is formed by knot
Structure is as shown in Figure 3 C.
Active area etching is carried out in this step, specifically forms patterned photoresist on hard mask layer 303 first
Layer, the patterned photoresist layer define the pattern of active area；Then, it is carved successively as mask using the patterned photoresist layer
The hard mask layer 303, floating gate material layer 302, gate dielectric layer 301 and semiconductor substrate 300 are lost, to partly be led described
Groove and by the active area of the trench separation is formed in body substrate 300, while on the gate dielectric layer of the active area 301
Form the main part 302A of floating boom；The groove is finally filled with isolated material and forms isolation structure 304, the isolation structure
304 height is highly consistent with the hard mask layer 303.
Illustratively, the isolation structure 304 uses oxide, such as silica is as isolated material, filling process
Laying for example, is formed in the flute surfaces first, then filling the groove by CVD method forms isolation structure
304, flatening process, such as CMP (chemically mechanical polishing) technique are finally executed, height and the institute of the isolation structure 304 are made
State the highly consistent of hard mask layer 303.
Then, the part isolation structure 304 is removed, so that the height of isolation structure 304 is higher than the semiconductor substrate
300 surface, and less than the main part 302A of the floating boom, it is as shown in Figure 3D to be formed by structure.
Illustratively, by executing recess (recess) etching technics, the part isolation structure 304 is removed, so that every
Height from structure 304 is higher than the surface of the semiconductor substrate 300, and less than the main part 302A of the floating boom.It is described recessed
(recess) etching technics is fallen into illustratively, using dry etch process.The dry method etch technology includes but not limited to：Reaction
Ion(ic) etching (RIE), ion beam milling, plasma etching or laser cutting.And as an example, in the present embodiment, institute
It states and is etched to dry etching, the technological parameter of the dry etching includes：Etching gas includes the gases such as CF4, CHF3, flow
Respectively 50sccm~500sccm, 10sccm~100sccm, pressure are 2mTorr~50mTorr, wherein sccm representatives cube
Cm per minute, mTorr represent millitorr.
Then, it is formed towards control gate protruding portion 305 outstanding, is formed by the both ends of the floating boom main part 302A
Structure is as shown in FIGURE 3 E.
Illustratively, in the present embodiment, protruding portion 305 is formed by following step：It is to cover with the hard mask layer 303
The both ends progress that film is located at length direction by epitaxy technique (i.e. selective epitaxial process) in the floating boom main part 302A is outer
Epitaxial growth, the both ends to be located at length direction in the floating boom main part 302A are formed towards control gate protruding portion outstanding
305.Due to the limitation of hard mask layer 303 and isolation structure 304A, protruding portion 305 is formed in floating boom main part 302A length directions
Both ends, and project upwards, i.e., protruded towards control gate.
In the present embodiment, floating boom main part 302A and protruding portion 305 collectively form floating boom 306, due to floating boom upper surface
Upward protruding portion is formd, so that the surface area of 306 upper surface of floating boom increases.
In addition, 305 part of protruding portion is formed on isolation structure 304A, in active area direction (i.e. width direction)
Size does not increase, because without increasing the area of storage unit on the active area.That is, having identical storage single on the active area
Under the premise of elemental area, the surface area that floating boom upper surface may be implemented increases, to increase the grid between floating boom and control gate
Capacitance.
Then, hard mask layer 303 is removed, is formed by structure as illustrated in Figure 3 F.
Specifically, hard mask layer 303 can be removed by suitable dry etching or wet etching.Illustratively, due to
In this implementation hard mask layer 303 using the nitride of silicon, thus remaining hard mask layer can be removed by phosphoric acid wet etching
303.Certainly, it if hard mask layer 303 uses other materials, can be removed by other suitable methods.
Finally, step 307 is executed, forms separation layer 307 on the floating boom 306 and on the separation layer 307
Control gate (not shown), be formed by structure as shown in Figure 3 G.
ONO (oxidenitride oxide) structure may be used in separation layer 307, good interface characteristics to both have
Can, and there is higher dielectric constant.In the present embodiment, since the surface area of 306 upper surface of floating boom increases, thus floating boom
306 and the contact area at interface of control gate increase, grid capacitance between such control gate and floating boom 306 increases, to change
It has been apt to device power consumption, has reduced leakage current.
Control gate is formed using deposition commonly used in the art, etching technics, and details are not described herein.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device includes not only above-mentioned steps, before above-mentioned steps, among or may also include other needs later
The step of, such as ion doping, it is included in the range of this implementation production method.
It is understood that the manufacturing method for the semiconductor devices that the present embodiment proposes, can be not only used for flash memory processed
Memory device, and can be used for manufacturing other devices with stacking grid structure for applying analogously for this method.
According to the production method of the semiconductor devices of the present embodiment, by being formed towards control at the both ends of floating boom main part
Grid protruding portion outstanding, increases the contact area of floating boom and control gate interface, to increase between control gate and floating boom
The grid capacitance of interface, and then device power consumption is improved, and reduce leakage current
Embodiment two
The present invention also provides a kind of semiconductor devices, as shown in figure 4, the semiconductor devices includes：Semiconductor substrate 400,
It is formed with isolation structure 401 in the semiconductor substrate 400 and active area is separated to obtain by the isolation structure, described active
Gate dielectric layer 402 and the floating boom 403 on the gate dielectric layer 402 are formed in area；The shape on the floating boom 403
At having separation layer 404 and the control gate on the separation layer 404, wherein the floating boom 403 includes being located at the grid
Main part 4030 on dielectric layer 402 and positioned at 4030 both ends of the main part and towards control gate protruding portion outstanding
4031。
Wherein, semiconductor substrate 400 can be following at least one of the material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or for silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, semiconductor substrate 400 is the list of p-type doping
Crystal silicon.
Common isolation structure, such as STI (fleet plough groove isolation structure) may be used in isolation structure 401.The isolation junction
The height of structure 401 is higher than the surface of the semiconductor substrate 400, and less than the main part 4030 of the floating boom.
Gate dielectric layer 402 is using oxide, nitride or nitrogen oxides, and illustratively, in the present embodiment, grid is situated between
Matter layer 402 uses oxide.
Floating boom 403 uses common grid material, such as polysilicon, as an example, for example, p-type DOPOS doped polycrystalline silicon.Institute
State the both ends that protruding portion 4031 is located at 403 length direction of the floating boom.
Gate dielectric layer 404 is then preferably by ONO structure, that is, oxide, nitride, oxide structure both have in this way
There is good interface performance, it may have higher dielectric constant.
Control gate uses common grid material, such as polysilicon, as an example, for example, n-type doping polysilicon.
It is outstanding prominent towards control gate by being formed at the both ends of floating boom main part according to the semiconductor devices of the present embodiment
Go out portion, increase the contact area of interface between control gate and floating boom interface, to increase control gate and floating boom interface it
Between grid capacitance, improve device power consumption, and reduce leakage current.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, which includes：Semiconductor substrate is formed with floating on the semiconductor substrate
Grid；Be formed with control gate on the floating gate, wherein the floating boom include be located at the semiconductor substrate on main part and
Positioned at the main part both ends and towards control gate protruding portion outstanding.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or for silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode can also be the metal interconnection structure, etc. being electrically connected with transistor.In addition, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure is as example.In the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products for including the semiconductor devices.
Wherein, Fig. 5 shows the example of mobile phone.The outside of mobile phone 500 is provided with the display portion being included in shell 501
502, operation button 503, external connection port 504, loud speaker 505, microphone 506 etc..
The electronic device of the embodiment of the present invention, by the semiconductor devices for being included increase control gate and floating boom interface it
Between grid capacitance, improve device power consumption, and reduce leakage current.Therefore the electronic device equally has the advantages that similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of production method of semiconductor devices, which is characterized in that including：
Semiconductor substrate is provided；
Floating boom is formed on the semiconductor substrate；
Control gate is formed on the floating gate,
Wherein, the floating boom include be located at the semiconductor substrate on main part and be located at the main part both ends and direction
The control gate protruding portion outstanding.
2. the production method of semiconductor devices according to claim 1, which is characterized in that the protruding parts are in described floating
The both ends in gate length direction.
3. the production method of semiconductor devices according to claim 1, which is characterized in that further include：
Gate dielectric layer is formed on the semiconductor substrate；
The active area for forming isolation structure in the semiconductor substrate and being divided by the isolation structure, the floating boom are formed in
On the gate dielectric layer of the active area.
4. the production method of semiconductor devices according to claim 3, which is characterized in that shape in the semiconductor substrate
Include at the isolation structure and by the step of active area that the isolation structure separates：
Floating gate material layer and hard mask layer are sequentially formed on the semiconductor substrate；
The hard mask layer, the floating gate material layer, the gate dielectric layer and the semiconductor substrate are performed etching, with
Groove is formed in the semiconductor substrate and by the active area of the trench separation, is formed on the active area and is located at the grid
The main part of the floating boom on the dielectric layer of pole；
It fills the groove and forms the isolation structure, the height of the isolation structure is higher than the surface of the semiconductor substrate,
And less than the main part of the floating boom；
The protruding portion is formed at the both ends of the main part of the floating boom；
Remove the hard mask layer.
5. the production method of semiconductor devices according to claim 4, which is characterized in that using the hard mask layer as mask
By epitaxy technique the protruding portion is formed at the both ends of the main part of the floating boom.
6. the production method of semiconductor devices according to claim 3, which is characterized in that the hard mask layer is nitridation
Object.
7. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate is formed with floating boom on the semiconductor substrate；
It is formed with control gate on the floating gate,
Wherein, the floating boom include be located at the semiconductor substrate on main part and be located at the main part both ends and direction
The control gate protruding portion outstanding.
8. semiconductor devices according to claim 7, which is characterized in that the protruding parts are in the floating gate length direction
Both ends.
9. semiconductor devices according to claim 7, which is characterized in that the height of the isolation structure is partly led higher than described
The surface of body substrate, and less than the main part of the floating boom.
10. semiconductor devices according to claim 7, which is characterized in that further include：
Isolation structure in the semiconductor substrate and the active area divided by the isolation structure；
Gate dielectric layer is formed on the active area, the floating boom is formed on the gate dielectric layer of the active area.
11. semiconductor devices according to claim 10, which is characterized in that the both ends of the main part are at least a partially formed
On the isolation structure.
12. a kind of electronic device, which is characterized in that include the semiconductor devices as described in any one in claim 7-11
And the electronic building brick being connected with the semiconductor devices.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202309A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Floating gate flash memory device |
| CN102881693A (en) * | 2012-10-25 | 2013-01-16 | 上海宏力半导体制造有限公司 | Storage device and manufacturing method thereof |
| CN105206614A (en) * | 2015-08-19 | 2015-12-30 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory structure and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202309A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Floating gate flash memory device |
| CN102881693A (en) * | 2012-10-25 | 2013-01-16 | 上海宏力半导体制造有限公司 | Storage device and manufacturing method thereof |
| CN105206614A (en) * | 2015-08-19 | 2015-12-30 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory structure and preparation method thereof |
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Effective date of registration: 20221024 Address after: 100176 No.18 Wenchang Avenue, Beijing Economic and Technological Development Zone, Daxing District, Beijing Patentee after: Zhongxin North Integrated Circuit Manufacturing (Beijing) Co.,Ltd. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Patentee after: Semiconductor Manufacturing International (Beijing) Corp. Address before: 201203 18 Zhangjiang Road, Shanghai, Pudong New Area Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Patentee before: Semiconductor Manufacturing International (Beijing) Corp. |