CN108649030A - Semiconductor devices and preparation method thereof, electronic device - Google Patents
Semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN108649030A CN108649030A CN201710160746.2A CN201710160746A CN108649030A CN 108649030 A CN108649030 A CN 108649030A CN 201710160746 A CN201710160746 A CN 201710160746A CN 108649030 A CN108649030 A CN 108649030A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 176
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000011229 interlayer Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 32
- 239000004020 conductor Substances 0.000 claims description 10
- 150000004767 nitrides Chemical group 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000006396 nitration reaction Methods 0.000 claims description 6
- 239000011469 building brick Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 claims 1
- 150000002830 nitrogen compounds Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000002955 isolation Methods 0.000 description 20
- 239000011435 rock Substances 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 6
- 230000015654 memory Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- -1 titanium nitrides Chemical class 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
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- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PQZSQOYXZGDGQW-UHFFFAOYSA-N [W].[Pb] Chemical compound [W].[Pb] PQZSQOYXZGDGQW-UHFFFAOYSA-N 0.000 description 1
- 239000012861 aquazol Substances 0.000 description 1
- 229920006187 aquazol Polymers 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
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- 239000007924 injection Substances 0.000 description 1
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- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor devices of present invention offer and preparation method thereof, electronic device, the production method include：Semiconductor substrate is provided, stacking gate is formed on the semiconductor substrate, clearance wall is formed on the side wall of the stacking gate；The interlayer dielectric layer for surrounding the stacking gate is formed on the semiconductor substrate；Source contact and drain contact are formed in the interlayer dielectric layer；Wherein, the clearance wall top area is all by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.The production method can overcome the problems, such as that the reversion contact etching stop layer grid being eliminated result at the top of grid gap wall and the breakdown voltage between source/drain reduce.The semiconductor devices has the advantages that similar with electronic device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the prevalence of portable personal device, the demand to memory further increases, and is ground to memory technology
Studying carefully becomes the important directions of information technology research, in order to preferably improve the reliability of storage density and data storage, research and development
Emphasis is gradually concentrated mainly on non-volatility memorizer (NVM, non-volatile memory).NOR (patrol by nondisjunction type electronics
Volume door) type flash memory can be read or stylized in a manner of random-access, and since its is non-volatile
(non-volatility), durability (durability) and quickly the access time and widely made in the mobile device
With.
Autoregistration inverts the NOR devices that contact technique is suitable for 45nm, in autoregistration inverts contact for producing, is used as autoregistration
The silicon nitride layer of reversion contact stop-layer is located at the part on grid gap wall oxide can quilt in interlayer dielectric layer flatening
Grinding removal is crossed, this leads in grid gap wall the liner oxidation of (clearance wall is generally oxidenitride oxide structure)
Under object is also exposed to hydrofluoric acid during forming reversion contact by wet processing so that the liner oxidation at the top of clearance wall
Object is removed, and as shown in dashed region in Fig. 1, this can make the breakdown voltage between grid and source/drain be lower, or even work as tungsten
Lead to leakage current later with filling gaps (gap formed after pad oxide removal and reversion contact hole) such as titanium/titanium nitrides.
It is, therefore, desirable to provide a kind of production method of new semiconductor devices, to solve the above problems.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of production method of semiconductor devices, can overcome between grid
The problem of reversion contact etching stop layer grid being eliminated result at the top of gap wall and the breakdown voltage between source/drain reduce.
One aspect of the present invention provides a kind of production method of semiconductor devices comprising：
Semiconductor substrate is provided, stacking gate is formed on the semiconductor substrate, is formed on the side wall of the stacking gate
Clearance wall；
The interlayer dielectric layer for surrounding the stacking gate is formed on the semiconductor substrate；
Source contact and drain contact are formed in the interlayer dielectric layer；
Wherein, the clearance wall top area is all by having the material structure of Etch selectivity with the interlayer dielectric layer
At.
Preferably, the clearance wall that formed on the side wall of the stacking gate includes：
Primary clearance wall is formed on the side wall of the stacking gate, the primary clearance wall includes at least layer of oxide layer；
Remove the part that the oxide layer in the primary clearance wall is located at the clearance wall top area；
There is the top area that the material of Etch selectivity fills the clearance wall with the interlayer dielectric layer, so that institute
Clearance wall top area is stated all by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.
Preferably, the oxide layer in the removal primary clearance wall is located at the part packet of the clearance wall top area
It includes：
The filled layer for surrounding and covering the stacking gate is formed in the semiconductor substrate；
The part filled layer is removed to expose the top area of the stacking gate and primary clearance wall；
The part that the oxide layer in the primary clearance wall is located at the clearance wall top area is removed using wet processing；
Remove the remaining filled layer.
Preferably, the primary clearance wall includes the first oxide layer stacked gradually, nitration case and the second oxide layer.
Preferably, the filled layer is organic filled layer.
Preferably, it is nitride to have the material of Etch selectivity with the interlayer dielectric layer.
Preferably, further include forming the reversion covered at the top of the semiconductor substrate surface, clearance wall and the stacking gate
Contact etching stop layer.
Preferably, described that there is the top that the material of Etch selectivity fills the clearance wall with the interlayer dielectric layer
The step of the step of region inverts contact etching stop layer with the formation is completed in same step.
Preferably, the reversion contact etching stop layer is formed by furnace process.
The production method of semiconductor devices proposed by the present invention, by keeping the material of clearance wall top area all and layer
Between dielectric layer have Etch selectivity material so that subsequently through reversion contact etching technique formed source and drain contact hole when will not
Gap is formed at the top of clearance wall, so as to avoid formed source and drain contact when conductive material be also filled into clearance wall top area
In and cause the breakdown voltage between grid and source/drain to reduce, improve the performance and yield of device.
Another aspect of the present invention provides a kind of semiconductor devices made using the above method, which includes：
Semiconductor substrate is formed with stacking gate on the semiconductor substrate, is formed on the side wall of the stacking gate
Clearance wall；
It is formed with the interlayer dielectric layer for surrounding the stacking gate on the semiconductor substrate；
Source contact and drain contact are formed in the interlayer dielectric layer；
Wherein, the clearance wall top area is all by having the material structure of Etch selectivity with the interlayer dielectric layer
At.
Preferably, the top area of the clearance wall is all made of nitride..
Semiconductor devices proposed by the present invention can reduce to avoid the breakdown voltage between grid and source/drain, thus property
It can be improved with yield.
Further aspect of the present invention provides a kind of electronic device comprising semiconductor devices as described above and with described half
The electronic building brick that conductor device is connected.
Electronic device proposed by the present invention due to above-mentioned semiconductor device, thus has the advantages that similar.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows that a kind of schematic SEM for the NOR devices that clearance wall is formed with gap at present is illustrated；
Fig. 2 shows the step flow charts of the production method of semiconductor devices according to an embodiment of the present invention
The production method that Fig. 3 A~Figure 17 A show semiconductor devices according to an embodiment of the present invention is implemented respectively successively
The sectional view along active area direction of the obtained semiconductor devices of step；
The production method that Fig. 3 B~Figure 17 B show semiconductor devices according to an embodiment of the present invention is implemented respectively successively
Sectional view of the obtained semiconductor devices of step along isolation structure direction；
Figure 18 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with reference numeral.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device in attached drawing is overturn, then, it is described as " below other elements "
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
As previously mentioned, portion gap wall oxide is eliminated result in grid when NOR devices carry out reversion contact for producing at present
It is reduced with source/drain breakdown voltage, the present invention is directed to such case, proposes a kind of production method of semiconductor devices, overcomes this
Kind problem.
As shown in Fig. 2, the production method includes：Step 200, semiconductor substrate is provided, on the semiconductor substrate shape
At stacking gate, clearance wall is formed on the side wall of the stacking gate；Step 201, it is formed on the semiconductor substrate and surrounds institute
State the interlayer dielectric layer of stacking gate；Step 202, source contact and drain contact are formed in the interlayer dielectric layer；Wherein, institute
Clearance wall top area is stated all by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.
The production method of semiconductor devices proposed by the present invention, by keeping the material of clearance wall top area all and layer
Between dielectric layer have Etch selectivity material so that subsequently through reversion contact etching technique formed source and drain contact hole when will not
Gap is formed at the top of clearance wall, so as to avoid formed source and drain contact when conductive material be also filled into clearance wall top area
In and cause grid and breakdown voltage between source/drain to reduce, improve the performance and yield of device.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
Below with reference to Fig. 3 A to Figure 17 A and Fig. 3 B~Figure 17 B to the semiconductor devices of an embodiment of the present invention
Production method is described in detail, and wherein Fig. 3 A~Figure 17 A show the system of semiconductor devices according to an embodiment of the present invention
Make the sectional view along active area direction that method implements the obtained semiconductor devices of each step successively；Fig. 3 B~Figure 17 B are shown
The production method of semiconductor devices according to an embodiment of the present invention implement successively the obtained semiconductor devices of each step along every
Sectional view from structure direction.
In the present embodiment, it proposed by the present invention is partly led so that the source and drain for making NOR memories contacts as an example to illustrate
The production method of body device.Above-mentioned attached drawing is please referred to, the production method of the semiconductor devices of the present embodiment includes the following steps：
First, semiconductor substrate 300 is provided, forms stacking gate on the semiconductor substrate, in the side of the stacking gate
Primary clearance wall 307 is formed on wall, the primary clearance wall 307 includes at least layer of oxide layer, is formed by structure such as Fig. 3 A
Shown in Fig. 3 B.
Wherein, semiconductor substrate 300 can be following at least one of the material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or for silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device in semiconductor substrate 300, such as
NMOS and/or PMOS etc..Equally, conductive member can also be formed in semiconductor substrate 300, conductive member can be transistor
Grid, source electrode or drain electrode, can also be the metal interconnection structure, etc. being electrically connected with transistor.As an example, in this implementation
In example, the constituent material of semiconductor substrate 300 selects monocrystalline silicon.
Isolation structure 301 in semiconductor substrate 300 can be shallow trench isolation (STI) structure or selective oxidation silicon
(LOCOS) isolation structure can be formed by method commonly used in the art, to define and separate active area.As an example,
Isolation structure 301 uses shallow trench isolation (STI) structure.
Tunnel oxide 302 is illustratively silicon oxide layer, can (physical vapor is heavy by such as thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), the methods of ALD (atomic layer deposition) formed.
Stacking gate includes the floating boom 303 for stacking gradually setting, dielectric layer 304, control gate 305 and control gate hard mask layer
306, wherein floating boom 303 is close to semiconductor substrate 300, and 305 source and drain semiconductor substrate 300 of control gate.Illustratively, floating boom
303 and control gate 305 use the semi-conducting material such as polysilicon, and pass through select molecular beam epitaxy (MBE), Organometallic
Learn vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth
(SEG) a kind of formation in.Dielectric layer 304 is such as the dielectric materials such as oxide, nitride, it is preferable that in the present embodiment,
Dielectric layer 304 both has good interface performance in this way using ONO structure (that is, oxidenitride oxide), it may have
Good dielectric properties and suitable thickness.Various suitable mask materials, such as oxygen may be used in control gate hard mask layer 306
Compound, nitride, nitrogen oxides etc..Illustratively, in the present embodiment, control gate hard mask layer 306 uses nitride, example
Property be silicon nitride, such as PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer deposition) can be passed through
The methods of formed.
Primary clearance wall 307 is formed on the side wall of stacking gate, and includes at least side oxide layer.Illustratively,
Gap wall 307 includes the first oxide layer 3070, nitration case 3071 and the second oxide layer 3072.Oxide layer and nitration case may be used often
Oxide and nitride, such as silica, silicon nitride, silicon oxynitride etc..
Then, the filled layer 308 for surrounding and covering the stacking gate is formed in the semiconductor substrate 300, is formed
Structure it is as shown in Figure 4 A and 4 B shown in FIG..
Filled layer 308 is using the good material of various spreadabilities, and illustratively, in the present embodiment, filled layer 308, which uses, to be had
Machine filled layer (ODL).
It is understood that the thickness of filled layer 308 is more than the thickness of stacking gate namely filled layer 308 is higher than stacking gate
Surface.
Then, removal is partially filled with layer 308, to expose the top area of the stacking gate and clearance wall 307, is formed by
Structure is as fig. 5 a and fig. 5b.
Illustratively, recess (recess) etching is executed by suitable wet method or dry etch process, to remove part
Filled layer 308 makes the top of filled layer 308 be less than the surface of stacking gate, to expose the top of the stacking gate and clearance wall 307
Region.
Then, the portion that the oxide layer in the primary clearance wall 307 is located at 307 top area of primary clearance wall is removed
Point, it is as shown in Figure 6 A and 6 B to be formed by structure.
Illustratively, it by wet-etching technology, such as is performed etching by the hydrofluoric acid (HF) of suitable concentration, to go
Except the oxide layer in the primary clearance wall 307 is located at the part of 307 top area of primary clearance wall, while described first
The top area of beginning clearance wall 307 forms gap, as shown in dashed circle in Fig. 6 A and Fig. 6 B.
Then, remaining filled layer 308 is removed, is formed by structure as shown in figures 7 a and 7b.
Illustratively, remaining filled layer 308 is removed by suitable dry and wet technique, such as by suitable molten
Agent removes remaining filled layer 308.
Then, formed cover the semiconductor substrate 300, clearance wall and the stacking gate reversion contact etching stop layer
309, it is as shown in Figure 8 A and 8 B to be formed by structure.
Reversion contact etching stop layer 309 is used to connect as stop-layer, reversion when subsequently carrying out reversion contact hole etching
Touch etching stop layer 309 cover the semiconductor substrate 300 surface and the stacking gate side wall (also covering i.e. initially between
Gap wall 307) and top.It inverts contact etching stop layer 309 and uses common material, illustratively, in the present embodiment, reversion
Contact etching stop layer 309 uses silicon nitride, and the manufacture craft for using step coverage good is formed, so as to primary clearance wall
Gap in 307 top areas is refilled.Illustratively, in the present embodiment, reversion contact etching stop layer 309 passes through
Furnace process is formed.
In the present embodiment, also to 307 top region of primary clearance wall while forming reversion contact etching stop layer 309
The gap in domain is refilled, to make the top area of the clearance wall 307A newly formed be all made of silicon nitride, in this way between
The top of gap wall 307A is all by having material of Etch selectivity with the interlayer dielectric layer (generally oxide) being subsequently formed
It constitutes, therefore gap will not be formed in clearance wall top area in the follow-up reversion contact etching that carries out, will not correspondingly fill out again
It is charged into conductive material.
It is understood that although the gap of clearance wall top area is filled using silicon nitride in the present embodiment,
Make all silicon nitrides of clearance wall top area, but in other embodiments, other materials can also be used, as long as the material
There is Etch selectivity, the Etch selectivity herein to refer to the material with the interlayer dielectric layer being subsequently formed
It is less than 1 with the etching selection ratio for the interlayer dielectric layer being subsequently formed:50 so that be situated between subsequently through wet-etching technology removal interlayer
When electric layer, the material is unaffected, i.e., the material will not be removed by the wet-etching technology of subsequently removal interlayer dielectric layer.
Then, the interlayer dielectric layer 310 for covering and surrounding the stacking gate, institute are formed in the semiconductor substrate 300
The structure of formation is as shown in fig. 9 a and fig. 9b.
Interlayer dielectric layer 310 is formed in the gap between stacking gate, for each stacking gate to be isolated.Interlayer dielectric layer
310 may be used various suitable materials, such as USG (undoped silicon glass), PSG (p-doped silica glass), BSG (boron-doped silicon glass
Glass), BPSG (boron-phosphorosilicate glass) etc., the formation such as PVD, CVD, ALD, spin-coating method can be passed through.It is understood that being formed
The dielectric material for starting deposition when layer dielectric layer 310 is inevitably higher than stacking gate, therefore can be carried out when depositing the after of completing
Planarization Operation, such as CMP (chemically mechanical polishing), so that interlayer dielectric layer 310 and stacking gate are highly consistent.
Then, the oxide layer cap rock 311 for forming covering interlayer dielectric layer 310 and stacking gate, is formed by structure such as Figure 10 A
Shown in Figure 10 B.
Various suitable oxides, such as silica may be used in oxide layer cap rock 311, can by PVD, CVD,
The techniques such as ALD are formed.In the present embodiment, oxide layer cap rock 311 uses PEOX, that is, passes through plasma reinforced chemical vapour deposition
The oxide that technique is formed, can improve the uniformity on surface, be conducive to the completion of follow-up photoetching process.
Then, reversion contact hole etching is carried out, contact hole 312 is inverted to be formed, is formed by structure such as Figure 11 A and figure
Shown in 11B.
Illustratively, reversion contact hole 312 can be formed by following step：
First, graphical photoresist layer is formed on oxide layer cap rock 311, which defines reversion and connect
The shape of contact hole and position.Illustratively, in gap of the reversion contact hole between control gate 305, and it is located at drain contact
Between.
Then, pass through suitable wet method or dry etch process etching oxidation layer cap rock by mask of graphical photoresist layer
311 and interlayer dielectric layer 310, and stop on reversion contact etching stop layer 309, to form reversion contact hole 312.It is described
The wet etching wet-etching technologies such as including hydrofluoric acid, dry etching include but not limited to：Reactive ion etching (RIE),
Ion beam milling, plasma etching or laser cutting.Illustratively, in this embodiment, it is executed using dry etch process
The etching, and as an example, in the present embodiment, it is described to be etched to dry etching, the technological parameter packet of the dry etching
It includes：Etching gas includes the gases such as CF4, CHF3.
Then, patterned photoresist layer is removed, and is cleaned.
Then, the reversion contact hole 312 is filled with insulating materials, is formed by structure as illustrated in figs. 12 a and 12b.
Various suitable materials may be used in insulating materials, and opposite interlayer dielectric layer 310 has higher selectivity.Show
Example property, in the present embodiment insulating materials use silicon nitride, can by the formation such as furnace process, PVD, CVD, ALD, from
And insulating layer 313 is formed in inverting contact hole 312.
It is understood that in order to fill full reversion contact hole 312, the height of insulating layer 313 can be higher than oxide layer cap rock
311。
Then, the part that etch-back removal insulating layer 313 is higher than oxide layer cap rock 311 is executed, is formed by structure as schemed
Shown in 13A and Figure 13 B.
Illustratively, it is that stop-layer executes eatch-back by suitable wet method or dry etch process with oxide layer cap rock 311
It carves, to remove the part that insulating layer 3132 is higher than oxide layer cap rock 311.
Then, planarization is executed, to remove removing oxide layer cap rock 311 and partial insulative layer 313, is formed by structure as schemed
Shown in 14A and Figure 14 B.
Illustratively, removing oxide layer cap rock 311 and part are gone to by flatening process such as CMP (chemically mechanical polishing)
Insulating layer 313, and stopping on reversion contact etching stop layer 309, to improve surface evenness, and after making planarization
Insulating layer 312 and stacking gate are highly consistent.
Then, the interlayer dielectric layer 310 for removing contact bore region to be formed is connect with forming source contact openings 314A and drain electrode
Contact hole 314B is formed by structure as shown in fig. 15 a and fig. 15b.
Illustratively, the interlayer dielectric layer of contact bore region to be formed is etched by hydrofluoric acid (HF) wet-etching technology
310, to form source contact openings 314A and drain contact hole 314B.In the present embodiment, source contact openings 314A is perpendicular
Long channel form, drain contact hole 314B are perpendicular poroid.
Although it is understood that in abovementioned steps in order to ensure removal higher than stacking gate 311 He of oxide layer cap rock
Insulating layer 313 can execute grinding when being planarized, be located at the reversion at the top of stacking gate and at the top of clearance wall 307A in this way
Contact etching stop layer 309 can be removed, but since clearance wall 307A top areas are all carved by having with interlayer dielectric layer 310
The material (silicon nitride) of erosion selectivity is constituted, when using wet processing to remove interlayer dielectric layer 310 in this step so just not
Gap can be formed in clearance wall 307A top areas again.
Then, the part that the reversion contact etching stop layer 309 is located at 300 surface of the semiconductor substrate is removed, is protected
The part 309A on the stacking gate side wall is stayed, is formed by structure as shown in Figure 16 A and Figure 16 B.
Illustratively, it is located at half by suitable dry etching or physical bombardment removal reversion contact etching stop layer 309
The part on 300 surface of conductor substrate, to expose 300 surface of semiconductor substrate, to be subsequently formed source and drain contact.
Finally, source contact openings 314A and drain contact hole 314B is filled with conductive material, to form source contact
315A and drain contact 315B is formed by structure as shown in Figure 17 A and Figure 17 B.
Illustratively, the conductive material is tungsten (W), and filling process is, for example,：It is initially formed adhesion layer, then viscous
By the process deposits tungsten such as CVD on attached layer, part of the planarization Operation removal higher than stacking gate is finally executed.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device includes not only above-mentioned steps, before above-mentioned steps, among or may also include other needs later
The step of, such as LDD injections, source-drain electrode formed
According to the production method of the semiconductor devices of the present embodiment, the oxidation of grid gap wall top area is removed first
Layer, then refills the top area, has with interlayer dielectric layer so that the material of clearance wall top area is all
The material of Etch selectivity, just will not be on clearance wall top when forming source and drain contact hole subsequently through reversion contact etching technique in this way
Portion forms gap, so as to avoid when forming source and drain contact conductive material be also filled into clearance wall top area and lead to grid
Pole and the breakdown voltage between source/drain reduce, and improve the performance and yield of device.
Embodiment two
The present invention also provides a kind of semiconductor devices made using the above method, should be partly as shown in Figure 17 A and Figure 17 B
Conductor device includes：Semiconductor substrate 300 is formed with stacking gate in the semiconductor substrate 300, in the stacking gate 300
Side wall on be formed with clearance wall 307A；The interlayer dielectric for surrounding the stacking gate is formed in the semiconductor substrate 300
Layer；Source contact 315A and drain contact 315B is formed in the interlayer dielectric layer；Wherein, the top regions the clearance wall 307A
Domain is all by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.
Isolation structure 301 in semiconductor substrate 300 can be shallow trench isolation (STI) structure or selective oxidation silicon
(LOCOS) isolation structure can be formed by method commonly used in the art, to define and separate active area.As an example,
Isolation structure 301 uses shallow trench isolation (STI) structure.Tunnel oxide 302 is illustratively silicon oxide layer
Stacking gate includes the floating boom 303 for stacking gradually setting, dielectric layer 304, control gate 305 and control gate hard mask layer
306, wherein floating boom 303 is close to semiconductor substrate 300, and 305 source and drain semiconductor substrate 300 of control gate.Illustratively, floating boom
303 and control gate 305 to use the semi-conducting material such as polysilicon, dielectric layer 304 be such as the dielectrics material such as oxide, nitride
Material, it is preferable that in the present embodiment, dielectric layer 304 is both had in this way using ONO structure (that is, oxidenitride oxide)
There is good interface performance, it may have good dielectric properties and suitable thickness.
Clearance wall 307A is formed on the side wall of stacking gate, and clearance wall 307A top areas all by with the interlayer
There is dielectric layer the material of Etch selectivity to constitute.Illustratively, the bottom section of clearance wall 307A includes the first oxide layer
3070, nitration case 3071 and the second oxide layer 3072.Common oxide and nitride, example may be used in oxide layer and nitration case
Such as silica, silicon nitride, silicon oxynitride.The all silicon nitrides of top area of clearance wall 307A.
The perpendicular long channel forms of source contact 315A, drain contact 315B are perpendicular poroid.Adjacent drain contact 315B
Between be isolated by insulating layer 313.
The semiconductor devices of the present embodiment can reduce to avoid the breakdown voltage between grid and source/drain, thus performance
It is improved with yield.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, which includes：Semiconductor substrate is formed with heap on the semiconductor substrate
Gatestack is formed with clearance wall on the side wall of the stacking gate；It is formed on the semiconductor substrate and surrounds the stacking gate
Interlayer dielectric layer；Source contact and drain contact are formed in the interlayer dielectric layer；Wherein, the clearance wall top area
All by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or for silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode can also be the metal interconnection structure, etc. being electrically connected with transistor.In addition, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure.As an example, in the present embodiment, the constituent material of semiconductor substrate selects monocrystalline silicon.
Isolation structure can be shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure, can be with
It is formed by method commonly used in the art, to define and separate active area.As an example, using shallow trench isolation in isolation structure
(STI) structure.
Stacking gate includes floating boom, dielectric layer, control gate and hard mask layer etc. for example, by using described in the embodiment of the present invention one
Production method formed, details are not described herein.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products for including the semiconductor devices.
Wherein, Figure 18 shows the example of mobile phone.The outside of mobile phone 400 is provided with the display portion being included in shell 401
402, operation button 403, external connection port 404, loud speaker 405, microphone 406 etc..
The electronic device of the embodiment of the present invention, by included semiconductor devices can to avoid grid and source/drain it
Between breakdown voltage reduce, thus performance and yield improve, thus the electronic device equally have the advantages that it is similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of production method of semiconductor devices, which is characterized in that including：
Semiconductor substrate is provided, stacking gate is formed on the semiconductor substrate, gap is formed on the side wall of the stacking gate
Wall；
The interlayer dielectric layer for surrounding the stacking gate is formed on the semiconductor substrate；
Source contact and drain contact are formed in the interlayer dielectric layer；
Wherein, the clearance wall top area is all by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.
2. the production method of semiconductor devices according to claim 1, which is characterized in that described in the side of the stacking gate
Clearance wall is formed on wall includes：
Primary clearance wall is formed on the side wall of the stacking gate, the primary clearance wall includes at least layer of oxide layer；
Remove the part that the oxide layer in the primary clearance wall is located at the clearance wall top area；
There is the top area that the material of Etch selectivity fills the clearance wall with the interlayer dielectric layer, so that between described
Gap wall top area is all by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.
3. the production method of semiconductor devices according to claim 2, which is characterized in that the removal primary clearance
The part that oxide layer in wall is located at the clearance wall top area includes：
The filled layer for surrounding and covering the stacking gate is formed in the semiconductor substrate；
The part filled layer is removed to expose the top area of the stacking gate and primary clearance wall；
The part that the oxide layer in the primary clearance wall is located at the clearance wall top area is removed using wet processing；
Remove the remaining filled layer.
4. the production method of semiconductor devices according to claim 2, which is characterized in that the primary clearance wall include according to
The first oxide layer, nitration case and the second oxide layer of secondary stacking.
5. the production method of semiconductor devices according to claim 3, which is characterized in that the filled layer is organic filling
Layer.
6. the production method of semiconductor devices according to claim 2, which is characterized in that have with the interlayer dielectric layer
The material of Etch selectivity is nitride.
7. the production method of semiconductor devices according to claim 2, which is characterized in that further include forming covering described half
Reversion contact etching stop layer at the top of conductor substrate surface, clearance wall and the stacking gate.
8. the production method of semiconductor devices according to claim 7, which is characterized in that it is described with the interlayer dielectric
There is layer the step of material of Etch selectivity fills the top area of the clearance wall to stop with formation reversion contact etching
Only the step of layer is completed in same step.
9. the production method of semiconductor devices according to claim 7 or 8, which is characterized in that the reversion contact etching
Stop-layer is formed by furnace process.
10. the semiconductor devices that a kind of production method using as described in any one of claim 1-9 makes, feature exist
In, including：
Semiconductor substrate is formed with stacking gate on the semiconductor substrate, and gap is formed on the side wall of the stacking gate
Wall；
It is formed with the interlayer dielectric layer for surrounding the stacking gate on the semiconductor substrate；
Source contact and drain contact are formed in the interlayer dielectric layer；
Wherein, the clearance wall top area is all by with the interlayer dielectric layer there is the material of Etch selectivity to constitute.
11. semiconductor devices according to claim 10, which is characterized in that the top area of the clearance wall is all by nitrogen
Compound is constituted.
12. a kind of electronic device, which is characterized in that include semiconductor devices as described in claim 10 or 11 and with it is described
The electronic building brick that semiconductor devices is connected.
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